JPH11186261A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance a wiring layer structure in reliability in the manufacture of a semiconductor device, by a method wherein voids are prevented from being generated in a Cu buried wiring layer or a Cu plug, and the Cu buried wiring layer or the Cu plug is enhanced in grain size so as to improve resistance to electromigration. SOLUTION: A recess 3 is provided to an insulating layer 2 formed on a board 1 so as to provide a wiring layer or a plug into it, a Cu layer 5 is filled in the recess 3 through the intermediary of a base conductive film 4, a disused part of the Cu layer 5 is removed through a chemical mechanical polishing method for the formation of a Cu buried layer 6, and then impurities are removed from the Cu buried layer 6 through a thermal treatment.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a Cu plating layer by CMP.
(Chemical Mechanical Poli
The present invention relates to a method for manufacturing a semiconductor device characterized by a heat treatment step of improving the electromigration resistance of a buried wiring layer buried in a recess by a shing method.

[0002]

2. Description of the Related Art Conventionally, as an interconnect layer of a semiconductor device, an interconnect layer mainly made of an Al alloy has been used. Therefore, the use of Cu, which has lower resistance than Al and excellent electromigration resistance, has been studied.

In the case of forming such a fine wiring layer using Cu, in a dry etching method required for fine processing, there is an appropriate gas for etching Cu with a high selectivity to an insulating film serving as a base. For this reason, forming a buried wiring layer structure by a damascene method has become mainstream.

[0004] The damascene method means that a concave portion such as a wiring layer groove or a via hole is provided in an insulating film, and the entire surface is subjected to an electrolytic plating method or a CV using Cu (hfac) TMVS or the like.
After depositing a thick Cu layer by the D method, the Cu layer deposited in the region other than the concave portion is removed by the CMP method to form a Cu buried wiring layer embedded in the concave portion. As a method of forming a thick Cu layer, a method of depositing a Cu layer by a sputtering method and then reflowing the Cu layer has been proposed.

[0005] Such a Cu embedded wiring layer has a short history, and there are many problems that have not been revealed yet. For example, impurities resulting from the manufacturing method are contained in the formed Cu layer, and grains (crystal grains) are formed. There is a problem that the growth of Cu is insufficient, the grains are small, and there are many triple points, which shortens the life of the Cu embedded wiring layer due to electromigration.

For example, when a Cu layer is deposited by an electroplating method, moisture and components of a plating bath are mixed in the Cu layer, and when a Cu layer is deposited by a CVD method, Cu (hfac A) When an organic substance or the like due to TMVS or the like is mixed or deposited by a sputtering method,
Atmosphere components such as r are mixed.

For this reason, in order to improve the electromigration resistance of the Cu embedded wiring layer, an attempt was made to increase the grain size by performing an annealing process after depositing the Cu layer. I do. FIG. 12 is a schematic sectional view taken along a plane perpendicular to the extending direction of the wiring layer.

Referring to FIG. 12A, first, an LTO to be a base oxide film 72 is formed on a silicon substrate 71 by PCVD (plasma enhanced chemical vapor deposition).
(Low-temperature-grown SiO ₂ film), and then PC
A SiN film 73 serving as an etching stopper layer and an SiO ₂ film 74 serving as an oxide layer separating oxide film are deposited by using the VD method, and then SiN is formed by RIE (reactive ion etching) using a resist pattern (not shown) as a mask.
After forming a recess reaching the film 73, the resist pattern and the exposed SiN film 73 are removed to form a wiring layer groove 75.

Next, after depositing a TaN film 76 serving as a barrier metal by a sputtering method, a Cu seed film 77 serving as a seed in an electrolytic plating step is also deposited by a sputtering method, and then a thick Cu film is formed by an electrolytic plating method. A plating layer 78 is deposited.

Next, heat treatment is performed in an H ₂ atmosphere, that is, in a reducing atmosphere to increase the grain size of the Cu plating layer 78.

Then, polishing is performed by CMP until the surface of the SiO ₂ film 74 is exposed, and the Cu plating layer 78, the Cu seed film 77, And T
After removing the aN film 76, a Cu embedded wiring layer 79 is formed.

By performing such a process for the upper wiring layer and the Cu plug for making a connection with the upper wiring layer, a multilayer wiring structure using the Cu embedded wiring layer can be formed.

[0013]

However, the conventional CMP
In the method, voids are generated by heat treatment, or the grain growth is not sufficient, and the grain size is still small, so that electromigration resistance is low, and the reliability of the Cu embedded wiring layer is low. There is.

As a result of the study, it was concluded that one of the causes of such voids was that heat treatment was performed before the CMP step in which the large-capacity Cu plating layer 78 was present. This situation will be described with reference to FIGS.

FIG. 13 (a) and FIG. 13 (b) FIG. 13 (a) shows Cu deposited by electrolytic plating.
The amount of each degassed component released from the plating layer 78 is determined by TDS (T
thermal Desorption Spectro
FIG. 13B shows the amount of each degassed component released from the Cu layer deposited by the sputtering method for comparison. By performing the heat treatment step of FIG. 12B at 300 ° C. or more, the water (H ₂ O)
And the amount of released hydrogen (H ₂ ) has increased again. It is considered that the moisture and hydrogen contained in the inside were released along with the growth of the grains in the Cu plating layer 78. Note that carbon dioxide (CO ₂ ) is derived from organic components contained in the plating bath, and hydrogen is considered to be derived from moisture in view of the similarity of the intensity curves.

On the other hand, in the case of the sputtering method which is a physical deposition method, although impurities due to deposition conditions are eliminated, the emission amount is small, and the emission amount hardly increases even when the temperature rises. In addition, since the sensitivity of the measuring device differs for each gas component, the relative amount in the figure does not make much sense because the sensitivity of the measuring device differs for each gas component, and the amount of each degassed component represents the total amount of each gas component. The degree does not mean the total amount of the gas components shown in the figure.

14A and 14B. FIG. 14A shows a plane perpendicular to the extending direction of the wiring layer when polished by the CMP method after heat treatment as shown in FIG. FIG. 14 is a schematic sectional view taken
(B) is a schematic sectional view along the extension direction of the wiring layer. When the heat treatment is performed before the CMP step in which a large-capacity Cu plating layer is present, the growth of the grains 82 proceeds from both the surface of the Cu plating layer and the bottom part in contact with the TaN film 76, so that the growth of the grains 82 Insufficient and three grains 8 at a part of the grain boundary 81 which is the contact point
A triple point 83 where 2 overlaps occurs.

In such a Cu plating layer, FIG.
As shown in FIG. 3 (a), water (H
₂ O), carbon dioxide (CO ₂ ), or other impurities, and very fine voids due to these impurities pass through the grain boundaries 81 and condense.
It is considered that the void 80 is generated at the location shown in FIG. Further, when the grain growth proceeds from the surface of the Cu plating layer to the bottom, it is observed that voids 80 are generated on the bottom side.

As a result of various experiments, this void 80
It has been clarified that heat generation conditions are also involved in the occurrence of heat generation, and it often occurs during heat treatment at 300 ° C. or higher.

As other conditions, the higher the adhesion between the barrier metal and the seed film, the more difficult it is for the void 80 to be generated, and the higher the coverage of the seed film, the higher the void 80 becomes.
It is evident that copper is hardly generated, and a large amount of Cu deposited in regions other than the wiring layer trenches or via holes.
It is considered that the stress of the plating layer also affects the growth promotion of the void 80.

Further, it is clear that the generation of the void 80 also depends on the width of the wiring layer or the diameter of the via hole. For example, a Cu embedded wiring layer or a Cu plug having a width or diameter of 1.0 μm or less is used. In, the generation of voids 80 was observed.

Accordingly, an object of the present invention is to prevent the generation of voids in a Cu embedded wiring layer or a Cu plug, increase the grain size, increase electromigration resistance, and increase the reliability of the wiring layer structure. And

[0023]

FIG. 1 is an explanatory view of the principle configuration of the present invention. Referring to FIG. 1, means for solving the problems in the present invention will be described. The figure is a schematic cross-sectional view taken along a plane perpendicular to the extending direction of the wiring layer. 1 (a) to 1 (c) (1) In the present invention, a concave portion 3 for forming a wiring layer or a plug is provided in an insulating film 2 formed on a substrate 1, and an underlying conductive film 4 is formed in the concave portion 3. In a method of manufacturing a semiconductor device in which a Cu buried layer 6 is formed by filling a Cu layer 5 through a via hole and removing an unnecessary Cu layer 5 by a chemical mechanical polishing method, the unnecessary Cu layer 5 is removed. It is characterized in that heat treatment for removing impurities in the buried layer 6 is performed.

As described above, after the unnecessary Cu layer 5 is removed, that is, by performing the heat treatment after the CMP step, the influence of the stress due to the large-capacity Cu layer 5 deposited on the portions other than the recesses 3 in the heat treatment step. As a result, the adhesion to the underlying conductive film 4 is improved, and the generation of voids is suppressed.
Electromigration resistance is improved. The underlying conductive film 4 means a barrier metal or a barrier metal / seed film.

Further, since the growth of the grains is performed in a relatively narrow region such as the Cu buried layer 6, for example, the Cu buried wiring layer or the Cu plug, the grains are likely to be large in size, and the generation of the triple point is also likely to occur. Since it almost disappears,
Electromigration resistance is improved.

(2) Further, according to the present invention, in the above (1), the heat treatment for removing the impurities in the Cu buried layer 6 after removing the unnecessary Cu layer 5 is performed on the Cu buried layer 6. Before forming an insulating film.

When the width or diameter of the Cu buried layer 6 is large, it is desirable to perform such a heat treatment before forming an insulating film, for example, an interlayer insulating film on the Cu buried layer 6.
By performing heat treatment before the formation of the insulating film, the grain size (average crystal grain size) can be further increased.

(3) The present invention is characterized in that, in the above (2), the width or diameter of the Cu buried layer 6 is 1.0 μm or more.

The heat treatment before the formation of the insulating film is carried out by
This is particularly effective when the width or diameter of the u-embedded layer 6 is 1.0 μm or more. For example, the grain size can be about 2.0 μm.

(4) Further, according to the present invention, in the above (1), a heat treatment for removing impurities in the Cu buried layer 6 after removing the unnecessary Cu layer 5 is performed on the Cu buried layer 6. After forming an insulating film.

As described above, when the width or the diameter of the Cu buried layer 6 is small, it is desirable to perform the heat treatment after forming the insulating film on the Cu buried layer 6, and to perform the heat treatment after the formation of the insulating film. Thereby, generation of voids can be suppressed.

(5) The present invention is characterized in that in (4) above, the width or diameter of the Cu buried layer 6 is 1.0 μm or less.

The heat treatment after the formation of the insulating film is carried out by C
This is particularly effective when the width or diameter of the u-embedded layer 6 is 1.0 μm or less, and although the grain size is not so large due to the width or diameter of the Cu-embedded layer 6, voids are not generated, The life of the Cu buried layer 6 is improved.

(6) In the present invention, in the above (4), the Cu buried layer 6 may be a Cu buried layer 6 having a width or a diameter of 1.0 μm or more and a Cu buried layer 6 having a width or a diameter of 1.0 μm or less. Cu
C including a buried layer 6 and having a width or a diameter of 1.0 μm or more.
The average crystal grain size in the u buried layer 6 is 1.
It is characterized by being larger than the average crystal grain size in the Cu buried layer 6 of 0 μm or less.

As described above, the Cu buried layer 6 having a width or diameter of 1.0 μm or more and the Cu buried layer 6 having a width of 1.0 μm or less are used.
When both are mixed, it is also effective to perform heat treatment after forming the insulating film, giving priority to suppression of generation of voids.
In that case, the average crystal grain size (grain size) in the Cu buried layer 6 having a width or diameter of 1.0 μm or more is determined by the average crystal grain size in the Cu buried layer 6 having a width or diameter of 1.0 μm or less. Can be bigger.

(7) Further, according to the present invention, in any one of the above (1) to (6), a first insulating film is provided on the Cu buried layer 6, and a wiring layer is provided on the first insulating film. Alternatively, a concave portion for forming a plug is provided, the concave portion is filled with a Cu layer via an underlying conductive film, and an unnecessary Cu layer is removed by a chemical mechanical polishing method to form a Cu buried layer.
After depositing the above insulating film, a heat treatment for desorbing impurities in the Cu buried layer is performed to form a multilayer wiring structure.

As described above, by repeating any one of the above steps (1) to (6), a highly reliable multilayer wiring structure can be formed.

(8) The present invention is characterized in that in any one of the above (1) to (7), the Cu layer 5 is deposited by an electroplating method.

In such a heat treatment step, the Cu layer 5 is formed by a PVD (Physical Vapor Deposition) method such as a sputtering method, a CVD method, or the like.
The method is effective in the case of depositing by any method such as the electroless plating method, the electroless plating method, or the electrolytic plating method, but is particularly effective in the case of the electrolytic plating method in which the amount of impurities mixed into the Cu layer 5 is large.

(9) In the present invention according to (8), the substrate 1 is introduced into a heat treatment chamber at a temperature of 300 ° C. or less in the heat treatment step for removing impurities in the Cu buried layer 6. Thereafter, the temperature of the substrate 1 is increased at a rate of 20 ° C./min or less.

If such a heat treatment is performed rapidly, voids are generated. Therefore, the substrate 1 is introduced into a low-temperature heat treatment room at a temperature of 300 ° C. or less, and then the substrate 1 is heated at a slow temperature increase rate of 20 ° C./min or less. Is desirable.

(10) Further, according to the present invention, in the above (9), the heat treatment temperature in the heat treatment
Not less than the temperature in the processing step after formation, and from 300 to
The temperature is set to 500 ° C.

If the heat treatment temperature in such a heat treatment step is lower than the temperature of the treatment step after the formation of the Cu buried layer 6, the treatment step after the formation of the Cu buried layer 6, for example, the formation of an insulating film, As the grains grow again in the process,
Since there is a possibility that voids may be generated, the temperature needs to be raised to a higher temperature, and the desorption state of impurities, for example, moisture, hydrogen, or carbon dioxide from the Cu layer 5, that is, the degassing temperature From the characteristics, it is desirable to set the temperature to 300 to 500 ° C., and if it exceeds 500 ° C., diffusion of Cu becomes a problem. However, FSG (fluorine-containing S
When a low dielectric constant film such as an iO ₂ film), HSQ which is an inorganic SOG (spin on glass), or an organic insulating film is used, the temperature is preferably 450 ° C. or lower from the viewpoint of heat resistance.

(11) The present invention is characterized in that, in the above (10), the time during which the maximum temperature is reached is 5 to 2000 seconds in the heat treatment step.

As described above, the time during which the maximum temperature is reached is
If the time is not longer than 5 seconds, the growth of the grain is insufficient. On the other hand, if the time is longer than 2000 seconds, the generation of protrusions in the Cu buried layer 6 or the Cu
Is a problem.

(12) Further, the present invention is characterized in that in any one of the above (9) to (11), the atmosphere in the heat treatment step is a hydrogen atmosphere.

As described above, the atmosphere in the heat treatment step is
Recovery of the damaged layer in the CMP process and the Cu buried layer 6
Is preferably performed in a hydrogen atmosphere, that is, a reducing atmosphere in order to prevent oxidation of the surface.

(13) The present invention is characterized in that in any one of the above (9) to (11), the oxygen concentration of the atmosphere in the heat treatment step is set to 100 ppm or less.

As described above, the oxygen concentration in the atmosphere in the heat treatment step, for example, the hydrogen atmosphere, the nitrogen atmosphere, or the argon atmosphere may be 100 ppm or less in order to prevent the surface of the Cu buried layer 6 from being oxidized. It is desirable that the atmosphere be a hydrogen atmosphere.

[0050]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A process for forming a buried Cu wiring layer according to a first embodiment of the present invention will now be described with reference to FIGS. 2 and 3. The illustration of the configuration of the element region and the element isolation region formed on the silicon substrate is omitted in the drawing. Each drawing is a schematic cross-sectional view taken along a plane perpendicular to the extending direction of the wiring layer.

Referring to FIG. 2 (a), first, a P
Using a CVD method, for example, a 700 nm thick LTO
(Low-temperature-grown SiO ₂ film) is grown to form a base oxide film 12, and then, similarly, becomes a 50-nm-thick SiN film 13 and a wiring-layer-separating oxide film to be an etching stopper layer by using the PCVD method. For example, a 700 nm thick SiO ₂ film 14 made of LTO is deposited.

Next, using a resist pattern (not shown) as a mask, a recess reaching the SiN film 13 is formed by RIE using a mixed gas of C ₄ F ₈ + CO + Ar, and then the resist pattern and the exposed SiN film 1 are formed.
By removing 3, a wiring layer groove 15 having a width of 1.0 μm or more, for example, 10.0 μm is formed.

Next, as shown in FIG. 2B, a TaN film 16 serving as a barrier metal is deposited, for example, to a thickness of 20 nm by a sputtering method, and then, without breaking vacuum, Cu is used as a seed in an electroplating step by a sputtering method. Seed film 17
Is deposited, for example, to a thickness of 100 nm to form a base conductive film. The sputtering conditions in this case were 2 × 10
^-3 mm in Ar gas atmosphere at Torr
And a DC power of 12 kW was applied to the parallel plate electrodes.

In this case, once the TaN film 16 is deposited and once exposed to the air, a natural oxide film grows between the TaN film 16 and the Cu seed film 17 to be deposited next, and Since the adhesion is reduced, the TaN film 16 and C
It is desirable to continuously form the u seed film 17.

Next, as shown in FIG._TwoThickness on membrane 14
Is, for example, 1000 nm (1 μm) thick Cu
A plating layer 18 is deposited. In this case, the electric field
The conditions were as follows: a sulfuric acid bath, 2.5 A / (10 cm) ^Twoof
Rows with 100 ms cycle pulse current at current density
The growth rate was 400 nm / min.

Next, as shown in FIG. 3D, polishing is performed by a CMP method until the surface of the SiO ₂ film 14 is exposed, and the Cu plating layer 18, the Cu seed film 17, And T
The aN film 16 is removed, and a Cu embedded wiring layer 19 is formed.

Next, as shown in FIG. 3E, when the temperature is 300 ° C. or less, for example,
The silicon substrate 11 is introduced into a heat treatment chamber filled with 100% H ₂ gas of 00 Torr, and the temperature is raised at a rate of 20 ° C./min or less, for example, 6 ° C./min, to 300 to 500 ° C., for example, 390 ° C. Raise the temperature for 5 to 2000 seconds, for example,
Heat treatment is performed by holding for 120 seconds (2 minutes) to remove moisture, hydrogen, carbon dioxide, and the like contained in the Cu embedded wiring layer 19 and increase the grain size of the Cu embedded wiring layer 19.

As described above, in the first embodiment of the present invention, the heat treatment is performed after the CMP step and before the formation of the upper interlayer insulating film and the like. Since the grain size of No. 19 can be increased, the generation of triple points can be suppressed, and the generation of voids can be suppressed since the heat treatment conditions are set in the above-described appropriate range. In addition, the electromigration resistance can be improved.

The TaN film serving as a barrier metal is made of T
In order to confirm the effects of the first embodiment of the present invention, a TiN film was used as a barrier metal, a wiring layer having a width of 10 μm was formed, and various heat treatment conditions were used. The experiment was performed using.

As a result of this experiment, the average crystal grain size (grain size) in the Cu buried wiring layer when no heat treatment was performed was 0.9 μm, as in the first embodiment. When the heat treatment was performed before the insulating film was deposited, the grain size was 2.0 μm, which was about twice. Note that the heat treatment was performed at 350 ° C. for 2 minutes.

For comparison, after depositing the insulating film,
When heat treatment is performed at 400 ° C. for 30 minutes,
The grain size increases only to about 1.1 μm, and the effect of the present invention is clear.

Further, before depositing the insulating film, the temperature is set to 350 ° C.
In the case where the heat treatment is performed for 2 minutes at 400 ° C. and then the heat treatment is performed at 400 ° C. for 30 minutes after the deposition of the insulating film, the grains regenerate and grow, and the grain size becomes 2.2 μm. It was confirmed that heat treatment was effective at least before depositing the insulating film.

Next, a modification of the first embodiment of the present invention will be described with reference to FIG. Referring to FIG. 4A, as described in the first embodiment, when the Cu seed film 17 is formed by the sputtering method, the eaves 20 and the edge-shaped concave portions 21 are formed as shown in the drawing. Easy to be
When the eaves portion 20 and the edge-shaped concave portion 21 are excessively generated, when the Cu plating layer 18 is deposited by the electrolytic plating method, the Cu plating layer 18 may be sufficiently filled in the wiring layer groove 15. No, it will promote the generation of voids.

4B. Therefore, after the Cu seed film 17 is formed, the eaves portion 20 and the edge-shaped concave portion 21 are formed by performing reverse sputtering, that is, sputter etching in an inert gas such as Ar. It is desirable to make the shape as shown in FIG.

Next, a process for forming a Cu plug according to a second embodiment of the present invention will be described with reference to FIGS. 5 and 6. In order to simplify the description, an element formed on a silicon substrate will be described. A region, an element isolation region, a lower wiring layer connected to a Cu plug, and the like are not shown. Referring to FIG. 5A, first, similarly to the first embodiment, a silicon substrate 11 on which a predetermined element or the like is formed is formed by using a PCVD method.
For example, an LTO film having a thickness of 700 nm is grown to form a base oxide film 12, and then, similarly, a thickness serving as an etching stopper layer is reduced to, for example, 50 nm using a PCVD method.
The thickness consisting LTO film serving as the SiN film 13 and the interlayer insulating film, for example, depositing a SiO ₂ film 14 of 700 nm.

Next, using a resist pattern (not shown) as a mask, a recess reaching the SiN film 13 is formed by RIE using a mixed gas of C ₄ F ₈ + CO + Ar, and then the resist pattern and the exposed SiN film 1 are formed.
By removing 3, a via hole 22 having a diameter of 1.0 μm or less, for example, 0.6 μm, is formed.

Next, as shown in FIG. 5B, a TiN film 23 serving as a barrier metal is deposited, for example, to a thickness of 50 nm by a sputtering method. The membrane 17
For example, a base conductive film is formed by depositing 200 nm.
The sputtering conditions in this case are also 2 × 10 ⁻³ T
In an orr Ar gas atmosphere, a DC power of 12 kW was applied to a parallel plate electrode having a diameter of 290 mm.

Next, as shown in FIG._TwoThickness on membrane 14
Is, for example, 1000 nm (1 μm) thick Cu
A plating layer 18 is deposited. In this case, the electric field
The conditions are as follows: 2.5 A / (10 cm) using a sulfuric acid bath. ^Twoof
Rows with 100 ms cycle pulse current at current density
The growth rate was 400 nm / min.

Then, polishing is performed by CMP until the surface of the SiO ₂ film 14 is exposed, and the Cu plating layer 18, the Cu seed film 17, And T
The Cu plug 24 is formed by removing the iN film 23.

Next, referring to FIG. 6E, the thickness of the etching stopper layer is again reduced by the PCVD method, for example, to the thickness of the 50 nm SiN film 25 and the thickness of the LTO film serving as the wiring layer isolation oxide film. ,
For example, a 700 nm SiO ₂ film 26 is deposited.

Next, as shown in FIG. 6F, when the temperature is 300 ° C. or less, for example, 150 ° C.
The silicon substrate 11 is introduced into a heat treatment chamber filled with 100% H ₂ gas of 00 Torr, and the temperature is raised at a rate of 20 ° C./min or less, for example, 6 ° C./min, to 300 to 500 ° C., for example, 390 ° C. Heat treatment is performed by raising the temperature and holding for 30 to 2000 seconds, for example, 120 seconds (2 minutes) to remove moisture, hydrogen, carbon dioxide, and the like contained in the Cu plug 24 and increase the grain size. .

As described above, in the second embodiment of the present invention, since the heat treatment is performed after the CMP step and after forming the upper interlayer insulating film and the like, the diameter is 1.0
No void is generated during the heat treatment of the Cu plug 24 of μm or less.

The heat treatment after the formation of such an interlayer insulating film and the like is effective even for a fine Cu embedded wiring layer having a width of 1.0 μm or less, and the grain size in this case is Cu
Although the particle size is limited by the width of the buried wiring layer and is hardly larger than the particle size of the width, no void is generated and the electromigration resistance is improved.

For example, in order to confirm the effect of the second embodiment of the present invention, a wiring layer having a width of 0.35 μm was formed, and experiments were performed under various heat treatment conditions. In the fine wiring layer, the grain size is almost the same because the grain size is restricted by the wiring width. However, the generation state of voids is completely different, and therefore, the current test at 6 MA / cm ² at 250 ° C. Caused a great difference in the electromigration life.

As a result of this experiment, no void was generated in the Cu buried wiring layer where no heat treatment was performed, and the time to 50% failure was 1180 hours. When the heat treatment is performed after the deposition of the insulating film as in the second embodiment, no voids
The time to 0% failure was 1550 hours, and an improvement of 30% or more was obtained. The heat treatment was performed at a temperature rising rate of 20 ° C.
/ Min at 400 ° C. for 30 minutes.

For comparison, before depositing the insulating film,
When the temperature was raised at a rate of 60 ° C./min and the heat treatment was performed at 350 ° C. for 2 minutes, voids were observed,
The time to reach% failure was 103 hours, which was less than 1/10 of that when no heat treatment was performed.

Further, before depositing the insulating film, a heat treatment was performed at 350 ° C. for 2 minutes at a heating rate of 60 ° C./min.
When the heat treatment was performed at 0 ° C./min at 400 ° C. for 30 minutes, voids were observed, and the time to 50% failure was 147 hours, which was ８ of the case where no heat treatment was performed. In the case where the width of the wiring layer or the diameter of the plug is 1.0 μm or less, it was confirmed that it is effective to perform the heat treatment after depositing at least the insulating film. .

Next, with reference to FIGS. 7 to 11, a description will be given of a manufacturing process of a multilayer wiring layer structure using a Cu embedded wiring layer and a Cu plug according to a third embodiment of the present invention.
Basically, it is a repetition of the first embodiment and the second embodiment described above. For simplicity, the description will be made with a two-layer wiring layer structure. First, as shown in FIG. 7 (a), a P
Using a CVD method, for example, a 700 nm-thick LTO film is grown to form a base oxide film 32, and then,
The thickness of the etching stopper layer formed by the CVD method is, for example, 50 nm. The thickness of the SiN film 33 and the wiring layer separating oxide film is, for example, 700 nm.
An m ₂ SiO ₂ film 34 is deposited.

Next, using a resist pattern (not shown) as a mask, a recess reaching the SiN film 33 is formed by RIE using a mixed gas of C ₄ F ₈ + CO + Ar, and then the resist pattern and the exposed SiN film 3 are formed.
By removing 3, a wiring layer groove 35 having a width of 1.0 μm or more, for example, 1.2 μm, is formed.

Next, as shown in FIG. 7B, a TiN film 36 serving as a barrier metal is deposited, for example, to a thickness of 50 nm by a sputtering method. The membrane 37
For example, a base conductive film is formed by depositing 200 nm.

Next, referring to FIG. 7C, a thick Cu film having a thickness on the SiO ₂ film 34 of, for example, 1000 nm (1 μm) is formed by electrolytic plating.
A plating layer 38 is deposited.

Then, polishing is performed by CMP until the surface of the SiO ₂ film 34 is exposed, and the Cu plating layer 38, the Cu seed film 37, And T
The iN film 36 is removed, and a Cu embedded wiring layer 39 is formed.

Next, as shown in FIG. 8E, when the temperature is 300 ° C. or less, for example,
The silicon substrate 31 is introduced into a heat treatment chamber filled with 100% H ₂ gas of 00 Torr, and the temperature is raised at a rate of 20 ° C./min or less, for example, 6 ° C./min, to 300 to 500 ° C., for example, 390 ° C. A heat treatment is performed by raising the temperature and maintaining the temperature for 30 to 2000 seconds, for example, 120 seconds (2 minutes) to remove moisture, hydrogen, carbon dioxide, and the like contained in the Cu embedded wiring layer 39, and to perform Cu embedding. Embedded wiring layer 3
Increase the grain size of 9

Next, similarly, a 50 nm thick SiN film 40 serving as an etching stopper layer is similarly formed by the PCVD method.
After an SiO ₂ film 41 having a thickness of, for example, 700 nm made of an LTO film serving as an interlayer insulating film is deposited, C ₄ F ₈ is formed using a resist pattern (not shown) as a mask.
After forming a recess reaching the SiN film 40 by RIE using a mixed gas of + CO + Ar, the resist pattern and the exposed SiN film 40 are removed to form a via hole 42 having a diameter of 1.0 μm or less, for example, 0.6 μm. , 43 are formed.

Next, as shown in FIG. 9 (g), a TiN film 44 serving as a barrier metal is deposited, for example, to a thickness of 50 nm by a sputtering method. The membrane 45
For example, a base conductive film is formed by depositing 200 nm.

Referring to FIG. 9H, similarly to the step of FIG. 7C, the thickness on the SiO ₂ film 41 is set to, for example, 1000 n by electrolytic plating.
A thick Cu plating layer 46 having a thickness of m (1 μm) is deposited.

Then, polishing is performed by a CMP method until the surface of the SiO ₂ film 41 is exposed, and the Cu plating layer 46, the Cu seed film 45, and the Cu seed layer 45 deposited in regions other than the via holes 42 and 43 are polished. , TiN film 44 is removed to form Cu plugs 47 and 48.

Next, referring to FIG. 10 (j), the thickness of the etching stopper layer is again reduced by the PCVD method, for example, to the thickness of the 50 nm SiN film 49 and the thickness of the LTO film serving as the wiring layer isolation oxide film. ,
For example, a 700 nm SiO ₂ film 50 is deposited.

Next, as shown in FIG. 10 (k), a recess reaching the SiN film 49 is formed by RIE using a mixed gas of C ₄ F ₈ + CO + Ar using a resist pattern (not shown) as a mask. After formation, resist pattern and exposed S
By removing the iN film 49, the width becomes 0.2 to 10
Various wiring layer grooves 51 in the range of μm, and via holes 52 having a diameter of 1.0 μm or less, for example, 0.6 μm, as necessary, are formed. The concave portion for the Cu plug 48 is not the via hole 52 but has a width of 1.0 μm or less.
For example, the wiring layer groove may be 0.6 μm.

Next, a TiN film 53 serving as a barrier metal is deposited, for example, to a thickness of 50 nm by a sputtering method, and then a Cu seed film 54 serving as a seed in an electroplating step is formed by a sputtering method without breaking a vacuum. An underlying conductive film is formed by depositing 200 nm, and then the thickness on the SiO ₂ film 50 is set to, for example, the electrolytic plating method as in the step of FIG.
A thick Cu plating layer (not shown) having a thickness of 1000 nm (1 μm) is deposited.

Next, the SiO ₂ film 5 is formed by the CMP method.
Polishing until the surface of No. 0 is exposed, and a Cu plating layer deposited in a region other than the wiring layer groove 51 and the via hole 52;
After removing the Cu seed film 54 and the TiN film 53, C
A u-buried wiring layer 55 and a Cu plug 56 are formed.

Next, after depositing an SiN film 57 having a thickness of, for example, 50 nm by PCVD, the temperature is set to 300 ° C. or less, for example, 150 ° C. and 100 Torr.
The silicon substrate 11 is introduced into a heat treatment chamber filled with H ₂ gas mixed with 3% N ₂ , and the temperature is raised at a rate of 20 ° C./min or less, for example, 6 ° C./min, and 300 to 500 ° C., for example. Temperature to 400 ° C. for 5 to 2000 seconds, for example, 3
A heat treatment is performed by holding for 0 minute (1800 seconds) to increase the grain size of the Cu embedded wiring layer 55, the Cu plug 56, and the lower Cu plugs 47 and 48.

In this heat treatment step, since the Cu buried wiring layer 39 undergoes another heat treatment, as described in the description of the effect of the first embodiment, the grains grow again, and the grain size becomes larger. And the electromigration resistance increases.

11 (a) and 11 (b). FIG. 11 is a diagram for schematically explaining a state of a grain boundary according to the third embodiment of the present invention.
FIG. 11B is a schematic cross-sectional view taken along a plane perpendicular to the extension direction of the final wiring layer, and FIG.
FIG. 4 is a schematic cross-sectional view along the extension direction of a Cu embedded wiring layer 55.

In this case, the size of the grains 59 is increased, and the grain boundaries 58 are arranged in a direction perpendicular to the direction in which the Cu buried wiring layer 55 extends.
This indicates that the electromigration resistance is improved.

In the third embodiment, in the step of forming the upper wiring layer, a wiring layer having a width of 1.0 μm or more and a wiring layer of 1.0 μm or less are mixed. It is effective to perform a heat treatment before the insulating film, that is, the SiN film 57 covers the Cu buried wiring layer 55 and the Cu plug 55.

In such a heat treatment step, 1.
As described above, the grain size in the Cu embedded wiring layer having a width of 0 μm or more slightly increases, so that the grain size in the Cu embedded wiring layer having a width of 1.0 μm or less is restricted by the width of the wiring layer. For example, the grain size in a Cu embedded wiring layer or Cu plug having a width or a diameter of 1.0 μm or more is one of the grain size in a Cu embedded wiring layer having a width or a diameter of 0.5 μm. .5 times or more.

When the widths of all the wiring layers including the lower wiring layer and the diameters of all the via holes are set to 1.0 μm or less, all the heat treatment steps may be performed collectively at the end. The heat treatment process is simplified.

Although the embodiment of the present invention has been described above, the present invention is not limited to the configuration described in the embodiment, and various modifications are possible. For example, the barrier metal is a TiN film instead of a TaN film, or a TiN film.
A TaN film may be used in place of the N film, and a TaN film is excellent in terms of barrier characteristics. Further, a WN film or a TiSiN film may be used.

In the description of each of the above embodiments, a barrier metal such as a TiN film is deposited by a sputtering method. However, the present invention is not limited to the sputtering method. ) May be used.

In the above embodiments, the Cu seed film is deposited by the sputtering method. However, the present invention is not limited to the sputtering method.
It may be deposited by MOCVD or electroless plating.

Further, as described above, since the adhesion between the barrier metal and the seed film affects the generation of voids, in order to increase the adhesion between the barrier metal and the seed film, the adhesion between the barrier metal and the seed film is increased. Al, Ti, T of about 20 nm
It is effective to form a, Zr or W.

In the description of each of the above embodiments, pure Cu is used as the Cu seed film. However, the present invention is not limited to pure Cu.
At least one of Zr, Ti, Al, or W may be mixed in at 5% by weight or less. By mixing these elements, Cu becomes difficult to move, thereby suppressing an increase in crystal grain size and improving adhesion. It becomes possible to do.

In the description of each of the above embodiments, the Cu buried layer is deposited by the electroplating method. However, the present invention is not limited to the electroplating method.
ac) It may be deposited by a PVD method such as an MOCVD method or a sputtering method using TMVS, or an electroless plating method. In these cases, a Cu seed film is not necessarily required.

In particular, when depositing by electroless plating, sulfuric acid containing copper sulfate at 25 ° C. and forcolic acid as a reducing agent or EDTA (ethylenediaminetetraacetic acid) and formaldehyde at about 60 ° C. The film may be formed by dipping in dicopper.

In the case where these other deposition methods are used, impurities such as MOCV,
Since an organic component accompanying the method D, an atmospheric gas such as Ar accompanying the sputtering method, or moisture accompanying the plating bath is included, a heat treatment is effective for increasing the grain size.

In the description of each of the above embodiments, an LTO film formed at a low temperature is used as an interlayer insulating film or a wiring layer separation film in consideration of the influence on a Cu buried layer. However, it is not limited to the LTO film.
SG (fluorine-containing SiO ₂ film), inorganic S containing hydrogen
HSQ which is OG, or a low dielectric constant film such as an organic insulating film may be used. By using such a low dielectric constant film, a parasitic capacitance between wiring layers can be reduced. Thereby, a delay in operation speed can be prevented. However, when such a low dielectric constant film is used, particularly when HSQ or an organic insulating film is used, the heat treatment temperature should be 450 ° C. or less from the viewpoint of the heat resistance of the low dielectric constant film. desirable.

In the case of forming a multi-layer wiring structure as in the third embodiment, due to the heating temperature in the step of forming the interlayer insulating film, the grains of the already formed Cu buried wiring layer may be more than necessary. It is desirable that the film be formed at a temperature as low as possible because
It is desirable to form the film at a temperature lower than the heat treatment temperature for degassing the u-buried wiring layer, for example, at about 300 ° C.

The heat treatment atmosphere is 100% H
₂ atmosphere or an H ₂ atmosphere containing 3% N ₂ , but may be performed in another atmosphere, for example, an N ₂ atmosphere or an inert gas atmosphere such as an Ar atmosphere. Also in this case, the oxygen concentration in the atmosphere is desirably 100 ppm or less in order to prevent oxidation of the surface of the Cu buried layer.

[0110]

According to the present invention, the Cu buried wiring layer and the C
When the u plug is formed by the CMP method, the heat treatment is performed after removing the extra Cu layer by the CMP method, so that no void is generated in the Cu embedded wiring layer and the Cu plug, and the Cu plug is formed. Since the triple point can be reduced by increasing the grain size of the embedded wiring layer and the Cu plug, the electromigration resistance is improved,
Thereby, the reliability of a high-speed and high-integration semiconductor integrated circuit device using low-resistance Cu as a wiring layer can be improved.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a basic configuration of the present invention.

FIG. 2 is an explanatory diagram of a manufacturing process partway through the first embodiment of the present invention.

FIG. 3 is an explanatory view of a manufacturing process of the first embodiment of the present invention after FIG. 2;

FIG. 4 is an explanatory diagram of a modified example of the first embodiment of the present invention.

FIG. 5 is an explanatory diagram of a manufacturing process partway through a second embodiment of the present invention.

FIG. 6 is an explanatory diagram of a manufacturing process of the second embodiment of the present invention after FIG. 5;

FIG. 7 is an explanatory diagram of a manufacturing process partway through a third embodiment of the present invention.

FIG. 8 is an explanatory diagram of a manufacturing process of the third embodiment of the present invention up to the middle of FIG. 7;

FIG. 9 is an explanatory view of a manufacturing process of the third embodiment of the present invention up to the middle of FIG. 8;

FIG. 10 is an explanatory diagram of a manufacturing process of the third embodiment of the present invention after FIG. 9;

FIG. 11 is an explanatory diagram of a grain boundary according to a third embodiment of the present invention.

FIG. 12 is an explanatory diagram of a manufacturing process of a conventional CMP method.

FIG. 13 is an explanatory diagram of gas components desorbed by heat treatment.

FIG. 14 is an explanatory diagram of a problem in a conventional CMP method.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 substrate 2 insulating film 3 concave portion 4 underlying conductive film 5 Cu layer 6 Cu buried layer 11 silicon substrate 12 underlying oxide film 13 SiN film 14 SiO ₂ film 15 wiring layer groove 16 TaN film 17 Cu seed film 18 Cu plating layer 19 Cu embedded wiring layer 20 Eave portion 21 Edge-shaped concave portion 22 Via hole 23 TiN film 24 Cu plug 25 SiN film 26 SiO ₂ film 31 Silicon substrate 32 Base oxide film 33 SiN film 34 SiO ₂ film 35 Wiring layer groove 36 TiN film 37 Cu seed film 38 Cu plating layer 39 Cu buried wiring layer 40 SiN film 41 SiO ₂ film 42 Via hole 43 Via hole 44 TiN film 45 Cu seed film 46 Cu plating layer 47 Cu plug 48 Cu plug 49 SiN film 50 SiO ₂ film 51 Wiring Layer groove 52 Via hole 53 TiN film 54 Cu De film 55 Cu buried wiring layer 56 Cu plug 57 SiN film 58 grain boundary 59 grains 71 silicon substrate 72 underlying oxide film 73 SiN film 74 SiO ₂ film 75 wiring layer trench 76 TaN film 77 Cu seed film 78 Cu plated layer 79 Cu embedded wiring layer 80 void 81 grain boundary 82 grain 83 triple point

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Koji Endo 4-1-1, Kamidadanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Nobuhiro Misawa 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture No. 1 Inside Fujitsu Limited (72) Inventor Kenko Mizushima 4-1-1 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside 1-1 Fujitsu Limited (72) Satoshi Murakami 4-chome, Kamikodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture No. 1 in Fujitsu Limited (72) Inventor Anthony Hobbs 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited

Claims (13)

[Claims] An insulating film formed on a substrate is provided with a concave portion for forming a wiring layer or a plug, and the concave portion is filled with a Cu layer via an underlying conductive film, and unnecessary Cu is removed by a chemical mechanical polishing method. In a method for manufacturing a semiconductor device in which a Cu buried layer is formed by removing a layer, a heat treatment for removing impurities in the Cu buried layer is performed after removing the unnecessary Cu layer. Semiconductor device manufacturing method. 2. A heat treatment for removing impurities in the Cu buried layer after the unnecessary Cu layer is removed,
2. The method according to claim 1, wherein the method is performed before forming an insulating film on the buried layer. 3. The width or diameter of the Cu buried layer is 1.
3. The method for manufacturing a semiconductor device according to claim 2, wherein the thickness is 0 μm or more. 4. After the unnecessary Cu layer is removed, a heat treatment for desorbing impurities in the Cu buried layer is performed by the Cu heat treatment.
2. The method according to claim 1, wherein the method is performed after forming an insulating film on the buried layer. 5. The width or diameter of the Cu buried layer is as follows:
5. The method for manufacturing a semiconductor device according to claim 4, wherein the thickness is 0 μm or less. 6. The Cu buried layer having a width or a diameter of 1.
Cu embedded layer of 0 μm or more and width or diameter of 1.0 μm
The following width or diameter is 1.0.
5. The method of manufacturing a semiconductor device according to claim 4, wherein the average crystal grain size in the Cu buried layer having a size of not less than μm is larger than the average crystal grain size in the Cu buried layer having a width or a diameter not more than 1.0 μm. 7. A first insulating film is provided on the Cu buried layer, a concave portion for forming a wiring layer or a plug is provided in the first insulating film, and the concave portion is provided with a base conductive film therebetween. Cu
After filling the layer and removing an unnecessary Cu layer by a chemical mechanical polishing method to form a Cu buried layer, depositing a second insulating film, and removing impurities in the Cu buried layer. 7. The method according to claim 1, wherein the heat treatment is performed to form a multilayer wiring structure. 8. The method according to claim 1, wherein the Cu layer is deposited by an electrolytic plating method.
13. The method for manufacturing a semiconductor device according to the above item. 9. In a heat treatment step for desorbing impurities in the Cu buried layer, the substrate is introduced into a heat treatment chamber at a temperature of 300 ° C. or less, and then the temperature is increased at a rate of 20 ° C./min or less. 9. The method according to claim 8, wherein the substrate is heated. 10. The heat treatment temperature in the heat treatment step is equal to or higher than the temperature in the subsequent treatment steps, and
The method according to claim 9, wherein the temperature is set to 00 to 500 ° C. 10. 11. The method of manufacturing a semiconductor device according to claim 10, wherein in the heat treatment step, the time during which the temperature reaches the maximum temperature is 5 to 2000 seconds. 12. The method of manufacturing a semiconductor device according to claim 9, wherein the atmosphere in the heat treatment step is a hydrogen atmosphere. 13. The method of manufacturing a semiconductor device according to claim 9, wherein the oxygen concentration in the atmosphere in the heat treatment step is set to 100 ppm or less.