JPH11185487A - Semiconductor memory device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To increase the number of rewritable times and retention time. Kind Code: A1 A semiconductor memory device for storing data to be held for a long time or data with a large number of rewrites in a plurality of memory cell arrays including memory cells having the same address, wherein the data pin inputs and outputs n-bit data. 200, a special sector data pin 201 for inputting and outputting special sector data, a special sector control pin 202 to which a control signal indicating that the special sector data has arrived is applied, A switch group 203 including a plurality of switches to which 1-bit data in the data and the data from the special sector data pin are applied, n memory cell arrays 204, sense amplifier groups 205, and current source transistors 314 , A first transistor group, a reference voltage source, and a comparison circuit 206.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device that can reliably read cell information even if the number of rewritable times is increased or the holding time is long.

[0002]

2. Description of the Related Art In recent years, FeRAM (Ferro-electric Ran)
dom Access Memory), EPROM (Erasable and Pro
Grammable Read Only Memory), EEPROM (Electr
ical Erasable and Programmable Read Only Memory)
Non-volatile semiconductor memories such as these have attracted attention. EPR
In OM and EEPROM, electric charge is stored in the floating gate,
Data is stored by detecting a change in threshold voltage due to the presence or absence of electric charges by the control gate. The EEPROM includes a flash EEPROM that erases data in the entire memory chip or divides a memory cell array into arbitrary blocks and erases data in each block unit.

[0003] Memory cells constituting a flash EEPROM are roughly classified into a split gate type and a stacked gate type. Split gate type flash EE
A PROM is disclosed in WO 92/18980 (G11C 13/00). FIG. 2 shows the publication (WO92 / 1898).
0) Split gate type memory cell 1
01 shows a cross-sectional structure.

An N-type source S and a drain D are formed on a P-type single crystal silicon substrate 102. Source S
A floating gate FG is formed on a channel CH sandwiched between the gate and the drain D via a first insulating film 103. The control gate CG is formed over the floating gate FG with the second insulating film 104 interposed. Part of the control gate CG is arranged on the channel CH via the first insulating film 103,
The selection gate 105 is configured. Second insulating film 104
The data is stored by storing electrons in the floating gate FG surrounded by.

[0005]

In the case where electrons are stored in the floating gate FG, the cell current flowing through the memory cell decreases as the number of times of rewriting increases, so that stable writing and reading of data cannot be performed. This is because the second insulating film 1
04 is deteriorated, making it difficult for electrons to escape from the floating gate FG.
And then return to the floating gate FG again, the potential of the floating gate FG decreases, and the floating gate F
This is probably because a channel is formed under G, which makes it difficult.

[0006] This deterioration differs from cell to cell and has variations. If it is extremely bad, reading cannot be performed. This problem is remarkable in a nonvolatile semiconductor memory device, but cell information may not be read due to a defect of a memory cell even in a normal semiconductor memory device. A problem arises when important data is stored in such a memory cell.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned problems, and it is intended that a plurality of memory cell arrays having memory cells having the same address have data and rewrite counts to be held for a long period of time. A data pin for inputting / outputting n-bit data, a data pin for special sector for inputting / outputting data for a special sector, and a data pin for inputting / outputting the data for the special sector. A special sector control pin to which a control signal is applied, a switch group including a plurality of switches to which 1-bit data of the n-bit data and data from the special sector data pin are applied, N memory cell arrays for storing n-bit data from a group; A sense amplifier group for amplifying n-bit data from the memory cell array; a current source transistor; A reference voltage source for generating a voltage near an intermediate value of the voltage values according to the sum of the read currents of the n-bit data; and a voltage at a connection point between the current source transistor and the first transistor group. A comparison circuit for comparing the reference voltage with the reference voltage of the reference voltage source, and a level comparison result of the comparison circuit is output as read data.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor memory device according to the present invention will be described using a nonvolatile semiconductor memory device. In the nonvolatile semiconductor memory device of the present invention, the same n-bit data (important data) is stored in n (n is a positive integer) memory cell arrays each having a common address, and the n memory cell arrays are simultaneously read. Then, a voltage corresponding to the sum of the n read currents is compared with a reference voltage, and the level comparison result is output as read data of the memory cell array.

Thus, if electrons are not injected into the floating gates of the n memory cells, the cell current at the time of reading flows n times in total. So, that n
A level comparison between the voltage corresponding to the doubled current and the intermediate reference voltage is performed. The level comparison result is derived as a read output. As a result, even if some of the n read cell currents do not flow, the total can be determined with a sufficient margin with respect to the reference voltage.

Conversely, it is assumed that electrons are injected into the floating gates of the n memory cells and no cell current flows. In this state, even if some cell currents flow for some reason, if the reference value is not reached, it is determined that no current flows. Accordingly, the detection accuracy of reading is increased, and the number of rewritable times and the holding time of the semiconductor memory device can be increased.

For example, when eight memory cell arrays are used, 8I (I is a current flowing according to one memory cell)
Is flowing, the reference voltage is generated in the vicinity of 4I, for example.
Use a current of 3.9I or 4.1. Thereby, even if three of the eight memory cells do not operate and the current becomes zero, it can be determined. The magnitude of the reference voltage can be freely changed according to the design concept. For example, it may be 3.8I or 4.2I.

FIG. 1 is an overall view of a semiconductor memory device according to the present invention. In FIG. 1, 200 is a data pin for inputting / outputting 8-bit data, 201 is a special sector data pin for inputting / outputting 1-bit data for a special sector (important data), and 202 is a data pin for the special sector. A special-sector control pin to which a control signal indicating the arrival is applied.
A switch group including a plurality of switches (203A, 203B, 203C...) To which 1-bit data in the bit data and the data from the special sector data pin 201 are applied, and 204 is a switch group from the switch group 203 Eight memory cell arrays 205 for storing 8-bit data are provided by eight memory cell arrays 204.
A sense amplifier group 206 for amplifying the bit data is a comparator circuit for comparing a voltage corresponding to the sum of the read currents of the 8-bit data from the sense amplifier group 205 with the reference voltage of the reference power supply 207.

First, a description will be given of a case where the apparatus shown in FIG. 1 stores and reads out ordinary data, and then a case where data to be held for a long period of time and data which is frequently rewritten are stored. Normal data input / output is
This is performed via the data pin 200. Now, assuming that 8-bit input data is applied to the data pin 200, the input data is applied to the switches (2
03A, 203B, 203C...) Are applied in parallel. The switch group 203 selectively outputs data from the data pin 200 or the special sector data pin 201 according to a control signal from the special sector control pin 202.

In this case, data from the data pin 200 is selected, and 8-bit data is applied to the column decoder 209 via the input buffer 208. On the other hand, address information is applied from the address latch 210 to the column decoder 209 and the row decoder 211, and the address of the memory cell array is specified. In the memory cell arrays M1 to M8, the same address is designated, and data from the column decoder 209 is stored.

At the time of reading, the column decoder 2
09 and the row decoder 211 specify a read address, and the specified memory cell is stored in the column decoder 2.
09 is connected to the sense amplifier group 205, and data read by the sense amplifier group 205 is applied to the data pin 200 via the output buffer 212. next,
When storing data to be held for a long time or data with a large number of rewrites, the switch group 203 switches in reverse according to the control signal from the special sector control pin. A storage area for such data to be stored is called a special sector.

When the switch group 203 switches in the opposite direction,
One-bit data from the special sector data pin 201 is selected and applied to the input buffer 208. The subsequent storage operation is as described above, and eight identical data are stored in eight memory cell arrays. At the time of reading, the same data of 8 bits is generated from the sense amplifier group 205 as in the case described above, and the comparison circuit 2
At 06, it is compared with the reference voltage of the reference power supply 207. The comparison circuit 206 performs a level comparison between the sum of the 8-bit signals and a reference voltage set near the intermediate value. This allows
Even if some of the eight read cell currents do not operate, the total can be determined with a sufficient margin with respect to the reference voltage.

Then, the result of the determination is derived to the outside from the special sector data pin 201 via the special sector output buffer 213. Therefore, according to the device shown in FIG. 1, the detection accuracy of reading is increased, and the number of rewritable times and the holding time of the semiconductor memory device can be increased. FIG. 3 shows a specific circuit configuration of the comparison circuit 206. FIG. 3 illustrates the case of 3 bits instead of 8 bits. In the description of FIG. 1, all the memory cell arrays of the memory are used, but one part may be used.

The output signals of the sense amplifier group 205 are applied to the terminals 301 to 303 in FIG. Now, the signal to be read is at “L” level, and the terminals 301 to 3
Assuming that all “H” level signals have been applied to
The transistors 304, 305, and 306 turn on.

In reading the memory, the terminal 307,
An “H” level signal is applied to 308, 309, and 310, and the circuit is set to read enable (READ ENABLE). Since the transistors 304, 305, and 306 have the same transistor size, the on-resistance is the same,
Equal current Io flows and 3Io flows through transistor 314. Therefore, the current 3 is applied to the gate of the transistor 315.
A low voltage determined by Io and the ON resistance of the transistor 314 is generated.

On the other hand, transistors 311, 312, 31
3 has the same transistor size as the transistors 304, 305, and 306. Therefore, the current Io flows through the transistor 311 and the transistors 312 and 31
3, a current Io / 2 flows. Therefore, a current 1.5Io flows through the transistor 316. And the transistor 31
7, an intermediate voltage determined by the current 1.5Io and the on-resistance of the transistor 316 is generated.

The transistors 315 and 317 constitute a differential amplifier and compare the levels of two input voltages. In the above state, the gate of the transistor 317 is higher,
The transistor 317 turns on and the transistor 315 turns off. The transistors 318 and 319 are off,
Current mirror circuit 3 including transistors 320 and 321
22 operates. That is, the source of the transistor 317
The same current as the current flowing between the drains
15 supplied between the source and the drain of the transistor 3
The drain voltage at 15 increases. Therefore, output terminal 3
An output signal of "L" level is obtained at 23.

In this case, even if one of the cell currents from the three memory cell arrays does not flow and the magnitude of the signal applied to the terminals 301 to 303 decreases, the determination is made by using the sum of the three. Of certainty increases.
Also, due to defective word lines, bit lines, decoders, etc.
If one of the three cell currents does not flow completely,
Current 2Io flows through transistor 314. For this reason,
A voltage determined by the current 2Io and the on-resistance of the transistor 314 is generated at the gate of the transistor 315. Even in this case, the current of 1.5 Io is applied to the gate of the transistor 317.
And a voltage determined by the on-resistance of the transistor 316, the gate voltage of the transistor 317 becomes higher.

Next, assuming that the signal to be read is at the "H" level and signals at the "L" level are applied to all of the terminals 301 to 303, the voltage VDD is applied to the gate of the transistor 315. Then, transistor 3
15 is turned on, and an “H” level output signal is obtained at the output terminal 323. Also in this case, the transistors 304 to 3
Even if any one of 06 is turned on, an output signal of "H" level can be obtained.

[0024]

According to the present invention, the read detection sensitivity is increased, and the number of rewritable times and the holding time of the semiconductor memory device can be increased. Further, according to the present invention, it is only necessary to add a data pin, a control pin, and a switch group for a special sector to a conventional memory device, so that the read detection accuracy is easily increased.

The semiconductor memory device of the present invention is particularly suitable for use in a nonvolatile semiconductor memory device in which data retention time is important.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a semiconductor memory device of the present invention.

FIG. 2 is a cross-sectional view of a split gate memory cell.

FIG. 3 is a specific circuit example of a comparison circuit 206 of the semiconductor memory device of the present invention.

[Explanation of symbols]

 200 data pin 201 special sector data pin 202 special sector control pin 203 switch group 204 memory cell array 206 comparison circuit 323 output terminal

Claims (2)

[Claims] 1. A semiconductor memory device for storing data to be held for a long time or data with a large number of rewrites in a plurality of memory cell arrays having memory cells having the same address, wherein data for inputting and outputting n-bit data is provided. A special sector data pin for inputting / outputting special sector data; a special sector control pin to which a control signal indicating that the special sector data has arrived; and one bit in the n-bit data A switch group including a plurality of switches to which the data of the special sector data pin and the data from the special sector data pin are applied; n memory cell arrays for storing n-bit data from the switch group; and the n memories Sense amplifier for amplifying n-bit data from cell array A first transistor group in which a read signal from the sense amplifier group is applied to a gate and a source / drain is connected to the current source transistor; and a sum of the n-bit data read current. A reference voltage source for generating a voltage in the vicinity of an intermediate value of the voltage value according to the following: a comparison circuit for comparing a voltage at a connection point between the current source transistor and the first transistor group with a reference voltage of the reference voltage source Wherein the level comparison result of the comparison circuit is output as read data. 2. The comparison circuit according to claim 1, wherein the base includes a transistor to which a voltage at a connection point between the current source transistor and the first transistor group is applied, and a transistor to which a reference voltage of the reference voltage source is applied. 2. The semiconductor memory device according to claim 1, comprising: