JPH11185472A - Semiconductor storage device - Google Patents

Abstract

[PROBLEMS] To provide a semiconductor memory device capable of easily controlling clock switching between an external clock and a correction clock, suppressing an increase in circuit scale, and reducing current consumption. SOLUTION: Two banks 64M bit synchronous DR
AM, in the SMD clock control circuit system,
The control logic & timing generator 15 includes the input buffer circuit 1
7. Switching circuit 18 and clock generator 19, SM
The D clock generation circuit 16 includes a pulse generator 20, a delay circuit 21, an SMD array circuit 22, an SMD control circuit 23, and an over-locking range detector 24. In a normal operation, an external clock CLK is used, and a burst operation starts from a read command. SMD clock SC only until the end
LK is used, and when the SMD locking range is exceeded, the clock is automatically switched to the external clock CLK.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device technology, and more particularly to a clock synchronous type synchronous DRAM.
The present invention relates to a technique effective when applied to a semiconductor memory device suitable for designing a correction clock control circuit system such as an SMD (Synchronous Mirror Delay) clock.

[0002]

2. Description of the Related Art For example, as a technique studied by the present inventors, a synchronous DRA as an example of a semiconductor memory device is disclosed.
M is suitable for high-speed operation by control of perfect synchronization by a clock. Usually, a synchronous DRAM has an internal clock generation function, and it is considered that a correction clock control circuit system or the like is used in order to match the phase with an external clock to make the delay of the internal clock apparently zero. .

[0003] With respect to such a correction clock control circuit system of the synchronous DRAM, for example, a digital DLL (Delay Lo) similar to the SMD clock control circuit system is used.
ckedLoop) IEICE TRAN as clock control circuit method
S.ELECTRON, VOL.E79-C, NO.6JUNE 1996 PAPER Special I
ssue on ULSI Memory Technology Digital DelayLock
ed Loop and Desine Technique for High-Speed Synchr
onous Interface ”, P789-P807.

[0004]

In the above-described correction clock control circuit system for a synchronous DRAM, when a correction clock is used, an increase in current consumption due to the operation of the correction clock circuit and control of switching to an external clock are performed. It is conceivable that this may lead to an increase in circuit complexity and scale.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device capable of realizing easy clock switching control, suppression of increase in circuit scale, and reduction of current consumption in a correction clock control circuit system such as an SMD clock. Is what you do.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0007]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the semiconductor memory device according to the present invention has a circuit configuration in which an external clock and a correction clock (SMD clock) are input to the gates of MOS transistors connected in parallel, and the internal clock generator is shared. . In this configuration, the switching control of the external and SMD clocks is performed by using the external clock during the normal operation.
SMD only during the cycle requiring the SMD clock, that is, the period from the read command to the end of the burst operation
The clock generation circuit is operated, and the SMD clock is used. When the external clock cycle exceeds the SMD locking range, a detection circuit system that automatically switches to the external clock is adopted.

Therefore, according to the semiconductor memory device, since the same internal clock generator is used to generate an internal clock according to a previously input clock, there is no clock delay with the same circuit scale. Use of an external, SMD clock is possible. In addition, since the switching can be easily performed, the SMD is performed only for the minimum necessary cycle period.
Control for operating the clock generation circuit and the clock generator becomes possible, and the average current consumption can be reduced.

As a result, it is possible to facilitate clock switching control, suppress an increase in circuit scale, and reduce current consumption. Therefore, the present invention can be applied to a clock-synchronous semiconductor memory device such as a synchronous DRAM having an internal clock generation function, to improve the access of the semiconductor memory device and reduce the average current consumption.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is an overall block diagram showing a semiconductor memory device according to one embodiment of the present invention, FIG. 2 is a block diagram showing a correction clock generation circuit of the semiconductor memory device in this embodiment, and FIG. FIG. 6 is a timing chart showing operation waveforms in a cycle requiring the operation.

First, the configuration of the semiconductor memory device according to the present embodiment will be described with reference to FIG.

The semiconductor memory device of the present embodiment is, for example, a 2-bank 64 Mbit synchronous DRAM,
Memory array banks 1 and 2, each memory array bank 1
Row decoders 3 and 4 and column decoders 5 corresponding to
6, sense amplifier & input / output buses 7, 8, common row address buffer 9, column address buffer 10, column address counter 11, refresh counter 1
2, input buffer 13, output buffer 14, control logic &
It comprises a timing generator 15, an SMD clock generation circuit 16, and the like.

An address signal Aa is externally input to the synchronous DRAM, and a row address signal XA,
A column address signal YA is generated and input to the row address buffer 9 and the column address buffer 10, respectively, and an arbitrary memory cell in the memory array banks 1 and 2 is passed through the row decoders 3 and 4 and the column decoders 5 and 6. Selected. The input / output data I / Oi is input via the input buffer 13 during a write operation, and is output via the sense amplifier & input / output buses 7 and 8 and the output buffer 14 during a read operation.

An external clock CL is used as a control signal.
K, a clock enable signal CKE, a chip select signal CSB, a row address strobe signal RASB, a column address strobe signal CASB, a write enable signal WEB, a data mask signal DQM, and the like are externally input, and the control logic & A command and an internal control signal are generated by the timing generator 15, and the operation of the internal circuit is controlled by the command and the internal control signal.

In particular, the control logic & timing generator 15 and the SMD clock generation circuit 16 in the present embodiment
For example, as shown in FIG. 2, an input buffer circuit 17, a switching circuit 18, a clock generator 19, a pulse generator 20, a delay circuit 21, an SMD array circuit 22, a SM
D control circuit 23 and locking range excess detector 24
The circuit configuration is such that an external clock CLK is input from the outside and an internal clock QCLK for input / output control in consideration of an appropriate delay is output.

The input buffer circuit 17 receives an external clock C
LK and the clock selection signal SMDS from the over-locking range detector 24 are input, these signals are held, an external clock CLK is output during normal operation, and the signal S from the read command to the end of the burst operation is output.
In the operation using the MD clock SCLK, when the locking range is exceeded, the SMD clock SCLK is automatically
And switches to the external clock CLK.

The switching circuit 18 comprises a combination of a PMOS transistor and an NMOS transistor. The switching circuit 18 receives an external clock CLK from the input buffer circuit 17 inputted to the gates of the respective NMOS transistors connected in parallel, and a signal from the SMD array circuit 22. A circuit for switching and outputting these signals based on the SMD clock SCLK by a first-input method.

The clock generator 19 includes a switching circuit 18
External clock CLK or SMD clock SCL
A circuit which receives K as an input and outputs an internal clock QCLK having a predetermined oscillation cycle based on one of the clocks.

The pulse generator 20 includes the input buffer circuit 1
7, an SMD ON signal from the SMD control circuit 23, and a clock selection signal SMDS from the over-locking range detector 24. The SMD basic clock ESCLK is output by waveform shaping.

The delay circuit 21 is a circuit which receives the SMD basic clock ESCLK from the pulse generator 20 as input, delays the phase of this clock, and outputs the delayed clock.

The SMD array circuit 22 has a delay function consisting of a plurality of stages. The SMD basic clock ESCLK from the pulse generator 20 and the delay signal from the delay circuit 21 are input, and the desired number of stages is determined based on these signals. Is a circuit that delays the phase according to the output and outputs the result. The output of the SMD array circuit 22 is supplied to the SMD clock SC via a buffer.
Output as LK.

The SMD control circuit 23 has a read command,
A circuit which receives a state flag as an input, outputs an SMD ON signal during a period from a read command to the end of a burst operation based on this signal, and outputs an SMD enable signal SMDE for detecting an excess of a locking range.

The over-locking range detector 24 has a SM
SMD enable signal SMDE from D control circuit 23,
Signal from SMD array circuit 22, SMD clock SC
In the operation using the SMD clock SCLK from the read command to the end of the burst operation with LK as an input, this circuit detects whether or not the locking range has been exceeded and outputs a clock selection signal SMDS for clock switching.

In the configuration of the control logic & timing generator 15 and the SMD clock generation circuit 16 as described above, the switching control of the external clock CLK and the SMD clock SCLK is performed. In the normal operation, the external clock CLK is used and the read operation is performed. The SMD clock SCLK is used only during the period from the command to the end of the burst operation, and when the SMD locking range is exceeded, the external clock CLK is automatically used.
Is switched to.

Next, the operation of the present embodiment will be briefly described first with an outline of the operation of the synchronous DRAM. The operation of the synchronous DRAM is controlled by a command for a general-purpose DRAM controlled by rising / falling control signals of a row address strobe signal RASB, a column address strobe signal CASB, and a write enable signal WEB.

All operations of the synchronous DRAM are performed in synchronization with the internal clock QCLK, and each operation is controlled by a command. This command is defined by a combination of control signals of a chip select signal CSB, a column address strobe signal CASB, a row address strobe signal RASB, and a write enable signal WEB.

That is, these control signals are High / Lo at the rising edge of the internal clock QCLK.
Depending on the state of w, bank active, read, write,
Commands such as precharge and refresh are defined, and these commands are decoded to make each circuit execute an operation corresponding to the command.

For example, in a standby state of a read operation or a write operation, when a memory array bank designated by the setting of a bank active command is selected to activate a designated word line, and a read command is set, Data can be read from the selected bank, and data can be written to the selected bank when a write command is set.

When a precharge command is set, a precharge operation of a designated memory array bank can be performed, and the precharge is automatically performed after a read operation or a write operation is completed. There are a read command with auto-precharge and a write command with auto-precharge for executing the operation.

Further, the refresh command includes, for example, an auto-refresh command and a self-refresh command. In setting the auto-refresh command, an address is generated internally and a refresh operation is automatically performed. This is performed for battery backup and the like, and after the self-refresh operation is completed, an auto-refresh operation is performed.

As described above, the synchronous DRAM
, A bank operation, a read operation, a write operation, a precharge operation, and a refresh operation. These operations are executed by, for example, starting the actual operation after precharging all memory array banks, setting the mode register, and performing auto-refresh after power-on.

Next, the normal operation of the cycle requiring the SMD clock SCLK and the operation when the locking range is exceeded will be described with reference to the timing chart of FIG. Note that a normal operation that does not require the SMD clock SCLK is performed using the external clock CLK.

First, a read command is generated in synchronization with the external clock CLK, a state flag is raised in synchronization with a rising edge of the read command, and the synchronous DRAM is readable in a read state activation period by the flag. Becomes

At this time, the external clock CLK is input to the pulse generator 20 via the input buffer circuit 17, and the pulse generator 20 outputs the SMD basic clock ESCLK in synchronization with the external clock CLK.

At the same time, a read command and a state flag are input to the SMD control circuit 23. The SMD enable signal SMDE rises in synchronization with the rising edge of the state flag, and the SMD enable signal S
During the activation period of the MDE, a normal operation in a cycle requiring the SMD clock SCLK is enabled.

The delay circuit 21 and the SMD array circuit 22, which have received the SMD basic clock ESCLK from the pulse generator 20, delay and invert the phase of the SMD basic clock ESCLK, and output the SMD clock SCLK via a buffer. I do.

At this time, the SM from the SMD control circuit 23
The locking range excess detector 24 receiving the D enable signal SMDE detects whether the SMD clock SCLK has exceeded the locking range, and outputs a clock selection signal SMDS for clock switching.

For example, this clock selection signal SMDS
Is the SMD from the read command to the end of the burst operation
In a cycle requiring the clock SCLK, when the cycle of the external clock CLK (locking range detection cycle) exceeds the locking range, the level becomes “L” level, and when it does not exceed the locking range, it becomes “H” level.

While the clock selection signal SMDS is at the "L" level, the clock is automatically switched to the external clock CLK via the input buffer circuit 17 receiving the clock selection signal SMDS and further through the switching circuit 18. Internal clock QCLK based on CLK can be output.

When the clock selection signal SMDS is "H"
During the level period, the state is maintained as it is via the input buffer circuit 17 and the switching circuit 18, and the internal clock QCLK based on the SMD clock SCLK can be output.

Therefore, according to the semiconductor memory device of the present embodiment, the control logic & timing generator 15 including the input buffer circuit 17, the switching circuit 18 and the clock generator 19, the pulse generator 20, the delay circuit 21, SMD
By having the SMD clock generation circuit 16 including the array circuit 22, the SMD control circuit 23 and the locking range excess detector 24, the external clock CLK is used during the normal operation, and the SMD clock is used only during the period from the read command to the end of the burst operation. The clock SCLK can be used, and when the SMD locking range is exceeded, the clock can be automatically switched to the external clock CLK.

Therefore, the same clock generator 19 is used for switching between the external clock CLK and the SMD clock SCLK.
, The external clock CLK and the SMD clock SCLK can be used with the same circuit scale and no clock delay, and the switching can be easily performed. Therefore, the SMD clock is generated only for the minimum necessary cycle period. Since the circuit 16 and the like may be operated, the average current consumption can be reduced.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and various modifications may be made without departing from the gist of the invention. It goes without saying that it is possible.

For example, in the above embodiment, 2
Although the description has been made with reference to the example of the 64M-bit synchronous DRAM in the bank, the present invention is not limited to this, and there is a trend toward four banks, eight banks, and even more banks, and a 256M-bit synchronous DRAM with a larger capacity. Eggplant DRA
M is also widely applicable, and the effect of the present invention is further increased by adopting such a multi-bank, large-capacity configuration.

Although the description has been given of the case where the present invention is applied to a synchronous DRAM, the present invention can be applied to all clock synchronous semiconductor memory devices such as DDR (Double Data Rate). Further, in addition to the SMD clock control circuit system, a DLL clock control circuit system, a PLL (Phase Lock
ed Loop) It can be widely applied to a correction clock control circuit method that requires a correction clock whose phase is adjusted by delay correction with an external clock, such as a clock control circuit method.

[0048]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1) Since the same clock generator can be shared by having a clock generator for generating an internal clock for the input of the external clock and the correction clock, the same circuit scale can be used. There is no clock delay, and it is possible to use an external clock and a correction clock.

(2) The switching circuit can be easily switched by adopting a parallel connection configuration composed of MOS transistors, so that clock switching control can be facilitated.

(3) By providing the correction clock generation circuit for generating the correction clock only during the period from the read command to the end of the burst operation, the correction clock generation circuit can be operated only in the cycle requiring the correction clock. Therefore, current consumption can be reduced.

(4) Since the detection circuit automatically switches to the external clock when the period of the external clock exceeds the locking range, the correction clock generation circuit and the clock generator are operated only for the minimum necessary cycle period. Therefore, the average current consumption can be reduced.

(5) According to the above (1) to (4), in the correction clock control circuit system such as the SMD clock, it is easy to control the switching of the clock between the external clock and the correction clock, to suppress the increase in the circuit scale, and to reduce the current consumption. Can be reduced.

(6) According to the above (5), the synchronous DRA
In a clock-synchronous semiconductor memory device such as M, it is possible to facilitate clock switching control, suppress an increase in circuit size, and reduce current consumption, thereby improving access and reducing average current consumption.

[Brief description of the drawings]

FIG. 1 is an overall block diagram showing a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a correction clock generation circuit of the semiconductor memory device according to one embodiment of the present invention.

FIG. 3 is a timing chart showing operation waveforms of a cycle requiring a correction clock of the semiconductor memory device according to the embodiment of the present invention;

[Explanation of symbols]

 1, 2 memory array bank 3, 4 row decoder 5, 6 column decoder 7, 8 sense amplifier & input / output bus 9 row address buffer 10 column address buffer 11 column address counter 12 refresh counter 13 input buffer 14 output buffer 15 control logic & Timing generator 16 SMD clock generation circuit 17 Input buffer circuit 18 Switching circuit 19 Clock generator 20 Pulse generator 21 Delay circuit 22 SMD array circuit 23 SMD control circuit 24 Locking range excess detector

Claims (5)

[Claims] 1. A clock-synchronous semiconductor memory device that operates by switching between an external clock and a corrected clock whose phase is adjusted by delay correction with the external clock.
With the external clock and the correction clock as inputs,
A semiconductor memory device comprising: a switching circuit for selecting and outputting one of them; and a clock generator for receiving an output of the switching circuit and generating an internal clock. 2. The semiconductor memory device according to claim 1, wherein said switching circuit comprises a first MOS transistor for gate-inputting said external clock and a second MOS transistor for gate-inputting said correction clock. A semiconductor memory device having a parallel connection configuration. 3. The semiconductor memory device according to claim 1, further comprising a correction clock generation circuit that generates the correction clock only during a period from a read command to the end of a burst operation. 4. The semiconductor memory device according to claim 3, wherein, during a period from the read command to the end of the burst operation, when the period of the external clock detects that the locking range due to the correction clock has been exceeded, the external clock is automatically set. A semiconductor memory device having a detection circuit for switching to an external clock. 5. The semiconductor memory device according to claim 1, wherein said semiconductor memory device is a synchronous DRAM.