JPH11176851A - Semiconductor chip package - Google Patents
Semiconductor chip packageInfo
- Publication number
- JPH11176851A JPH11176851A JP9352114A JP35211497A JPH11176851A JP H11176851 A JPH11176851 A JP H11176851A JP 9352114 A JP9352114 A JP 9352114A JP 35211497 A JP35211497 A JP 35211497A JP H11176851 A JPH11176851 A JP H11176851A
- Authority
- JP
- Japan
- Prior art keywords
- adhesive
- semiconductor chip
- sealing cover
- sealing
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本願の発明は、半導体チップ
が基台に固定され且つ封止カバーで気密封止されている
半導体チップパッケージに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip package in which a semiconductor chip is fixed to a base and hermetically sealed with a sealing cover.
【０００２】[0002]
【従来の技術】半導体レーザチップパッケージの様に光
を扱う半導体チップパッケージ等では、半導体チップを
樹脂封止することができないので、基台に固定されてい
る半導体チップを封止カバーで気密封止している。この
様に半導体チップが基台に固定され且つ封止カバーで気
密封止されている半導体チップパッケージでは、従来
は、基台と封止カバーとの界面に熱硬化樹脂や紫外線硬
化樹脂等の接着剤が塗布されて、封止カバーが基台に接
着されているだけであった。2. Description of the Related Art In a semiconductor chip package or the like that handles light like a semiconductor laser chip package, the semiconductor chip cannot be sealed with a resin. Therefore, the semiconductor chip fixed to the base is hermetically sealed with a sealing cover. doing. Conventionally, in a semiconductor chip package in which a semiconductor chip is fixed to a base and hermetically sealed by a sealing cover, conventionally, an interface between the base and the sealing cover is bonded with a thermosetting resin or an ultraviolet curing resin. The agent was only applied and the sealing cover was only adhered to the base.
【０００３】[0003]
【発明が解決しようとする課題】しかし、基台と封止カ
バーとの界面には接着剤が平面的にしか塗布されないの
で、接着範囲が狭くて、基台と封止カバーとの界面に通
気道が形成され易い。このため、従来の半導体チップパ
ッケージでは、封止性能が低く半導体チップの耐湿性が
低くて、半導体チップの信頼性が低かった。However, since the adhesive is applied only flatly to the interface between the base and the sealing cover, the bonding range is narrow, and the interface between the base and the sealing cover is ventilated. Roads are easily formed. For this reason, in the conventional semiconductor chip package, the sealing performance was low, the moisture resistance of the semiconductor chip was low, and the reliability of the semiconductor chip was low.
【０００４】即ち、接着剤として熱硬化樹脂を用いて硬
化時に加熱を行うと、接着された封止カバー内の空間の
圧力が封止カバー外の空間の圧力よりも高くなって、基
台と封止カバーとの界面に通気道が形成され易い。[0004] That is, when heating is performed during curing using a thermosetting resin as an adhesive, the pressure in the space inside the sealed cover becomes higher than the pressure in the space outside the sealed cover, so that the base and the base are hardened. An air passage is easily formed at the interface with the sealing cover.
【０００５】一方、接着剤として紫外線硬化樹脂を用い
ると硬化時に加熱が不要であるが、紫外線硬化樹脂は熱
硬化樹脂に比べて接着力が劣るので、やはり基台と封止
カバーとの界面に通気道が形成され易い。[0005] On the other hand, when an ultraviolet curable resin is used as an adhesive, heating is not required at the time of curing. However, since the ultraviolet curable resin has an inferior adhesive force as compared with the thermosetting resin, the ultraviolet curable resin also has an interface between the base and the sealing cover. An air passage is easily formed.
【０００６】なお、接着剤の硬化時に封止カバーに荷重
を加えると通気道の形成を抑制することができるが、封
止カバーが樹脂製等であると、この荷重によっても封止
カバーが変形したり亀裂が発生したりして、品質の低下
や半導体チップの特性不良を生じる。When a load is applied to the sealing cover during curing of the adhesive, the formation of the air passage can be suppressed. However, if the sealing cover is made of resin or the like, the sealing cover is deformed by the load. Or cracks may occur, resulting in a decrease in quality or defective characteristics of the semiconductor chip.
【０００７】従って、本願の発明は、半導体チップの耐
湿性が高く、また、半導体チップに特性不良を生じさせ
なくて、半導体チップの信頼性が高い半導体チップパッ
ケージを提供することを目的としている。SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor chip package in which the semiconductor chip has high moisture resistance, does not cause characteristic failure in the semiconductor chip, and has high reliability.
【０００８】[0008]
【課題を解決するための手段】請求項１に係る半導体チ
ップパッケージでは、枠体が基台の表面に沿って封止カ
バーを包囲しているので、枠体の高さを高くして第２の
接着剤の充填時に枠体を第２の接着剤の流れ止めにする
ことによって、封止カバーと枠体との間に第２の接着剤
を立体的に厚く充填することができる。In the semiconductor chip package according to the first aspect, the frame surrounds the sealing cover along the surface of the base. When the frame is filled with the adhesive, the second adhesive can be three-dimensionally and thickly filled between the sealing cover and the frame by stopping the flow of the second adhesive.
【０００９】このため、硬化時に加熱を行わなくて接着
力の劣る接着剤を第１及び第２の接着剤として用いて
も、また、第１の接着剤の硬化時に封止カバーに荷重を
加えなくても、少なくとも第２の接着剤と基台との界面
では通気道の形成を抑制することができ、封止性能が高
くて半導体チップの耐湿性が高い。For this reason, even if an adhesive having inferior adhesive strength is used as the first and second adhesives without heating during curing, a load is applied to the sealing cover when the first adhesive is cured. Even if it is not provided, formation of a ventilation path can be suppressed at least at the interface between the second adhesive and the base, and the sealing performance is high and the moisture resistance of the semiconductor chip is high.
【００１０】しかも、接着剤の硬化時に荷重を加える必
要がないので、封止カバーの変形や亀裂の発生を防止す
ることができる。このため、封止性能が高くて半導体チ
ップの耐湿性が高く、また、半導体チップに特性不良を
生じさせない。In addition, since it is not necessary to apply a load when the adhesive is cured, it is possible to prevent the sealing cover from being deformed or cracked. For this reason, the sealing performance is high, the moisture resistance of the semiconductor chip is high, and the semiconductor chip does not cause characteristic failure.
【００１１】請求項２に係る半導体チップパッケージで
は、枠体が封止カバーと一体化されているので、封止カ
バーと枠体とを基台に同時に接着することができて、封
止工程の増大が抑制されている。In the semiconductor chip package according to the second aspect of the present invention, since the frame is integrated with the sealing cover, the sealing cover and the frame can be simultaneously bonded to the base. The increase is suppressed.
【００１２】請求項３に係る半導体チップパッケージで
は、枠体が基台と一体化されているので、基台に対して
枠体を接着する作業が不要であり、封止工程の増大が抑
制されている。In the semiconductor chip package according to the third aspect, since the frame is integrated with the base, an operation of bonding the frame to the base is unnecessary, and an increase in the sealing process is suppressed. ing.
【００１３】請求項４に係る半導体チップパッケージで
は、第２の接着剤が光吸収剤を含んでいるので、パッケ
ージ外からの外乱光やパッケージ内における内乱光を吸
収することができて、散乱光が低減されている。In the semiconductor chip package according to the fourth aspect, since the second adhesive contains a light absorbing agent, it is possible to absorb disturbance light from outside the package and internal light inside the package, and to scatter light. Has been reduced.
【００１４】[0014]
【発明の実施の形態】以下、半導体レーザチップパッケ
ージに適用した本願の発明の一実施形態を、図１を参照
しながら説明する。本実施形態の半導体レーザチップパ
ッケージ１１を製造するためには、基台１２上に半導体
基板１３、１４を介して半導体レーザチップ１５を固定
し、半導体基板１３、１４及び半導体レーザチップ１５
と基台１２との間にワイヤ１６をボンディングする。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention applied to a semiconductor laser chip package will be described below with reference to FIG. In order to manufacture the semiconductor laser chip package 11 of the present embodiment, a semiconductor laser chip 15 is fixed on a base 12 via semiconductor substrates 13 and 14, and the semiconductor substrates 13 and 14 and the semiconductor laser chip 15 are fixed.
The wire 16 is bonded between the base and the base 12.
【００１５】そして、半導体レーザチップ１５等を覆う
封止カバー１７と、基台１２の表面に沿って封止カバー
１７を包囲する枠体１８とを、紫外線硬化樹脂である仮
付け用接着剤２１で基台１２に仮付けする。仮付け用接
着剤２１の硬化時には、仮付け用接着剤２１に紫外線を
２〜３秒程度照射し、封止カバー１７や枠体１８には荷
重を加えない。Then, the sealing cover 17 covering the semiconductor laser chip 15 and the like and the frame 18 surrounding the sealing cover 17 along the surface of the base 12 are bonded to a temporary adhesive 21 made of an ultraviolet curing resin. Is temporarily attached to the base 12. At the time of curing the temporary bonding adhesive 21, ultraviolet rays are irradiated to the temporary bonding adhesive 21 for about 2 to 3 seconds, and no load is applied to the sealing cover 17 and the frame 18.
【００１６】このため、仮付け用接着剤２１の接着力は
十分には強くなく、また、基台１２と封止カバー１７と
の界面には通気道が形成され易い。なお、封止カバー１
７の上面には透光部（図示せず）が設けられており、半
導体レーザチップ１５から射出されたレーザ光はこの透
光部を介して半導体レーザチップパッケージ１１外へ放
射される。For this reason, the adhesive force of the temporary bonding adhesive 21 is not sufficiently strong, and a ventilation path is easily formed at the interface between the base 12 and the sealing cover 17. In addition, the sealing cover 1
A light-transmitting portion (not shown) is provided on the upper surface of 7, and laser light emitted from the semiconductor laser chip 15 is radiated out of the semiconductor laser chip package 11 via the light-transmitting portion.
【００１７】その後、黒色等の染料や顔料等である光吸
収剤を含んでいる熱硬化樹脂等の封止用接着剤２２を封
止カバー１７と枠体１８との間に流し込み、封止用接着
剤２２を１時間程度熱硬化して、この封止用接着剤２２
を硬化させる。Thereafter, a sealing adhesive 22 such as a thermosetting resin containing a light absorbing agent such as a dye or a pigment such as black is poured between the sealing cover 17 and the frame 18 to form a sealing material. The adhesive 22 is heat-cured for about one hour, and this sealing adhesive 22 is cured.
To cure.
【００１８】但し、封止カバー１７が加熱によって変形
したり応力を発生したりし易い材料から成っていれば、
封止用接着剤２２として常温硬化樹脂や紫外線硬化樹脂
等を用いてもよい。封止用接着剤２２は封止カバー１７
と枠体１８との間に立体的に厚く充填することができる
ので、封止用接着剤２２として常温硬化樹脂や紫外線硬
化樹脂等を用いても、接着力が十分に強く、また、基台
１２と封止カバー１７との界面に通気道が形成されにく
い。However, if the sealing cover 17 is made of a material which is easily deformed or generates stress by heating,
A room temperature curable resin, an ultraviolet curable resin, or the like may be used as the sealing adhesive 22. The sealing adhesive 22 is used for the sealing cover 17.
And the frame 18 can be filled three-dimensionally and thickly, so that even if a room-temperature-curable resin or an ultraviolet-curable resin is used as the sealing adhesive 22, the adhesive strength is sufficiently strong. An air passage is hardly formed at the interface between the sealing cover 12 and the sealing cover 17.
【００１９】また、以上の実施形態では基台１２と封止
カバー１７と枠体１８とが互いに別体であるが、枠体１
８が封止カバー１７と一体化されていてもよく、枠体１
８が基台１２と一体化されていてもよい。In the above embodiment, the base 12, the sealing cover 17, and the frame 18 are separate from each other.
8 may be integrated with the sealing cover 17, and the frame 1
8 may be integrated with the base 12.
【００２０】更に、以上の実施形態は半導体レーザチッ
プパッケージ１１に本願の発明を適用したものである
が、半導体レーザチップパッケージ１１以外の半導体チ
ップパッケージにも本願の発明を適用することができ
る。Further, in the above embodiment, the present invention is applied to the semiconductor laser chip package 11, but the present invention can be applied to semiconductor chip packages other than the semiconductor laser chip package 11.
【００２１】[0021]
【発明の効果】請求項１に係る半導体チップパッケージ
では、封止性能が高くて半導体チップの耐湿性が高く、
また、半導体チップに特性不良を生じさせないので、半
導体チップの信頼性が高い。According to the semiconductor chip package of the present invention, the sealing performance is high and the moisture resistance of the semiconductor chip is high.
In addition, since the semiconductor chip does not cause a characteristic defect, the semiconductor chip has high reliability.
【００２２】請求項２、３に係る半導体チップパッケー
ジでは、封止工程の増大が抑制されているので、製造コ
ストの増大が抑制されている。In the semiconductor chip package according to the second and third aspects, the increase in the sealing process is suppressed, so that the increase in the manufacturing cost is suppressed.
【００２３】請求項４に係る半導体チップパッケージで
は、散乱光が低減されているので、光を扱う半導体チッ
プの信頼性が高い。In the semiconductor chip package according to the fourth aspect, since the scattered light is reduced, the reliability of the semiconductor chip handling the light is high.
【図１】本願の発明の一実施形態を示しており、（ａ）
は（ｂ）のＡ−Ａ線に沿う位置における側断面図、
（ｂ）は封止カバーを取り除いた状態の平面図である。FIG. 1 shows an embodiment of the invention of the present application, and (a)
Is a side sectional view at a position along the line AA in FIG.
(B) is a plan view in a state where a sealing cover is removed.
１１…半導体レーザチップパッケージ（半導体チップパ
ッケージ）、１２…基台、１５…半導体レーザチップ
（半導体チップ）、１７…封止カバー、１８…枠体、２
１…仮付け用接着剤（第１の接着剤）、２２…封止用接
着剤（第２の接着剤）11 semiconductor laser chip package (semiconductor chip package), 12 base, 15 semiconductor laser chip (semiconductor chip), 17 sealing cover, 18 frame, 2
1: adhesive for temporary attachment (first adhesive), 22: adhesive for sealing (second adhesive)
Claims (4)
に接着されている封止カバーと、 前記基台の表面に沿って前記封止カバーを包囲している
枠体と、 前記封止カバーと前記枠体との間に充填されている第２
の接着剤とを具備することを特徴とする半導体チップパ
ッケージ。A base on which the semiconductor chip is fixed; a sealing cover covering the semiconductor chip and bonded to the base with a first adhesive; A frame surrounding the sealing cover; and a second filler filled between the sealing cover and the frame.
A semiconductor chip package comprising: an adhesive;
ていることを特徴とする請求項１記載の半導体チップパ
ッケージ。2. The semiconductor chip package according to claim 1, wherein said frame is integrated with said sealing cover.
ことを特徴とする請求項１記載の半導体チップパッケー
ジ。3. The semiconductor chip package according to claim 1, wherein said frame is integrated with said base.
ることを特徴とする請求項１記載の半導体チップパッケ
ージ。4. The semiconductor chip package according to claim 1, wherein said second adhesive contains a light absorbing agent.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9352114A JPH11176851A (en) | 1997-12-05 | 1997-12-05 | Semiconductor chip package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9352114A JPH11176851A (en) | 1997-12-05 | 1997-12-05 | Semiconductor chip package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11176851A true JPH11176851A (en) | 1999-07-02 |
Family
ID=18421878
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9352114A Pending JPH11176851A (en) | 1997-12-05 | 1997-12-05 | Semiconductor chip package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11176851A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7195687B2 (en) | 2001-04-11 | 2007-03-27 | Sony Corporation | Device transferring method, and device arraying method and image display unit fabricating method using the same |
| US11476637B2 (en) | 2019-12-16 | 2022-10-18 | Nichia Corporation | Light-emitting device |
-
1997
- 1997-12-05 JP JP9352114A patent/JPH11176851A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7195687B2 (en) | 2001-04-11 | 2007-03-27 | Sony Corporation | Device transferring method, and device arraying method and image display unit fabricating method using the same |
| US11476637B2 (en) | 2019-12-16 | 2022-10-18 | Nichia Corporation | Light-emitting device |
| US11811190B2 (en) | 2019-12-16 | 2023-11-07 | Nichia Corporation | Light-emitting device |
| US12166330B2 (en) | 2019-12-16 | 2024-12-10 | Nichia Corporation | Light-emitting device |
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