JPH11176806A - Plasma purge method for controlling plasma treated particles - Google Patents

Abstract

[PROBLEMS] To limit contaminant particles deposited on an integrated circuit layer in a processing chamber using plasma. A process utilizing plasma and utilizing a reactant gas mixture, a first RF power and a first reaction chamber pressure suitable for an integrated circuit layer. Thereafter, a first plasma purge step is performed during a first purge time immediately after the plasma treatment, the step comprising a first purge gas mixture, a second purge gas mixture,
High frequency power and second reaction chamber pressure are utilized. The second high frequency power is lower than the first high frequency power, and the second reaction chamber pressure is higher than the first reaction chamber pressure. If necessary, the first plasma
A second plasma purge step is performed at a second purge time immediately after the purge step. The second plasma purge step utilizes a second purge gas mixture, a third RF power, and a third reaction chamber pressure. The third high frequency power is substantially equal to the second high frequency power, and the third reaction chamber pressure is lower than the second reaction chamber pressure.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates generally to plasma-based methods for processing integrated circuit layers.
More particularly, the present invention relates to a plasma-based method for treating an integrated circuit layer, wherein the plasma-based method limits deposition of contaminant particles on the integrated circuit layer.

[0002]

BACKGROUND OF THE INVENTION In the art of integrated circuit fabrication, the use of high frequency plasma excitation to generate reactive and non-reactive plasmas that assist in the processing of integrated circuit layers is known. Plasma that supports the processing of integrated circuit layers is used in many integrated circuit layer fabrication processes. The plasma is utilized in integrated circuit layer fabrication processes including, but not limited to, integrated circuit layer formation processes, integrated circuit layer removal processes, and integrated circuit layer repair processes. Types of integrated circuit layers that are supported through the use of high frequency plasma include, but are not limited to, integrated circuit conductor layers, integrated circuit insulator layers, integrated circuit semiconductor layers, and integrated circuit photoactive layers.

[0003] Although the use of high frequency excitation to generate plasmas having applications within many aspects of integrated circuit layer fabrication has become very common in the art, such plasmas are not without problems. Absent. In particular, one of the most troublesome problems arising from plasma-based processing of integrated circuit layers is the formation of contaminant particles in the plasma-based processing reaction chamber and the processing reactions using such plasma. The deposition of these contaminant particles on the surface of the integrated circuit layer that is housed in the room and is to be treated by the plasma. Contaminant particles originate from a number of sources including, but not limited to, the material from which the plasma is formed and the material from which the processing reaction chamber containing the plasma is formed. When deposited on an integrated circuit layer intended for high frequency plasma processing, particles from these materials often cause defects to be created that hinder the production of fully functional and reliable integrated circuits.

[0004] Several aspects of the dynamics of contaminant particle formation and deposition in integrated circuit layer fabrication processes and processing reaction chambers using radio frequency plasma are known in the art. For example, it is known in the art that electrostatic forces induced by high frequency plasma play a significant role in depositing contaminant particles on an integrated circuit layer exposed to high frequency plasma in a processing chamber using plasma. Have been. It is also known that non-electrostatic forces such as temperature gradient forces, hydrodynamic drag and gravity play a greater role in depositing contaminant particles on an integrated circuit layer in a process reaction chamber without high frequency plasma. Accordingly, the present invention relates to controlling contaminant particles in an integrated circuit layer processing reaction chamber using a radio frequency plasma, preferably through a method derived from an understanding of the dynamics of particle formation and deposition in such chambers.

[0005] It is known in the art that methods of processing integrated circuit layers using plasma are influenced through an understanding of the technical principles underlying such processing. For example, Jain et al., In US Pat. No. 5,403,780, describe a method for improving the planarized etch-back profile, stability and reliability of a silicon oxide insulator layer formed through an etching process using a plasma. Has been disclosed. The disclosed method utilizes a composite silicon oxide insulator layer that is partially silicon-containing and tuned to provide the desired planarization, stability, and reliability of the composite silicon oxide insulator layer.

[0006] Further, a two-step plasma purge method that limits deposition of contaminant particles on integrated circuit layers in processes using various types of plasma is disclosed in a related application commonly assigned by the institute. Are disclosed. U.S. Patent Application No. 0, filed September 15, 1995, the entire teachings of which are incorporated herein by reference.
8 / 529,013, C.I. C. See Liao, "Method of Plasma Purge for Plasma Processed Particle Control".

[0007]

What is desired in the art is the use of an additional high frequency plasma to limit the deposition of contaminant particles on integrated circuit layers in a plasma-based processing reaction chamber. An additional method that utilizes an understanding of particle generation and deposition phenomena that provides similar integrated circuit layer processing. Highly desirable are methodologies that are generally applicable to integrated circuit layer processing using a wide range of plasmas and plasma-based processing reaction chambers while performing through a minimum number of processing steps.

It is a first object of the present invention to provide a method for limiting the deposition of contaminant particles on an integrated circuit layer in a processing chamber using a plasma, the method provided being: In general, it is applicable to processing using a wide range of plasma and processing chamber using plasma.

A second object of the invention is to provide a method according to the first object of the invention, which is guaranteed with a minimum number of processing steps.

[0010] A third object of the present invention is also for manufacturing.
It is to provide a method according to the first object of the invention and the second object of the invention.

[0011]

According to the object of the present invention,
The present invention provides a method for limiting the deposition of contaminant particles on an integrated circuit layer in a processing chamber using a plasma. In order to carry out the method of the present invention, a plasma treatment is first performed on an integrated circuit layer in a plasma treatment chamber. Plasma-based processing utilizes plasma-based processing and a reactant gas mixture, first RF power, and first reaction chamber pressure suitable for the integrated circuit layer. Thereafter, a first plasma purge step for a first purge time immediately after the processing using the plasma is performed. The first plasma purge step utilizes a first purge gas mixture, a second radio frequency power and a second reaction chamber pressure. The second high frequency power is lower than the first high frequency power, and the second reaction chamber pressure is higher than the first reaction chamber pressure. Optionally, a second plasma purge step is performed for a second purge time immediately after the first plasma purge step. The second plasma purge step utilizes a second purge gas mixture, a third RF power, and a third reaction chamber pressure. The third high frequency power is substantially equal to the second high frequency power, and the third reaction chamber pressure is lower than the second reaction chamber pressure.

The method of the present invention is generally applicable in limiting the deposition of contaminant particles on integrated circuit layers in a plasma-based process chamber where a variety of plasma-based integrated circuit layer processes are performed. The method of the present invention is directed to a single plasma purge processing step immediately following plasma-based processing performed on an integrated circuit layer in a minimal plasma-based processing reaction chamber. The plasma purging step includes a second high-frequency power lower than the first high-frequency power provided by the integrated circuit processing using the plasma and a second reaction higher than the first reaction chamber pressure provided by the integrated circuit processing using the plasma. It is performed at room pressure. Performing the first plasma purge process step with a second RF power less than the first RF power and a second reaction chamber pressure greater than the first reaction chamber pressure, thereby providing an integrated circuit layer in the otherwise plasma-assisted processing reaction chamber. Particles that should have deposited on it are likely to be diluted and polarized away from the integrated circuit layer. A second plasma purging process performed as required by the plasma purging method of the present invention using a third high frequency power substantially equal to the second high frequency power and a third reaction chamber pressure lower than the second reaction chamber pressure. Throughout the steps, the particles are polarized further away from the integrated circuit layer and are ejected from the plasma-based processing reaction chamber.

The method of the present invention is easily manufacturable and involves a minimum number of processing steps. The method of the present invention can be performed as a one-step plasma purge process following a process using plasma in a process chamber using plasma. To obtain the superior performance of the present invention, the method of the present invention optionally includes a second plasma purge step immediately following the first plasma purge step. May be formed. Both the first plasma purging step and the optional second plasma purging step include high frequency power, reaction chamber pressure and reaction chamber well known in the art of integrated circuit layer processing using plasma in an integrated circuit. This is done through modification of the gas mixture parameters. Thus, the method of the present invention is easily manufacturable and is performed with a minimum number of additional processing steps.

[0014]

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for limiting the deposition of contaminant particles on an integrated circuit layer in a processing chamber using a plasma. To achieve that goal,
The method of the present invention incorporates, at a minimum, one plasma purge processing step of a first purge time immediately following integrated circuit layer processing using a plasma. Both the plasma purge process step and the integrated circuit layer processing using plasma are performed in a plasma-based processing reaction chamber. Using (1) a first purge gas mixture, (2) a second RF power less than the first RF power utilized in integrated circuit layer processing using plasma, and (3) plasma during the plasma purge process step. Utilizing a second chamber pressure greater than the first chamber pressure utilized in the integrated circuit layer processing, thereby providing a plasma-based process on the integrated circuit layer subjected to the plasma purging step of the present invention. Fewer contaminant particles are deposited on the integrated circuit layer using a comparable plasma that does not benefit from being subjected to the plasma purging step of the plasma purging method of the present invention.

The plasma purging method of the present invention optionally includes a second plasma purging step for a second purging time immediately after the first plasma purging step. The second plasma purge processing step includes (1)
A second purge gas mixture, (2) a third, similar to the second RF power utilized in the first plasma purge process step
And (3) a third reaction chamber pressure lower than the second reaction chamber pressure used in the first plasma purge processing step. Through the optional two-step plasma purge process of the plasma purge method of the present invention, the optional two-step plasma purge process is performed.
Particles deposited on the integrated circuit layer using the plasma subjected to the purging process may be either (1) subjected to only the one-step plasma purging process of the plasma purging method of the present invention, or A plasma purge method that does not benefit from being exposed to either the one-step plasma purge process or the optional two-step plasma purge process of the inventive plasma purge method. Fewer processing integrated circuit layers used.

[0016] The one-step plasma purging step of the present invention is an integrated step using a plasma in a processing chamber using a plasma, with or without a second plasma purging step performed as needed. Used immediately after integrated circuit layer processing using plasma of any integrated circuit layer that is susceptible to deposition of contaminant particles during circuit layer processing. The plasma purge method of the present invention is a dynamic purge method.
Random access memory (DRAM) integrated circuits, static random access memory (SRAM) integrated circuits, application specific integrated circuits (ASICs), integrated circuits with field effect transistors (FETs) in the structure, bipolar in the structure Bipolar complementary metal oxide semiconductor (BiCM) in integrated circuits and structures having transistors
OS) is utilized following integrated circuit layer processing using plasma of integrated circuit layers formed on integrated circuits, including but not limited to integrated circuits having transistors. The plasma purge method of the present invention has wide applicability during integrated circuit processing.

Referring now to FIGS. 1-3, there is shown a series of schematic cross-sectional views illustrating an electrode and a plasma in a process chamber using plasma according to a first preferred embodiment of the plasma purge method of the present invention. . The first preferred embodiment of the plasma purging method of the present invention is a general embodiment in which the plasma purging method of the present invention follows any plasma-based integrated circuit layer processing in a plasma-based processing reaction chamber. Two additional preferred embodiments of the plasma purge method of the present invention are described following the first preferred embodiment of the plasma purge method of the present invention. In two additional preferred embodiments of the plasma purge method of the present invention, the plasma purge method of the present invention is incorporated after the silicon oxide integrated circuit layer etching process using a plasma. The preferred embodiment and the plasma purge method of the present invention in which the plasma purge method of the present invention is incorporated after a silicon oxide integrated circuit layer deposition process using a plasma.
And a third preferred embodiment of the purge method.

Referring now to FIG. 1, there is shown a schematic cross-sectional view of an electrode and a plasma in a processing chamber using plasma at the time the integrated circuit layer is being processed by the plasma (processing chamber using plasma). Is not shown). FIG. 1 shows an anode 10 on which a semiconductor substrate 12 is arranged. On the side facing the semiconductor substrate 12 is a cathode 14. Plasma 16 is formed between cathode 14 and semiconductor substrate 12. The plasma 16 is applied to the semiconductor substrate 1
2 integrated circuit layer 13 formed on the upper exposed surface
Used when processing. FIG. 1 also shows the presence of particles 18 inside and near the plasma 16 near the surface of the integrated circuit layer 13 formed on the semiconductor substrate 12. As shown in FIG. 1, the particles 18 are concentrated on a plane near the surface of the integrated circuit layer 13. The presence of particles 18 at this location indicates that the plasma is formed in a plasma-based processing reaction chamber where the plasma is formed at a high frequency plasma power of about 200 to about 950 watts and a chamber pressure of about 200 to about 3000 mTorr. It is common in integrated circuit layer processing using plasma.

The plasma 16 shown in the schematic sectional view of FIG.
Is utilized in a wide range of plasma-based processes that produce integrated circuit layers. The plasma 16 shown in the schematic cross-sectional view of FIG. 1 includes, but is not limited to, an integrated circuit layer forming process using plasma, an integrated circuit layer removing process using plasma, and an integrated circuit layer repairing process using plasma. It is used in the integrated circuit layer fabrication process using Further, the integrated circuit layer 13 formed on the semiconductor substrate 12 includes a wide range of integrated circuit layers conventionally processed through an integrated circuit layer fabrication process using plasma.
The integrated circuit layer 13 formed on the semiconductor substrate 12 includes:
It includes, but is not limited to, a group of integrated circuit layers consisting of an integrated circuit conductor layer, an integrated circuit insulator layer, an integrated circuit semiconductor layer, and an integrated circuit photoactive layer.

In order to process the integrated circuit layer 13, the plasma 16 of the first preferred embodiment of the method of the present invention comprises a reactant gas mixture suitable for plasma-based processing and the integrated circuit layer; And the first reaction chamber pressure is utilized. Typically and preferably, the first RF power is in the range of about 200 to about 950 watts. Usually and preferably, the first reaction chamber pressure will range from about 200 to about 3000 mTorr.

Referring now to FIG. 2, there is shown an electrode and plasma in a processing chamber using plasma from a one-step plasma purge process of the plasma purge method of the present invention. FIG. 2 shows features similar to those shown in FIG. 1 except that the size of the plasma has increased to reach the plasma 16 'of FIG. Further, particles 18
The plane that has achieved the high concentration has moved further away from the surface of the integrated circuit layer 13 formed on the integrated circuit substrate 12. These changes in the size of the plasma 16 and the position of the particles 18 are due to the first plasma purge processing step of the first preferred embodiment of the plasma purge method of the present invention.

The first plasma purging step is performed immediately after the plasma-based processing of the first preferred embodiment of the plasma purging method of the present invention. First plasma
The purging step is preferably performed for a first time of about 5 to about 30 seconds.
Performed during the purge time. The first plasma purge process step utilizes a first purge gas mixture, a second RF power, and a second reaction chamber pressure. The second high frequency power is lower than the first high frequency power, and the second reaction chamber pressure is higher than the first reaction chamber pressure.

The second RF power is preferably integrated to provide an optimal value for limiting the deposition of contaminant particles on the integrated circuit layer 13 through the first preferred embodiment of the plasma purge method of the present invention. The first high-frequency power used in the processing using the plasma for processing the circuit layer 13 is about 20 to
It was found experimentally to be about 50 percent. Similarly, the second reaction chamber pressure is preferably about 150 to about 400 percent of the first reaction chamber pressure utilized in processing with the plasma in which the integrated circuit layer 13 is processed.

For the first preferred embodiment of the plasma purge method of the present invention, a number of types of purges including, but not limited to, reactive purge gas, non-reactive purge gas, oxidizing purge gas and non-oxidizing purge gas. Although gases are known in integrated circuit fabrication, the first purge gas mixture preferably includes an oxidizing purge gas component. More preferably, the oxidation purge gas component is an oxygen oxidation purge gas component. Most preferably, the oxygen oxidation purge gas component is between about 80 and about 500 standard cubic centimeters / minute (scc
m). Optionally, the first purge gas mixture also includes a non-oxidizing purge gas component in addition to the oxidizing purge gas component. As a more preferred option, the non-oxidizing purge gas component is an argon non-oxidizing purge gas component.
Most preferably, the argon non-oxidizing purge gas component is provided at a flow rate of about 20 to about 200 standard cubic centimeters / minute.

In a first preferred embodiment of the plasma purge method of the present invention, the first purge gas mixture is probably
After performing plasma-based processing on the integrated circuit layer 13, it assists in scientifically and physically etching any particles 18 remaining in the plasma-based processing reaction chamber. Further, the particle density in the plasma 16 ′ is further away from the surface of the integrated circuit layer 13 by lowering the first high-frequency power in the processing chamber using the plasma to the second high-frequency power through the first plasma purge step. Focus on location. Finally, the first plasma purge
Increasing the first reaction chamber pressure to the second reaction chamber pressure in the step reduces the concentration of particles 18 per mole of the first purge gas in the plasma-based processing reaction chamber.

The integrated circuit layer 13 on the semiconductor substrate 12 is removed by the first method of the first preferred embodiment of the plasma purging method of the present invention.
When exposed to integrated circuit layer processing using a plasma prior to the plasma purging step, an equivalent except that it does not benefit from the one-step plasma purging processing of the first preferred embodiment of the plasma purging method of the present invention. When the semiconductor substrate 12 is removed from the processing chamber using the plasma, fewer particles are found on the surface of the integrated circuit layer 13 as compared to the integrated circuit layer 13.

In order to obtain the superior performance of the plasma purge method of the first preferred embodiment of the method of the present invention, a second plasma purge step immediately after the first plasma purge step is used if necessary. It is possible to FIG. 3 is a schematic cross-sectional view of electrodes and plasma in a processing reaction chamber using plasma in the second plasma purge processing step.
Is shown in The schematic cross-sectional view of FIG. 3 shows that the size of the plasma 16 ′ shown in FIG.
It is similar to the schematic sectional view shown in FIG. 2 except that it reaches 6 ″. In addition, the planes of the dense particles 18 are continuously polarized and are located further away from the surface of the integrated circuit layer 13 of FIG.

The second plasma purge step is preferably performed for a second plasma purge time of about 5 to about 15 seconds. The second plasma purge step preferably utilizes a second purge gas mixture, a third RF power and a third reaction chamber pressure. Preferably, the second purge gas mixture is equivalent to the first purge gas mixture. Preferably, the third high frequency power is comparable to the second high frequency power and the third reaction chamber pressure is the second high frequency power.
Lower than reaction chamber pressure.

To provide optimal performance of the optional two-step plasma purge process of the first preferred embodiment of the method of the present invention, the third RF power is preferably the first plasma power. Second used in the purge step
It has been found experimentally to be about 20 to about 100 percent of the high frequency power. Similarly, the third reaction chamber pressure is the first
It has also been experimentally found that it is on the order of about 50 percent of the second chamber pressure utilized in the plasma purge step.

In the second plasma purge step, the purpose of the second purge gas is to use the first plasma purge
After the step, the continuous scientific and physical etching of any particles 18 that are continuously present in the processing chamber using the plasma. Further, by continuously lowering the high-frequency power from the first plasma purge step to the second plasma purge step, the plasma 1 disposed away from the surface of the integrated circuit layer 13 is reduced.
The particles 18 present in 6 'are continuously polarized. Finally, by reducing the reaction chamber pressure again from the first plasma purge step to the second plasma purge step, a significant amount of the second purge gas is entrained in that amount of the second purge gas. With the particles 18 removed, they are removed from the reaction chamber.

It is also known in the art that integrated circuit layer processing using a plasma is generally facilitated or modified through the application of a magnetic field during integrated circuit layer processing using such a plasma. Processing using plasma of the first preferred embodiment of the plasma purging method of the present invention,
The first plasma purge step and the optional second plasma purge step benefit from the application of such magnetic fields as needed. To that end, (1) the use of plasma to incorporate magnets near the cathode and anode electrodes in the reaction chamber, and (2) the processing reaction using plasma, for example, electron cyclotron resonance (ECR) means. There are a number of ways to introduce a magnetic field into a plasma-based processing reaction chamber, including, but not limited to, generating a magnetic field through external means. For the first preferred embodiment of the plasma purge method of the present invention, a magnetic field is required during the plasma-based process, the first plasma purge process step, and the optional second plasma purge process step. Exists accordingly. The magnetic field, if present, is preferably on the order of about 100 gauss.

Upon completing the optional second plasma purge step, the one-step plasma purge process of the first preferred embodiment of the plasma purge method of the present invention is expanded to include the present invention. Two steps performed as needed in the first preferred embodiment of the plasma purge method
Provides a plasma purge process. The plasma of the present invention
The integrated circuit layer processed in the processing using plasma prior to the optional two-step plasma purging of the first preferred embodiment of the purging method comprises (1)
A similar integrated circuit layer that does not benefit from the optional two-step plasma purge process of the first preferred embodiment of the plasma purge method of the present invention, or (2)
One of the first preferred embodiments of the plasma purge method of the present invention
Shows fewer surface contaminant particles than a similar integrated circuit layer that benefited only from the step plasma purge process.

The one-step plasma purging process of the present invention or a two-step plasma purge performed as necessary
In addition to the first preferred embodiment of the plasma purging method of the present invention relating to the general application of the purging process, one step of the first preferred embodiment of the plasma purging method of the present invention or two steps performed as necessary There are two additional preferred embodiments of the plasma purge method of the present invention relating to integrated circuit layer processing using a specific plasma prior to the plasma purge processing. The first additional embodiment relates to the plasma purge process of the first preferred embodiment of the plasma purge method of the present invention following the silicon oxide integrated circuit layer etching process using plasma. This embodiment is
5 illustrates a second preferred embodiment of the plasma purge method of the present invention. A second additional embodiment is a first embodiment of the plasma purge method of the present invention following an integrated circuit layer deposition process using a plasma.
It relates to a plasma purge process of a preferred embodiment. This embodiment represents a third preferred embodiment of the plasma purge method of the present invention.

With respect to the second preferred embodiment of the plasma purge method of the present invention, a silicon oxide integrated circuit layer etching process using a plasma is generally known in the integrated circuit fabrication art. Such processing is typically performed in a processing chamber using plasma at a high frequency power and reaction chamber pressure within the specified ranges for the plasma-based processing of the first preferred embodiment of the plasma purge method of the present invention. In addition, a number of methods for forming a silicon oxide integrated circuit layer on a semiconductor substrate are also generally known. These methods include chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), spin-on-glass (SO
G) Including but not limited to vapor deposition and physical vapor deposition (PVD) sputtering. Any of the above-described vapor deposition methods is used when forming a silicon oxide integrated circuit layer on which the plasma purge processing of the second preferred embodiment of the plasma purge method of the present invention is performed.

Accordingly, to implement the second preferred embodiment of the plasma purge method of the present invention, a silicon oxide integrated circuit layer is first formed on a semiconductor substrate. The silicon oxide integrated circuit layer is then etched through processing using a plasma. The plasma as the silicon oxide integrated circuit layer is etched is then purged by the first preferred embodiment of the plasma purge method of the present invention.

For the second embodiment of the plasma purging method of the present invention, the treatment using the plasma in which the silicon oxide integrated circuit layer is etched preferably comprises (1) about 60
A first radio frequency of 0 to about 950 watts; (2) a first reaction chamber pressure of about 200 to about 300 mTorr;
A reactant gas mixture of 00 standard cubic centimeters / minute (sccm) trifluoromethane, about 65 to about 100 standard cubic centimeters / minute carbon tetrafluoride and about 40 to about 80 standard cubic centimeters / minute argon; and (4) about 20 A magnetic field strength of ~ 100 Gauss is utilized.

For the second preferred embodiment of the plasma purge method of the present invention, the first plasma purge step is preferably (1) a second radio frequency of about 250 to about 350 watts, and (2) about 400 to 400 watts. A second reactor pressure of about 900 mTorr, (3) a first oxygen oxidation purge gas component of about 100 to about 300 standard cubic centimeters / minute (sccm), and (4) a magnetic field strength of about 20 to about 100 Gauss. . Optionally, for the second preferred embodiment of the plasma purge method of the present invention, the second plasma purge step preferably comprises: (1) a third step of about 50 to about 150 watts;
High frequency, (2) third reaction chamber pressure on the order of about 200 mTorr, (3) third oxygen oxidation purge gas component at about 100 to about 200 standard cubic centimeters / minute (sccm), and (4) about 20 to about 100 gauss. Utilizing the magnetic field strength of

In the second preferred embodiment of the plasma purging method of the present invention, the silicon oxide integrated circuit layer etching process using plasma prior to one step or two-step plasma purging performed as required An etched silicon oxide integrated circuit layer is formed on the semiconductor substrate, and the etched silicon oxide integrated circuit layer can be used as a step of the second preferred embodiment of the plasma purge method of the present invention or as needed. Fewer contaminant particles are deposited on the surface than similarly etched silicon oxide integrated circuit layers that do not benefit from exposure to the two-step plasma purge process that occurs.

With respect to the third preferred embodiment of the plasma purge method of the present invention, treatment with a plasma on which a silicon oxide integrated circuit layer is deposited is also known in the art. Processing using such a plasma typically utilizes a suitable silicon source reactive gas such as silane and tetraethyl orthosilicate (TEOS). Both of these two silicon source reactive gases are utilized in the third preferred embodiment of the plasma purge method of the present invention.

For the third preferred embodiment of the plasma purge method of the present invention, treatment with a plasma wherein the silicon oxide integrated circuit layer is deposited from a silane or tetraethyl orthosilicate (TEOS) silicon source reactive gas is preferred. Include (1) a first of about 200 to about 700 watts;
High frequency power, (2) a first reaction chamber pressure of about 500 to about 3000 mTorr, and (3) a silicon source reactive gas of about 100 to about 600 standard cubic centimeters / minute (sccm) are utilized. No magnetic field is normally used in this process.

For the third preferred embodiment of the plasma purge method of the present invention, the one-step plasma purge process preferably comprises: (1) a second radio frequency of about 50 to about 30 watts; A second reactor pressure of about 7000 mTorr is utilized, and (3) an oxygen oxidation purge gas component of about 100 to about 200 standard cubic centimeters / minute.
Similarly, for the third preferred embodiment of the plasma purge method of the present invention, the optional second plasma purge step is preferably (1) a third RF power of about 20 to about 150 watts. (2) a third reaction chamber pressure of the order of about 500 mTorr and (3) an oxygen oxidation purge gas component at a flow rate of about 100 to about 200 standard cubic centimeters / minute (sccm).

In the third preferred embodiment of the plasma purging method of the present invention, a semiconductor oxide layer is deposited using a plasma prior to one-step or two-step plasma purging performed as needed. A silicon oxide integrated circuit layer is deposited on the substrate, and the silicon oxide integrated circuit layer is deposited in one step of the third preferred embodiment of the plasma purging method of the present invention, or in a two-step plasma processing performed as needed. Fewer contaminant particles deposit on the surface than similarly deposited silicon oxide integrated circuit layers that do not benefit from exposure to the purge process.

<Example> Three series of 8-inch wide semiconductor substrates are
They had a silicon oxide integrated circuit layer formed on their surface. The silicon oxide integrated circuit layer is formed by either spin-on-glass silicon oxide integrated circuit layer processing or plasma enhanced chemical vapor deposition (PECVD) silicon oxide integrated circuit layer processing by methods and materials conventional in the art. Was. The thickness of the silicon oxide integrated circuit layer ranged from about 3000 to about 15,000 angstroms. All surfaces of the silicon oxide integrated circuit layer were measured through conventional techniques in the art to determine the level of surface contaminant particles pre-existing on these surfaces.

The silicon oxide integrated circuit layer on one of the three series of semiconductor substrates is then plasma-etched using the plasma-etch process outlined for the second embodiment of the plasma purge method of the present invention. Was exposed to The etching process using the plasma includes (1) a first RF power of about 850 watts, (2) a first reaction chamber pressure of about 260 mTorr, (3) trifluoromethane of about 40 standard cubic centimeters / minute, about 100
A reactant gas mixture of standard cubic centimeters per minute (sccm) of carbon tetrafluoride and about 50 standard cubic centimeters per minute of argon was used, and (4) a magnetic field strength of about 50 gauss.

Of the three series, the silicon oxide integrated circuit layer on the second semiconductor substrate was subjected to etching using the same plasma provided to the silicon oxide integrated circuit layer on the first series semiconductor substrate. . However, the silicon oxide integrated circuit layers on the second series of semiconductor substrates were further subjected to a one-step plasma purge process according to a second preferred embodiment of the plasma purge method of the present invention. The one-step plasma purge process includes (1) a second RF power of about 250 watts, (2) a second reaction chamber pressure of about 400 mTorr, (3) about 300 standard cubic centimeters / minute (sc)
cm) of the first oxygen oxidation purge gas component, (4) a magnetic field strength of about 50 Gauss, and (5) a first purge time of about 10 seconds.

Finally, the silicon oxide integrated circuit layer on the third semiconductor substrate wafer of the three series is optionally subjected to a two-step plasma according to the second preferred embodiment of the plasma purge method of the present invention. -Exposed to an etching process using plasma prior to the purging process. The silicon oxide integrated circuit layers on the third series of semiconductor substrates are etched using the same plasma as provided to the silicon oxide integrated circuit layers on the second semiconductor substrate wafer of the third series, and are subjected to one-step etching. Received plasma purge treatment. In addition, the silicon oxide integrated circuit layers on the third series of semiconductor substrates have also undergone an optional second plasma purge step according to a second embodiment of the plasma purge method of the present invention. The second plasma purge step includes: (1) a third RF power of about 100 watts;
(2) third reaction chamber pressure of about 50 mTorr, (3) about 20
0 standard cubic centimeters per minute (sccm) of a second oxygen oxidation purge gas component, (4) a magnetic field strength of about 60 Gauss,
And (5) utilized a second purge time of about 5 seconds.

Each silicon oxide integrated circuit layer was then re-measured to determine the level of surface contaminant particles added through the silicon oxide integrated circuit layer etching process using the plasma. The results of these measurements are reported in Table 1.

[0048]

[Table 1]

Considering the data in Table 1, one step
The plasma purge method of the present invention, when applied in the context of the second preferred embodiment of the plasma purge method of the present invention, either a plasma purge process or an optional two-step plasma purge process Contamination deposited on the surface from an equivalently etched silicon oxide integrated circuit layer that does not benefit from the one-step plasma purge process of the second preferred embodiment or the optional two-step plasma purge process It can be seen that this provides an etched silicon oxide integrated circuit layer with less material particles.

As will be appreciated by those skilled in the art, the preferred embodiments and examples of the present invention are illustrative of the invention rather than limitations of the invention. Modifications and changes to the methods and materials in which the preferred embodiments and examples of the present invention are practiced may result in additional embodiments and examples within the spirit and scope of the plasma purge method of the present invention as defined in the claims. .

[Brief description of the drawings]

The objects, features and advantages of the present invention will be understood in the context of the description of the preferred embodiment. The description of the preferred embodiments will be understood in the context of the accompanying drawings, which form an integral part of this disclosure.

FIG. 1 is a schematic cross-sectional view showing an electrode and a plasma in a processing reaction chamber using plasma in successive stages of a first preferred embodiment of the plasma purging method of the present invention (part 1).

FIG. 2 is a schematic cross-sectional view showing an electrode and a plasma in a processing reaction chamber using plasma in successive steps of the first preferred embodiment of the plasma purging method of the present invention (part 2).

FIG. 3 is a schematic cross-sectional view showing an electrode and a plasma in a processing reaction chamber using plasma in successive steps of the first preferred embodiment of the plasma purging method of the present invention (part 3).

Claims (26)

[Claims] A method for limiting the deposition of contaminant particles on an integrated circuit layer in a processing chamber using a plasma, the method comprising using a plasma on the integrated circuit layer in a processing chamber using a plasma. Performing the plasma-based process using the plasma-based process and a reactive gas mixture suitable for the integrated circuit layer, a first high-frequency power, and a first reaction chamber pressure; and Performing a first plasma purge step at a first purge time immediately after the treatment using the first plasma purge step, wherein the first plasma purge step includes reducing the first purge gas mixture, the second high frequency power, and the second reaction chamber pressure. Utilizing, wherein the second high frequency power is lower than the first high frequency power, and the second reaction chamber pressure is higher than the first reaction chamber pressure. The method comprising. 2. The method according to claim 1, wherein the processing using the plasma includes forming an integrated circuit layer using the plasma, removing the integrated circuit layer using the plasma, and modifying the integrated circuit layer using the plasma. A method selected from the group of processes using a plasma comprising the process. 3. The method of claim 1, wherein said integrated circuit layer is selected from a group of integrated circuit layers consisting of an integrated circuit conductor layer, an integrated circuit insulator layer, an integrated circuit semiconductor layer, and an integrated circuit photoactive layer. How to be. 4. The method of claim 1, wherein said first radio frequency power is between about 200 and about 950 watts and said first reaction chamber pressure is between about 200 and about 3000 mTorr. 5. The method of claim 1, wherein said first purge time is between about 5 and about 30 seconds. 6. The method of claim 1, wherein said first purge gas mixture comprises an oxidized first purge gas component. 7. The method of claim 6, wherein said oxidized first purge gas component comprises an oxygen oxidized first purge gas component. 8. The method of claim 7, wherein said oxygen-oxidized first purge gas component is provided at an oxygen flow rate of about 80-500 standard cubic centimeters / minute (sccm). 9. The method of claim 1, wherein the first purge gas mixture further comprises a non-oxidized first purge gas component in addition to the oxidized first purge gas component. 10. The method of claim 9, wherein the non-oxidized first purge gas component is an argon non-oxidized first purge gas component. 11. The method of claim 10, wherein the argon non-oxidized first gas component is provided at a flow rate of about 20 to about 200 standard cubic centimeters / minute (sccm). 12. The method of claim 1, wherein the second RF power is about 20 to 50 percent of the first RF power and the second reaction chamber pressure is about 150% of the first reaction chamber pressure. A method that is about 400 percent. 13. The method of claim 1, further comprising performing a second plasma purge step at a second purge time immediately after the first plasma purge step, wherein the second plasma purge step is performed. The step utilizes a second purge gas mixture, a third high frequency power and a third reaction chamber pressure, wherein the third high frequency power is about the same as the second high frequency power and the third reaction chamber pressure is the second reaction Method lower than chamber pressure. 14. The method of claim 13, wherein said second purge time is between about 5 and about 15 seconds. 15. The method according to claim 13, wherein said second purge gas mixture is equivalent to said first purge gas mixture. 16. The method of claim 13, wherein the third high frequency power is between about 20 and about 1 of the second high frequency power.
00%, and the third reaction chamber pressure is
A process that is on the order of about 50 percent of the reaction chamber pressure. 17. A method for limiting deposition of contaminant particles on a silicon oxide integrated circuit layer etched in a plasma-based processing reaction chamber, wherein the plasma-based processing reaction chamber includes: In the step of etching the silicon oxide integrated circuit layer, wherein the processing using the plasma utilizes a first reactive gas mixture, a first high frequency power and a first reaction chamber pressure, and immediately after the processing using the plasma. Performing a first plasma purge step during a first purge time of said first plasma purge step, wherein said first plasma purge step utilizes a first purge gas mixture, a second radio frequency power and a second reaction chamber pressure, 2 The high frequency power is lower than the first high frequency power and the second reaction chamber pressure is higher than the first reaction chamber pressure The method comprising the steps. 18. The method of claim 17, wherein the first high frequency power is between about 600 and about 950 watts,
The method wherein the first reaction chamber pressure is about 200 to about 300 mTorr. 19. The method of claim 18, wherein said second high frequency power is between about 250 to about 350 watts,
The method wherein the second reaction chamber pressure is from about 400 to about 900 mTorr. 20. The method according to claim 18, further comprising the step of immediately following the first plasma purge step.
Performing a second plasma purge step during a purge time, the second plasma purge step comprising: a second purge gas mixture, a third RF power, and a third
A method using a reaction chamber pressure, wherein the third high frequency power is substantially equal to the second high frequency power, and the third reaction chamber pressure is lower than the second reaction chamber pressure. 21. The method of claim 20, wherein the third RF power is between about 50 and about 150 watts and the third reaction chamber pressure is on the order of about 200 mTorr. 22. A method for limiting the deposition of contaminant particles on a silicon oxide integrated circuit layer deposited in a plasma-assisted reaction chamber, the plasma-assisted reaction chamber using plasma-assisted treatment. In the step of depositing a silicon oxide integrated circuit layer, wherein the processing using the plasma utilizes a second reactive gas mixture, a first high frequency power and a first reaction chamber pressure, and immediately after the processing using the plasma. Performing a first plasma purge step during a first purge time of said first plasma purge step, wherein said first plasma purge step utilizes a first purge gas mixture, a second radio frequency power and a second reaction chamber pressure, A method wherein the power is lower than the first high frequency power and the second reaction chamber pressure is higher than the first reaction chamber pressure. 23. The method of claim 22, wherein the first high frequency power is between about 200 and about 700 watts;
The method wherein the first reaction chamber pressure is about 500 to about 3000 mTorr. 24. The method of claim 23, wherein the second RF power is between about 50 and about 300 watts and the second reaction chamber pressure is between about 2000 and about 7000 mTorr. 25. The method according to claim 22, further comprising the step of immediately following the first plasma purge step.
Performing a second plasma purge step during a purge time, wherein the second plasma purge step utilizes a second purge gas mixture, a third RF power and a third reaction chamber pressure, and the third RF power Is the same as the second high frequency power, and the third reaction chamber pressure is lower than the second reaction chamber pressure. 26. The method of claim 25, wherein the third RF power is between about 20 and about 150 watts and the third reaction chamber pressure is on the order of about 500 mTorr.