JPH11176166A - Semiconductor storage device - Google Patents

Abstract

(57) Abstract: A semiconductor memory device capable of switching internal timing by an ATD pulse generation circuit by changing a bonding specification when different power supply voltage specifications are realized on the same chip. A 1-Mbyte wide high-speed SRAM comprising a memory mat including a plurality of memory cells, a row / column decoder, an address buffer, a sense amplifier for detecting and amplifying data, an input / output circuit for inputting / outputting data,
ATD pulse generation circuit for generating TD pulse signal, AT
It is composed of an ATD pulse grouping circuit for collecting and synthesizing D pulses, a read / write control circuit for generating an equalize / control signal, and the like. The voltage level of the internal timing adjustment signal ITC of the ATD pulse generation circuit ATDPG is changed by changing the bonding specification. By changing the pulse width to HIGH or LOW, the pulse width is switched to adjust the internal timing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device technology, and more particularly, to a case where different power supply voltage specifications such as a 5V version and a 3.3V version are realized on the same chip. The present invention relates to a technique that is effective when applied to a semiconductor memory device suitable for timing design with activation of an amplifier.

[0002]

2. Description of the Related Art For example, as a technique studied by the present inventor, an address buffer and an ATD have been proposed for a 1-Mbyte wide high-speed SRAM as an example of a semiconductor memory device.
(Address Transition Detector) In a pulse generating circuit, a method of adjusting a pulse width of an ATD pulse signal by cutting a trimming fuse at the time of 3.3V operation is generally used.

A semiconductor memory device such as an SRAM is disclosed in, for example, November 30, 1984.
Published by Ohmsha Co., Ltd.
SI Handbook ", pages 485 to 530, and the like.

[0004]

In the above-described SRAM address buffer and ATD pulse generation circuit, since the product development of a 5V / 3.3V product is performed in a fuse cutting step, a stock step in production is required. It is conceivable that it occurs in both the pre-process and the post-process. For example,
As shown in the example of the circuit diagram of FIG.
The internal timing by the TDPG is such that the fuse trimming is performed at the HIGH level due to the non-cutting of the adjusting fuse at the time of 5V operation, and at the LOW level due to the cutting at the time of 3.3V operation.

Therefore, the present inventor has proposed an address buffer ABUF in an address buffer ABUF and an ATD pulse generation circuit ATDPG as shown in the circuit diagram of FIG.
Noting that the adjustment of the logic threshold value of the ATD is switched by changing the bonding specification, the ATD pulse generation circuit A
It has been conceived that the TDPG can be similarly switched by changing the bonding specification.

Therefore, an object of the present invention is to provide a 5V version and a 3.3V version.
When realizing different power supply voltage specifications such as a plate, etc. on the same chip, a semiconductor memory device which can add logic instead of a signal by a trimming fuse and switch an internal timing by an ATD pulse generation circuit by changing a bonding specification. To provide.

[0007] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the semiconductor memory device according to the present invention has an ATD pulse generation circuit that switches the internal timing based on the ATD pulse signal by changing the bonding specification. For example, in the 5V version and the 3.3V version, a signal that is activated only at the time of 3.3V operation is logically added to the ATD pulse generation circuit instead of the signal by the trimming fuse.

This ATD pulse generation circuit has a delay circuit composed of a plurality of stages which can be adjusted to a desired pulse width by changing the bonding specification. The bonding specification is changed by the same bonding specification change as the function change of the semiconductor memory device. The switching and the change of the bonding specification are performed by connecting to a desired voltage level by wire bonding or wireless bonding, and the present invention is particularly applied to an SRAM or the like that realizes different power supply voltage specifications on the same chip.

Therefore, according to the semiconductor memory device, the same effect as the fuse cutting can be obtained by switching the bonding. Therefore, when a product is developed by a bonding option, the timing of the developed product can be adjusted, and the characteristics can be improved. Can be. Furthermore, since the stock process in product production is only a post-process, the possession of defective assets in the pre-process can be reduced.

Also, compared to fuse trimming, the risk of erroneous cutting of the fuse due to laser irradiation can be avoided, and bonding can be performed after confirming the effect of trimming by probe inspection, so that safety is high. The early launch can shorten the prototype and evaluation period.

Further, when a variety of product types are developed on one chip, if a shift in internal timing can be predicted in advance, a signal for pulse width adjustment is associated with a signal for product type switching, so that product type switching and its The optimum pulse width adjustment for each product type can be performed at the same time, and even after mass production, the stock process of the product becomes only the post process, and it can respond quickly to customer requirements.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is an overall block diagram showing a semiconductor memory device according to one embodiment of the present invention, FIG. 2 is a block diagram showing an ATD pulse generation circuit of the semiconductor memory device in this embodiment, and FIG. FIG. 4 is a timing chart showing a read operation, and FIG. 5 is a timing chart for explaining an example of the influence of a change in the ATD pulse width.

First, the configuration of the semiconductor memory device according to the present embodiment will be described with reference to FIG.

The semiconductor memory device of the present embodiment is, for example, a 1-Mbyte wide high-speed SRAM, and has a word line WL.
MMAT composed of a plurality of memory cells MC arranged at the intersection of the data line DL, a row decoder RDEC and a column decoder CDEC for selecting an arbitrary memory cell MC in the memory mat MMAT, and an address signal. Address buffer ABUF for generating a row / column address signal and detecting output data.
A sense amplifier SA for amplification, an input / output circuit DI / O for inputting / outputting data, and an ATD for generating an ATD pulse signal
It comprises a pulse generating circuit ATDPG, an ATD pulse collecting circuit ATDPI for collecting and synthesizing ATD pulses, a read / write control circuit RWC for generating an equalize / control signal, and the like.

In this SRAM, an address signal A is externally input to an address buffer ABUF, a row address signal and a column address signal are generated, and input to a row decoder RDEC and a column decoder CDEC, respectively. An arbitrary memory cell MC is selected. The input / output data DI / DO is input via the input / output circuit DI / O at the time of the write operation, and the sense amplifier SA and the input / output circuit DI / O at the time of the read operation.
Is output via.

The address signal A is input to an ATD pulse generation circuit ATDPG through an address buffer ABUF. The ATD pulse generation circuit ATDPG generates a basic ATD pulse signal ATDP. The pulse signal ATDP is synthesized, and is synthesized by the read / write control circuit RWC with the chip select signal / CS, the write enable signal / WE, etc., and the data line equalize signal DTEQ and the common data line equalize signal CDE
ATD pulse signals such as Q, a sense amplifier equalize signal SAEQ, and a sense amplifier control signal SAC are generated. The ATD pulse signal is sent to various internal circuits and used for equalizing and controlling a data reading system.

In particular, the ATD pulse generation circuit ATDPG in the present embodiment includes a delay circuit DEL and an exclusive OR circuit EOR as shown in FIG. 2, for example, and receives a signal from an address buffer ABUF as one input. Is input to an exclusive-OR circuit EOR via a delay circuit DEL, and is adjusted to a desired pulse width. The delay circuit DEL has a plurality of stages, the number of stages is controlled by the internal timing adjustment signal ITC, and the delay becomes the pulse width as it is.

Next, referring to FIG.
A specific circuit configuration of the UF and ATD pulse generation circuit ATDPG will be described. Here, an example of a circuit that can cope with the 5 V operation and the 3.3 V operation is shown.

The address buffer ABUF includes, for example, inverters IV1 to IV6 and a PMOS transistor TP
1 and TP2, and receives an external address signal A as an input, a row decoder RDEC and a column decoder CDE.
A selection signal ST / non-selection signal SB for C is branched into two systems and output via inverters IV1 to IV6 connected in cascade. The logic threshold value adjustment signal VLTC is input to the gate of the PMOS transistor TP1 on the power supply voltage VCC side connected in series between the connection node between the inverters IV1 and IV2 and the power supply voltage VCC. High voltage level (5V operation)
/ LOW (at 3.3 V operation), the inverters IV1 to I
The logic threshold of V6 is adjusted.

ATD pulse generation circuit ATDPG
Are, for example, inverters IV7, IV8, IV11 and P
A delay circuit DEL having MOS transistors TP3 to TP5 and NMOS transistors TN1 to TN3, inverters IV9 and IV10, and a PMOS transistor TP
6, TP7 and an exclusive OR circuit EOR having NMOS transistors TN4 and TN5. The delay circuit DEL receives a signal from the address buffer ABUF as an input.
Thus, the basic ATD pulse signal ATDP is generated after being adjusted to a desired pulse width. This ATD pulse signal AT
The pulse width of the DP is the same as the CMOS of the last stage of the delay circuit DEL.
P connected to the power supply voltage side and the ground voltage side of the circuit, respectively.
MOS transistor TP4 and NMOS transistor TN
3 is controlled by the internal timing adjustment signal ITC input to
The internal timing is adjusted by GH (at the time of 5V operation) / LOW (at the time of 3.3V operation).

In the address buffer ABUF and the ATD pulse generation circuit ATDPG configured as described above, the voltage level of the adjustment signal is simultaneously switched by changing the bonding specification.
When it is set to the IGH level, it is connected to the power supply voltage VCC, and when it is set to the LOW level during 3.3 V operation, it is connected to the ground voltage GND. In this case, the logic threshold adjustment signal VLTC and the internal timing adjustment signal ITC
Both have the same voltage level at the time of 5V operation and 3.3V operation, so they can be connected to one bonding pad BPAT. However, if the voltage levels are different, they are connected to different bonding pads. Will be.

Next, the operation of this embodiment will be described with reference to FIG.
The read operation of the SRAM will be described with reference to FIG.

First, in synchronization with the activation of the address signal A input to the address buffer ABUF, the basic ATD pulse signal ATDP generated from the ATD pulse generation circuit ATDPG is set to the HIGH level, and the word line WL and the column selection signal are selected. The switch YS is activated to select a desired memory cell MC in the memory mat MMAT.

Further, an ATD pulse generation circuit ATDPG
Read / write control circuit RWC in synchronization with the transition of ATD pulse signal ATDP to LOW level from
, The data line DL is activated by a data line equalize signal DTEQ and the common data line CDL is activated by a common data line equalize signal CDEQ.

Then, the LO of the ATD pulse signal ATDP is
The sense amplifier output SAO is activated by the sense amplifier control signal SAC generated from the read / write control circuit RWC in synchronization with the shift to the W level, and the data of the selected memory cell MC is input / output circuit DI / O.
Can be read out via

Next, an example of the influence of a change in the pulse width of the ATD pulse signal ATDP in the read operation will be described with reference to FIG.

In this read operation, the word line W
L and the data line DL are activated, a sense amplifier control signal SAC for determining the timing of the read operation is provided.
, But this sense amplifier control signal SA
The pulse width of C affects read data.

For example, when the power supply voltage specifications such as the 5V operation and the 3.3V operation are realized on the same chip, when the process varies, the internal timing is shifted from an appropriate design value. If the width is narrow, an erroneous operation of reading erroneous data occurs. If the pulse width is wide, access delay occurs.

Therefore, in the present embodiment, the voltage level of the internal timing adjustment signal ITC of the ATD pulse generation circuit ATDPG shown in FIG.
By changing the bonding specification to a HIGH or LOW voltage level as in the case of the BUF logical threshold value adjustment signal VLTC, the internal timing can be adjusted by switching the pulse width of the sense amplifier control signal SAC.

For example, as shown in FIG.
When the GH level is set, the ATD pulse generation circuit AT
The pad for the internal timing adjustment signal ITC of the DPG is connected to the pad for the power supply voltage VCC by wire bonding or wireless bonding such as a flip chip method, a beam lead method, or a tape carrier method. Also,
To set the LOW level at the time of 3.3 V operation, the pad for the internal timing adjustment signal ITC is connected to the pad for the ground voltage GND.

As described above, when the power supply voltage specifications such as the 5V operation and the 3.3V operation are realized on the same chip, the pulse width is narrow or the internal timing is widely shifted from the design value. Even in such a case, it is possible to prevent erroneous data reading and access delay by adjusting the pulse width to an appropriate value.

Further, such an ATD pulse signal ATD
The effects of control and equalization by P include the data line DL, the common data line CDL, and the sense amplifier output S.
By shorting pairs of different potentials such as AO and input / output data buses to have the same potential, the inversion time of those potentials can be reduced. In addition, current consumption can be reduced by pulse driving the internal operation circuit for a required time. Further, the operation margin of the product can be adjusted by adjusting the pulse width.

Therefore, according to the semiconductor memory device of the present embodiment, the signal for adjusting the logical threshold value of the inverter in the address buffer ABUF is replaced by the ATD pulse generation circuit ATDPG instead of the signal by the trimming fuse.
The ATD pulse generation circuit AT
The logic threshold value of the inverter in the address buffer ABUF and the internal timing can be simultaneously switched only by switching the internal timing adjustment signal ITC of the DPG by bonding.

Therefore, since the same effect as that of fuse cutting can be obtained by switching the bonding, the following effects can be obtained.

(1) When the product type is developed by the bonding option, the timing of the developed product can be adjusted.
The characteristics can be improved.

(2) Since the stock process for product production is only the post-process, possession of defective assets in the pre-process can be reduced.

(3) As compared with fuse trimming, it is possible to avoid the danger of cutting mistake when the fuse is cut by laser irradiation.

(4) Since trimming is performed by pad input, bonding can be performed after confirming the effect of trimming by probe inspection, so that safety is high, and the product can be started up early, shortening the trial production and evaluation period. can do.

(5) When a variety of product types are developed on one chip by a bonding option, if the shift of the internal timing due to product type development can be predicted in advance, the internal timing adjustment of the pulse width adjustment for the signal for product type switching is performed. By entanglement of the use signal, it is possible to simultaneously switch the type and adjust the pulse width optimal for the type.

(6) Even after mass production, trimming by fuse cutting is not performed, so that the product stock process becomes only a post process, and it is possible to quickly respond to customer requirements.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and various modifications may be made without departing from the gist of the invention. It goes without saying that it is possible.

For example, in the above embodiment, 5
The case where the power supply voltage specifications of the V operation and the 3.3V operation are realized on the same chip has been described. However, the present invention is not limited to this. The present invention can be applied to such a case.

Further, in addition to the change based on the power supply voltage specification, the same bonding specification can be used for changing various functions of the semiconductor memory device, such as a change in input / output bit configuration such as a × 4 or × 16 bit product. Can be.

Although the description has been given of the case where the present invention is applied to the SRAM, it goes without saying that the present invention can be applied to other products such as a DRAM having a trimming fuse for timing adjustment.

[0048]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1) By providing an ATD pulse generation circuit for switching the internal timing by changing the bonding specification, the same effect as the fuse cutting can be obtained by switching the bonding. The characteristics can be improved by adjusting the timing of the developed product.

(2) Due to the bonding option, the stock process for product production is performed only in the post-process, so that possession of defective assets in the pre-process can be reduced.

(3) Compared with fuse trimming, it is possible to avoid the danger such as mistaken cutting of a fuse due to laser irradiation.

(4) Since the trimming is performed by pad input, the bonding can be performed after confirming the effect of the trimming by the probe inspection. Therefore, the safety is high, and the early production start-up of the product allows the trial production and evaluation period to be reduced. Shortening becomes possible.

(5) When a variety of product types are developed on one chip by a bonding option, if a shift in internal timing can be predicted in advance, a signal for pulse width adjustment can be associated with a signal for product type switching. Therefore, it is possible to simultaneously switch the type and adjust the pulse width optimal for the type.

(6) Even after mass production, trimming by fuse cutting is not performed, so that the product stock process becomes only a post process, and it is possible to quickly respond to customer requirements.

(7) According to the above (1) to (6), in a semiconductor memory device such as an SRAM realizing different power supply voltage specifications on the same chip, switching the internal timing by the ATD pulse generation circuit by changing the bonding specification. Can improve the characteristics in product development, reduce the possession of defective assets in the previous process, shorten the prototype / evaluation period,
It is possible to quickly respond to customer requests.

[Brief description of the drawings]

FIG. 1 is an overall block diagram showing a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an ATD pulse generation circuit of the semiconductor memory device according to one embodiment of the present invention.

FIG. 3 is a circuit diagram showing a specific example of an address buffer and an ATD pulse generation circuit in one embodiment of the present invention.

FIG. 4 is a timing chart showing a read operation in one embodiment of the present invention.

FIG. 5 is a timing chart for explaining an example of the influence of a change in the ATD pulse width in one embodiment of the present invention.

FIG. 6 shows a semiconductor memory device as a premise of the present invention;
FIG. 3 is a circuit diagram showing a specific example of an address buffer and an ATD pulse generation circuit.

[Explanation of symbols]

 A address signal ABUF address buffer ATDP ATD pulse signal ATDPG ATD pulse generation circuit ATDPI ATD pulse aggregation circuit BPAT bonding pad CDEC column decoder CDEQ common data line equalize signal CDL common data line DEL delay circuit DL data line DI / DO input / output data DI / O Input / output circuit DT Data line DTEQ Data line equalize signal EOR Exclusive OR circuit GND Ground voltage ITC Internal timing adjustment signal IV1 to IV11 Inverter MC Memory cell MMAT Memory mat RDEC Row decoder RWC Read / write control circuit SA Sense amplifier SAC Sense amplifier control signal SAEQ Sense amplifier equalize signal SAO Sense amplifier output ST selection Signal SB Non-selection signal TN1 to TN5 NMOS transistors TP1 to TP7 PMOS transistor VCC Power supply voltage VLTC Logic threshold adjustment signal WL Word line YS Column selection switch

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Takeshi Fukazawa 3-1-1 Higashi Koigabo, Kokubunji-shi, Tokyo Inside Hitachi Ultra-SII Engineering Co., Ltd.

Claims (5)

[Claims] 1. A semiconductor memory device comprising: an ATD pulse signal generating circuit which receives an address signal from an address buffer as an input, generates an ATD pulse signal, and switches an internal timing based on the ATD pulse signal by changing a bonding specification. 2. The semiconductor memory device according to claim 1, wherein said ATD pulse generation circuit has a delay circuit having a plurality of stages which can be adjusted to a desired pulse width by changing said bonding specification. Semiconductor storage device. 3. The semiconductor memory device according to claim 1, wherein the bonding specification is switched by a change in the same bonding specification as a change in a function of the semiconductor storage device. 4. The semiconductor memory device according to claim 2, wherein said bonding specification is changed by connecting to a desired voltage level by wire bonding or wireless bonding. . 5. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is an SRAM that realizes different power supply voltage specifications on the same chip. .