JPH11175407A - System setting data protection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the protection of system setting data in a system setting data protecting circuit. SOLUTION: The state of a switch means 17 at the time of supplying a power source or at the time of resetting hardware is held by a state storing means 18 and the permission and inhibition of writing for the semiconductor memory part 11 is switched and controlled by a switching controlling means 19 for protecting system setting data preserved in a semiconductor memory part 11 backed-up by a battery.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system setting data protection circuit for protecting a system setting data by preventing illegal data writing due to a malfunction of a program to a semiconductor memory section for storing system setting data of a personal computer. In recent personal computers, system setting data is stored in a semiconductor memory unit including a battery-backed nonvolatile storage memory. However, since these semiconductor memory units can be easily written from a user program or the like, incorrect data is written due to a malfunction of the program, and in the worst case, the system cannot be started. Therefore, there is a demand for the development of a system setting data protection circuit that can prevent such a problem from occurring.

[0002]

2. Description of the Related Art As a conventional system setting data protection circuit, for example, there is one as shown in FIG.
3-58700 gazette). In FIG. 12, 10
Reference numeral 1 denotes a write control unit; and 102, a nonvolatile memory to which a write address 103 and write data 104 are input from the write control unit 101. A write signal line 105 is provided between the write control unit 101 and the nonvolatile memory 102,
The write signal line 105 is provided with a dip switch 106 as switching means for switching between permission and prohibition of supply of the write instruction signal. This dip switch 10
6 prevents the writing instruction signal from being supplied to the nonvolatile memory 102 except when the storage content of the nonvolatile memory 102 is changed.

Another conventional example is shown in FIG.
(See JP-A-2-93746). In FIG. 13, reference numeral 111 denotes a CPU;
Is a ROM in which a control program for controlling the CPU 111 is stored, 113 is a RAM as a write memory, 114
Is a memory protect switch, 115 is a NAND circuit, 1
16 is an AND circuit, 117 and 118 are OR circuits.
When writing to a predetermined area of the RAM 114 is prohibited by the memory protect switch 114, writing to the predetermined area of the RAM 113 is prohibited as in the related art, while writing to the predetermined area of the RAM 113 is permitted by the memory protect switch 114. In the state where the CPU 111
Writing to a predetermined area 113 is permitted.

[0004]

However, in such a conventional system setting data protection circuit, even in the case of FIG. 12 and FIG. There is a changeover switch that switches between permission and prohibition,
In some cases, the user operates the system without noticing that the changeover switch has been switched by an erroneous operation of the user and is in a writable state.

As a result, there has been a problem that the system setting data cannot be sufficiently protected. The present invention has been made in view of such a conventional problem, and has as its object to provide a system setting data protection circuit capable of improving protection of system setting data.

[0006]

In order to achieve this object, the present invention is configured as shown in FIG. According to a first aspect of the present invention, there is provided a system setting data protection circuit for protecting system setting data stored in a semiconductor memory unit 16 backed up by a battery, wherein permission and prohibition of a write signal to the semiconductor memory unit 16 are set. Switch means 17 for which switching can be arbitrarily changed by a user, state storage means 18 for holding the state of the switch means 17 at power-on or hardware reset, and the write signal and output of the state storage means 18 And a switching control means 19 for switching between permitting and prohibiting writing to the semiconductor memory unit 16 when the data is inputted.

According to a second aspect of the present invention, in the system setting data protection circuit according to the first aspect, a discriminating means for discriminating an output of the state storage means 18 when power is turned on or a hardware reset, and wherein the discriminating means is the semiconductor Memory unit 1
And a warning notifying unit for notifying a warning when it is determined that writing to the No. 6 is permitted.

According to the present invention having such a configuration,
Even if the user operates the switch unit 17 erroneously, such as touching the switch unit 17 by mistake, the state of the switch unit 17 at the time of turning on the power or resetting the hardware is maintained.
Since writing permission and prohibition of writing to the semiconductor memory unit 16 are controlled by switching, the prohibition of writing to the semiconductor memory unit 16 is maintained until the power is turned on again or the reset switch is turned on again, thereby protecting the system setting data. Can be improved.

When it is desired to determine that writing to the semiconductor memory unit 16 is permitted at the time of system startup, a warning is issued to alert the user, so that protection of system setting data can be improved. .

[0010]

FIG. 2 is a diagram showing a personal computer in which a system setting data protection circuit according to the present invention is used. In FIG. 2, reference numeral 1 denotes a CPU;
Are connected to a ROM 3 and a RAM 4 via a bus 2. A control program and the like are stored in the ROM 3, and the RAM 4 is used as a work area. Also, CP
A display unit 8, a printer 9, and an input unit 10 such as a keyboard are connected to U1 via interface units 5, 6, and 7, respectively.

The CPU 1 is connected to a RAM 11 composed of a non-volatile memory. The RAM 11 stores system setting data such as boot device selection data. Therefore, the RAM 11 is backed up by the battery 12. The RAM 11 is provided with a system setting data protection circuit 13 for protecting system setting data stored in the RAM 11. The system setting data protection circuit 13 includes a reset switch 14
Is connected, and when the reset switch 14 is turned on, a reset signal is output to the system setting data protection circuit 13. Also, when the power switch 15 is turned on,
A reset signal is output to the system setting data protection circuit 13.

FIG. 3 is a diagram showing a configuration example of the system setting data protection circuit 13 according to the first embodiment of the present invention.
In FIG. 3, reference numeral 16 denotes a semiconductor memory unit (RAM) as a nonvolatile memory. The semiconductor memory unit 16 is backed up by the battery 12 and stores system setting data, for example, boot device selection data. An address signal, a read signal, and a write signal are input to the semiconductor memory unit 16, data is read from a region indicated by the address signal by the read signal, and data is written to a region indicated by the address signal by the write signal.

Since the semiconductor memory unit 16 can be easily written from a user's program or the like, incorrect data is written due to a malfunction of the program, and in the worst case, the system cannot be started. For this reason, a system setting data protection circuit 13 is provided to prevent unauthorized data from being written. The system setting data protection circuit 13 includes a changeover switch 17 as a switch means that allows the user to arbitrarily change the permission and prohibition of the write signal to the semiconductor memory unit 16, and a switch at power-on or at a hardware reset. Switch 1
D flip-flop 18 as state storage means for holding the state of No. 7, and a switching control means for receiving a write signal and an output of the D flip-flop 18 and switching between permission and prohibition of writing requested to the semiconductor memory unit 17 And an AND circuit 19.

When the changeover switch 17 is turned off at the D input terminal of the D flip-flop 18, H from the power supply Vcc is output.
When the level voltage is input via the resistor 20 and the changeover switch 17 is turned on, the current from the power supply Vcc is
The current flows to the ground via the changeover switch 17, and an L-level voltage is input. That is, when the changeover switch 17 is turned off, the H level is inputted to the D input terminal of the D flip-flop 18, the Q output of the Q terminal becomes L level, and when the changeover switch 17 is turned off, the D flip-flop 18
L level is input to the D input terminal, and the Q output of the Q terminal becomes H level.

A reset signal is input to a clock input terminal of the D flip-flop 18. That is, when the reset switch 14 is turned on or the power-on switch 15 is turned on, a reset signal is input to the clock input terminal of the D flip-flop 18. When the reset signal changes from the L level to the H level, the Q output is determined by the D input of the D input terminal of the D flip-flop 18. That is, when the changeover switch 17 is on and the D input of the D input terminal is at the L level, the Q output is at the H level, and when the changeover switch 17 is off and the D input of the D input terminal is at the H level, the Q output is It becomes L level. When the reset signal changes from the H level to the L level, the Q output holds the previous state. Further, during the start-up of the system, for example, by touching the changeover switch 17 by mistake,
7, when the D input of the D input terminal of the D flip-flop 18 is switched from H level to L level, the Q output remains at L level until the next reset signal is input to the clock input terminal. Remains at the level.

FIG. 4 shows a time chart when the changeover switch 17 is turned on to enable writing. In FIG.
As shown in (A), when the changeover switch 17 is turned on, the power from the power supply Vcc flows from the changeover switch 17 to the ground via the resistor 20 and the D flip-flop 18
H level voltage is not input to the D input terminal of
As shown in (B), the D input is at the L level. (C)
As shown in the figure, the reset signal by the operation of the reset switch 14 or the power-on switch 15 is changed from H level to L level.
When the reset signal goes high again, the Q output of the D flip-flop 18 is indefinite until the reset signal goes high again as shown in FIG. Is at the L level,
Level. As shown in (E), when the write signal on the CPU 1 side goes to the H level and is input to the AND circuit 19, the Q output from the D flip-flop 18 is at the H level. Input signal is CPU1
It goes high in synchronization with the write signal on the side. Therefore,
Data can be written to the semiconductor memory unit 16.

FIG. 5 shows a time chart when the changeover switch 17 is turned off to make writing impossible. In FIG. 5, when the changeover switch 17 is turned off as shown in FIG. 5A, an H level voltage from the power supply Vcc is input to the D input terminal of the D flip-flop 18, and as shown in FIG. Becomes H level. When the reset signal by the operation of the reset switch 14 or the power-on switch 15 changes from the H level to the L level as shown in (C), and again becomes the H level, the Q output of the D flip-flop 18 becomes as shown in (D). It is indefinite until the reset signal goes high again, but when it goes high again, the D input goes high.
Since it is a level, it becomes an L level. As shown in (E), even if the write signal on the CPU 1 side changes from L level to H level, the Q output is at L level, and therefore, as shown in FIG. Memory unit 16
The write signal on the side remains at the L level. Therefore, no write signal is input to the semiconductor memory unit 16 and data writing is prohibited.

FIG. 6 shows a time chart when the changeover switch 17 is turned on by mistake during the write-disabled operation. 6, when the changeover switch 17 is off as shown in FIG. 6A, an H-level voltage from the power supply Vcc is input to the D input terminal of the D flip-flop 18, and as shown in FIG. , The D input is at the H level. As shown in (C), when the power-on switch 15 or the reset switch 14 is on, the reset signal is at the H level. Since the D input is at the H level, the Q output of the D flip-flop 18 is at the L level as shown in (D), and even if the write signal on the CPU 1 side is at the H level as shown in (E). , Semiconductor memory section 16
The write signal on the side remains at the L level, and writing of data to the semiconductor memory unit 16 is prohibited.

Here, as shown in FIG. 2A, when the user operates the changeover switch 17 erroneously by touching the changeover switch 17, the changeover switch 17 is turned on from off. Therefore, as shown in FIG.
The D input 8 changes from H level to L level. At this time,
As shown in (C), when the reset signal is at the H level, the Q output of the D flip-flop 18 does not change and remains at the L level. Therefore, as shown in FIG.
Even if the write signal on the PU1 side goes to the H level, the write signal on the semiconductor memory section 16 remains at the L level, and writing of data to the semiconductor memory section 16 remains prohibited.

Even when the reset signal changes from H level to L level, the state of the Q output is maintained at L level. Thereafter, when the reset signal changes from the L level to the H level again, the D output is at the L level, so that the Q output is at the H level. At this time, when the write signal on the CPU 1 side is at the H level, the semiconductor memory unit 16 side The write signal also goes high, and data writing is permitted. As described above, even if the user performs an erroneous operation, the prohibition of writing to the semiconductor memory unit 16 is maintained until the reset signal changes from the H level to the L level and changes to the H level again. as a result,
The protection of the system setting data can be improved.

FIG. 7 is a view showing a second embodiment of the present invention. In FIG. 7, an inverter circuit 21 to which the Q output of the D flip-flop 18 is input is provided, and a resistor 22 and a light emitting diode 23 are connected in series between the inverter circuit 21 and the power supply Vcc. Inverter circuit 21
Has a function as a discriminating means for discriminating whether the Q output of the D flip-flop 18 as the state storage means is at the H level or the L level when the power-on switch 15 or the reset switch 14 is turned on.

When the output of the inverter circuit 21 is at L level, the light emitting diode 23
It has a function as a warning notifying unit for warning that writing to is permitted. D flip-flop 18
Is at H level, the inverter circuit 21 is at H level.
The level input is inverted and the L level is output. When the output of the inverter circuit 21 becomes L level, a current flows from the power supply Vcc to the light emitting diode 23 via the resistor 22, and the light emitting diode 23 emits light to warn that writing to the semiconductor memory unit 16 is permitted. Other configurations are the same as those in FIG.

As described above, when writing to the semiconductor memory unit 16 is permitted at the time of starting the system, a warning is issued to alert the user. As a result, protection of system setting data can be improved. FIG. 8 is a diagram showing a third embodiment of the present invention. In FIG. 8, a three-state buffer 24 to which the Q output of the D flip-flop 18 is input is provided.
It becomes conductive by the read signal from PU1 and outputs the Q output of D flip-flop 18 to CPU1. CPU1
When the power-on switch 15 is turned on or the reset switch 14 is turned on, D
It has a function as a determination means for determining whether the Q output of the flip-flop 18 is at the H level or the L level via the three-state buffer 24, and determines the H level indicating that writing to the semiconductor memory unit 16 is permitted. If so, a warning is displayed on the display unit 8 as a warning notification unit.

That is, when the Q output of the D flip-flop 18 is at the H level, the three-state buffer 24
Is turned on by a read signal from the CPU, outputs an H level to the CPU 1, and when the Q output is at the L level,
1 is turned on by a read signal from the CPU 1 and outputs an L level to the CPU 1. FIG. 9 is a flowchart for explaining the processing of the CPU 1.

First, in step S1, the CPU 1 determines whether or not the Q output of the D flip-flop 18 is at the H level.
When the level is at the level, when the power-on switch 15 or the reset switch 15 is turned on, it is determined that writing to the semiconductor memory unit 16 is permitted, and the CPU 1 issues a warning to the display unit 8 in step S2. Display to alert the user. When the Q output is at L level,
When the power-on switch 15 is turned on or the reset switch 14 is turned on, it is determined that writing to the semiconductor memory unit 16 is prohibited, and step S
In step 3, normal processing is performed.

Also in this embodiment, the protection of the system setting data can be improved. FIG. 10 is a diagram showing a fourth embodiment of the present invention. In FIG. 10, 16
Is a semiconductor memory unit composed of a non-volatile memory. The semiconductor memory unit 16 is backed up by the battery 12 and stores system setting data. Semiconductor memory unit 1
6, an address signal, a read signal, and a write signal are input, and data is read or written. In this embodiment, data is written to the semiconductor memory unit 16 when the write signal is at the L level.

Reference numeral 18 denotes a D flip-flop as state storage means for holding the state of the changeover switch 17 as a switch when the power-on switch 15 is turned on or the reset switch 14 is turned on. When the changeover switch 17 is turned off, an H-level voltage from the power supply Vcc is input to the D input terminal via the resistor 20. When the changeover switch 17 is turned on, a current flows from the power supply Vcc to the resistor 20 and the changeover switch 17.
, And an L level voltage from the power supply Vcc is input.

A reset signal is input to the clock input terminal of the D flip-flop 18 when the power-on switch 15 is turned on or when the reset switch 14 is turned on. The Q output of the D flip-flop 18 holds the Q output when the reset signal changes from the H level to the L level, and changes to an output corresponding to the D input when the reset signal changes from the L level to the H level.

Numeral 25 denotes a three-state buffer as a switching control means for controlling permission and prohibition of writing to the semiconductor memory unit 16, and the three-state buffer 2
The write signal is input to 5, and the Q output of the D flip-flop 18 is input to the inversion control terminal. An H-level voltage from the power supply Vcc is constantly applied between the output side of the three-state buffer 25 and the write signal input terminal of the semiconductor memory unit 16.

When the Q output of D flip-flop 18 is at L level, three-state buffer 25 is conductive, and when the Q output is H level, three-state buffer 25 is not conductive. When three-state buffer 25 is in a non-conductive state, even if the write signal goes low, power supply Vcc
A voltage of a higher H level is supplied to the semiconductor memory unit 16 and the semiconductor memory unit 16 is in a write-protected state. When the Q output of the D flip-flop 18 is at the L level, the three-state buffer 25 conducts, and when the write signal goes to the L level, the semiconductor memory unit 16 enters a write-enabled state.

FIG. 11 shows a time chart when the user turns on the changeover switch 17 by mistake. In FIG. 11, as shown in FIG. 11A, when the user performs an erroneous operation such as touching the changeover switch 17, and the changeover switch 17 is switched from off to on, as shown in FIG. Is changed from the H level to the L level, but as shown in (C), the reset signal remains at the H level.
The Q output of flip-flop 18 remains at the H level. Therefore, the three-state buffer 25 is in a non-conducting state, and even if the write signal on the CPU 1 goes from H level to L level as shown in FIG. The write signal on the 16 side is the power supply Vcc
And remains at the H level due to the H level voltage from, and writing to the semiconductor memory unit 16 is prohibited.

Thereafter, as shown in (C), even if the reset signal changes from the H level to the L level, the Q output remains at the H level, the three-state buffer 25 becomes non-conductive, and the semiconductor memory unit is turned off. Writing to 16 is prohibited. Thereafter, when the power-on switch 15 is turned on again or the reset switch 14 is turned on again, the reset signal changes from L level to H level, and the Q output changes from H level to L level. Therefore, the three-state buffer 25 becomes conductive. At this time, when the write signal on the CPU 1 goes from the H level to the L level, a current flows from the power supply Vcc to the three-state buffer 25, and the write signal on the semiconductor memory unit 16 goes from the H level to the L level. 16 is allowed to be written.

As described above, even if the user operates the changeover switch 17 erroneously, writing to the semiconductor memory unit 16 is prohibited until the power-on switch 15 is turned on again or the reset switch 14 is turned on again. . Therefore,
The protection of the system setting data can be improved.
Also, in FIG. 10, as shown in FIGS. 1 and 8, the output of the D flip-flop 18 is determined to warn that writing to the semiconductor memory unit 16 is permitted at the time of starting the system. Needless to say, it is good.
Further, although the on / off switch is used as the changeover switch 17, the invention is not limited to this, and a mechanical switch may be used.

[0034]

As described above, according to the present invention, the state of the switch means at the time of turning on the power or resetting the hardware even when the switch means is erroneously operated by the user such as touching the switch means by mistake. The write-protection of the semiconductor memory unit is retained until the power is turned on again or the reset switch is turned on again in order to switch and control the writing permission and prohibition of the writing to the semiconductor memory unit. Protection can be improved.

When it is desired to determine that writing to the semiconductor memory unit is permitted when the system is started,
Since a warning is issued to alert the user, the protection of the system setting data can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 shows a personal computer in which the present invention is used.

FIG. 3 is a diagram showing a first embodiment of the present invention.

FIG. 4 is a time chart when writing is possible.

FIG. 5 is a time chart when writing is disabled.

FIG. 6 is a time chart when a changeover switch is turned on without writing.

FIG. 7 is a diagram showing a second embodiment of the present invention.

FIG. 8 is a diagram showing a third embodiment of the present invention.

FIG. 9 is a flowchart showing processing of a CPU;

FIG. 10 shows a fourth embodiment of the present invention.

FIG. 11 is a time chart for explaining the operation of FIG. 10;

FIG. 12 shows a conventional example.

FIG. 13 is a diagram showing another conventional example.

[Explanation of symbols]

 1: CPU 2: Bus 3: ROM 4, 11: RAM 5, 6, 7: Interface unit 8: Display unit 9: Printer 10: Input unit 12: Battery 13: System setting data protection circuit 14: Reset switch 15: Power supply Closing switch 16: Semiconductor memory unit 17: Changeover switch (switching means) 18: D flip-flop (state storage means) 19: AND circuit (switching control means) 20, 22: Resistor 21: Inverter circuit (discriminating means) 23: Light emission Diodes (warning notification means) 24, 25: three-state buffer

Claims (2)

[Claims] 1. A system setting data protection circuit for protecting system setting data stored in a semiconductor memory unit backed up by a battery, wherein a user can freely switch between enabling and disabling a write signal to the semiconductor memory unit. Switch means that can be changed to a state, state storage means for holding the state of the switch means at the time of power-on or hardware reset, and writing of the write signal and the output of the state storage means to the semiconductor memory unit. And a switching control means for switching between permission and prohibition of the system setting data protection circuit. 2. A system setting data protection circuit according to claim 1, wherein said determination means determines the output of said state storage means at the time of power-on or hardware reset, and said determination means permits writing to said semiconductor memory unit. And a warning notifying means for notifying a warning when it is determined that the setting has been performed.