JPH1116881A - Micromachining, manufacture of electronic element, capacitor and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for micromachining wherein the minimum machining dimension does not depend on machining technologies such as photolithography and dry etching. SOLUTION: A first insulating film 2 is formed on a substrate, and recesses are formed in the insulating film 2 by a photolitho dry etching method. A second insulating film 3 is formed on the insulating film 2, and the insulating film 3 is then removed so as to expose planes where the second insulating film 3 is buried in the recesses of the first insulating film 2. Micro-grooves 5 are formed by immersing the exposed planes in an etching liquid.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fine processing method for forming a fine groove in a plane parallel or perpendicular to a substrate surface of an insulating film, and an electronic device using this method for forming fine electrodes or wirings. And a capacitor having a large effective area per unit plane and a method for manufacturing the same.

[0002]

2. Description of the Related Art As is well known, as the performance and density of electronic elements represented by LSIs increase, the processing dimensions in the fine processing technology are steadily miniaturized.

A typical technique of the conventional fine processing technique is to form a fine resist pattern on a thin film to be processed to be an electrode or a wiring by photolithography, and then form the fine electrode and the wiring by etching. It was to do. However, due to the recent demand for further miniaturization, the following technology has been developed.

The first is miniaturization of a resist pattern formed by photolithography.
Development of new photoresist materials, shortening of the wavelength of light used for exposure, and recently, instead of light, X
The use of wires or electron beams has been practiced. The second is the development of an etching technique, and since the beginning of wet etching, dry etching has become the mainstream. In this etching technique, it is important how to faithfully transfer a resist pattern formed by photolithography to a thin film to be processed.

As is well known, the area occupied by a memory cell has been reduced with each generation due to the increase in the capacity of the DRAM and the advance of microfabrication technology. Miniaturization is most important. The memory cell must ensure a substantially constant amount of accumulated charge due to the problems of α-ray soft error and signal S / N ratio.

For this reason, a three-dimensional cell structure has been used, or a silicon nitride film having a higher dielectric constant than a silicon oxide film has been used as a capacitor insulating film. Examples of the three-dimensional cell structure include a trench cell and a stack cell.

Further, by miniaturizing a semiconductor or metal to the order of nanometers, a high-performance and high-density electronic element (quantum effect element) using a quantum effect, for example, a single-electron transistor can be manufactured.

[0008]

However, in the technology for responding to the demand for further miniaturization as described above, each step of micromachining becomes very complicated and the equipment to be used becomes very expensive. ing. In addition, every time miniaturization progresses, in the photolithography process, a change or improvement of a light source, an exposure apparatus, a resist, and the like used for exposure becomes essential. Even in the dry etching process, it is necessary to change and improve the etching gas and the apparatus.

Since the minimum processing size in the conventional fine processing depends on the minimum processing size of a resist by photolithography, processing smaller than the processing size possible with an existing exposure apparatus is practically impossible.

In the conventional microfabrication technology, electrodes and wires are formed on a surface parallel to the substrate surface, but it is very difficult to form electrodes and wires on a surface perpendicular to the substrate surface.
Furthermore, in the method of increasing the effective area per unit plane of the capacitor by making the cell structure three-dimensional, a further increase in the effective area is required, but in the conventional method, the structure becomes complicated and the manufacturing process becomes complicated. There is a problem that it becomes very complicated.

The present invention has been made in view of such problems of the prior art, and a fine processing method whose minimum processing size does not depend on the processing techniques of photolithography and dry etching, and an electronic device using the same. It is another object of the present invention to provide a method of manufacturing a capacitor, and a capacitor which has a large effective area per unit plane and can be easily manufactured.

[0012]

According to a first aspect of the present invention, a resist pattern is formed on a substrate by photolithography after laminating a plurality of insulating films on the substrate. Then, after exposing the surface of the laminated insulating film perpendicular to the substrate surface by dry etching using the resist pattern as a mask, the exposed surface is immersed in an etching solution to make the surface of the insulating film perpendicular to the substrate surface. Provided is a fine processing method characterized by forming a fine groove.

According to this method, the interface between the laminated insulating films is selectively etched by immersing the exposed surface in the etching solution, and a groove having a V-shaped cross section is formed at the interface. You. Further, the width and depth of the groove to be formed are controlled by wet etching conditions such as the concentration of the etchant used and the immersion time in the etchant. Therefore, the minimum processing size of the groove by this method does not depend on the processing technology of photolithography and dry etching. Further, the width and depth of the groove can be made smaller than the minimum dimension of the resist by the conventional photolithography.

In this method, it is preferable that each step until the exposed surface is immersed in the etching solution is performed at a temperature of 500 ° C. or less. According to a second aspect of the present invention, after a first insulating film is formed on a substrate, a resist pattern is formed on the insulating film by photolithography, and the first insulating film is formed by dry etching using the resist pattern as a mask. After forming a concave portion on a surface parallel to the substrate surface of the first insulating film and forming a second insulating film on the insulating film, the surface of the first insulating film where the second insulating film is buried is exposed. A fine processing method characterized by forming a fine groove on a surface of the insulating film parallel to the substrate surface by removing the insulating film and immersing the exposed surface in an etching solution as described above.

In this method, the insulating film may be removed by dry etching or by a chemical mechanical polishing method (a polishing method using an alkaline suspension containing fine particles such as silica). .

According to this method, the interface between the first insulating film and the second insulating film on the exposed surface is selectively etched by immersing the exposed surface in the etching solution. Are formed in a V-shaped groove. Further, the width and depth of the groove to be formed are controlled by wet etching conditions such as the concentration of the etchant used and the immersion time in the etchant. Therefore, the minimum processing size of the groove by this method does not depend on the processing technology of photolithography and dry etching. Also, the width and depth of the groove can be made smaller than the minimum dimension of a conventional photolithographic resist.

In this method, it is preferable that each step until the exposed surface is immersed in the etching solution is performed at a temperature of 600 ° C. or less. According to a third aspect of the present invention, a fine groove having a V-shaped cross section is formed in the insulating film by the fine processing method according to the first or second aspect, and at least the groove is formed on the surface of the insulating film having the groove. And (c) depositing an electronic element forming material (semiconductor or metal) so as to fill the groove, and then exposing a surface in which the electronic element forming material is embedded in the groove.

In this method, as a method of depositing an electronic element forming material (semiconductor or metal) so that at least the groove is filled in a surface of the insulating film having the groove, for example, if the electronic element forming material is silicon, And deposition of a silicon film by a CVD method using silane gas as a raw material. When the electronic element forming material is aluminum, first, a titanium nitride film is deposited as a close contact layer by sputtering on the surface of the insulating film having the grooves so that the grooves are not filled, and then the aluminum film is formed by sputtering. For example.

In this method, in order to expose the surface in which the electronic element forming material is buried in the groove, it is necessary to remove the deposited electronic element forming material at least to the position of the opening end of the groove. For example, a dry etching method or a chemical mechanical polishing method may be used.

According to this method, as described above, a fine groove having a V-shaped cross section is formed in the surface of the insulating film, and the V-shaped groove is filled with the material for forming an electronic element. , Selecting the exposed surface in the depth direction of the groove (ie,
By controlling the removal amount of the electronic element forming material)
It is possible to control the processing size (for example, the cross-sectional area of the electrode and the width of the wiring) of the electronic element formed of the material, and to significantly reduce the size by making the vicinity of the bottom of the groove an exposed surface. Can be. That is, the processing dimensions of the electronic element by this method do not depend on the processing techniques of photolithography and dry etching.

In this method, when a fine groove is formed by the fine processing method according to the first aspect, an electronic element is formed on a surface of the insulating film perpendicular to the substrate, and a pitch of the formed electronic element is equal to that of the laminated insulating film. Depends on film thickness.

In the case where a fine groove is formed by the fine processing method according to the second aspect, an electronic element is formed on a surface of the insulating film parallel to the substrate, and the pitch at which the electronic element is formed is equal to that of the first insulating film. It depends on the width of the concave portion to be formed and the pitch of the concave portion.
In this case, since two grooves are formed for each concave portion, by arranging a large number of grooves in parallel,
Compared with the conventional method using photolithography and dry etching, the formation pitch of wirings and electrodes can be reduced to half.

According to a fourth aspect of the present invention, the surface of the insulating film serving as a base is formed in an irregular shape perpendicular to the substrate surface, and the capacitor forming electrode layer, the capacitor forming insulating film, and the capacitor forming electrode are formed along the uneven surface. A capacitor is provided, wherein the layers are stacked in this order.

In this capacitor, the surface of the insulating film, which is the base, perpendicular to the substrate surface is uneven and the surface area of the insulating film is large, so that the effective area per unit plane is large.
This capacitor can be manufactured, for example, using the method of claim 5.

According to a fifth aspect of the present invention, a fine groove is formed on a surface of an insulating film serving as a base perpendicular to the substrate surface by the fine processing method according to the first aspect, and a capacitance forming electrode is formed along the groove surface. A method of manufacturing a capacitor, comprising: depositing a layer, a capacitor forming insulating film, and a capacitor forming electrode layer in this order.

According to this method, the formation of the groove increases the surface area of the surface of the underlying insulating film perpendicular to the substrate surface, so that the capacitance forming area per unit plane increases. In addition, since the formation area can be easily increased by increasing the number of stacked insulating films serving as bases, the effective area per unit plane of the capacitor can be easily increased.

[0027]

Embodiments of the present invention will be described below with reference to the drawings. A first embodiment of the present invention will be described with reference to FIGS.

In this embodiment, first, the silicon substrate 1
A 900 nm silicon oxide film (first insulating film) 2 is deposited thereon by plasma CVD using TEOS (Tetraethylorthosilicate) as a source gas. A resist is applied thereon, a resist pattern is formed by photolithography, dry etching is performed using the resist pattern as a mask, and then the resist pattern is removed. Thus, a recess 21 is formed on a surface of the silicon oxide film 2 parallel to the substrate surface. FIG. 1 shows this state.

Here, the width W ₁ of the concave portion 21 and the distance W ₂ between the adjacent concave portions 21 (the width of the convex portion 22) are both 0.6 μm.
m, the depth of the recess 21 was set to 0.8 μm. The light source of the exposure apparatus used for photolithography was i-line, and the light source was 0.6 μm
Is the minimum processing size.

Next, a 900 nm thick silicon oxide film (second insulating film) was deposited on the silicon oxide film 2 by plasma CVD. Thereby, the recess 21 of the silicon oxide film 2 is filled with the silicon oxide film 3 and the recess 2 is formed.
The silicon oxide film 3 was formed up to the upper end of the opening 1.
FIG. 2 shows this state.

By performing chemical mechanical polishing in this state, the silicon oxide films 2 and 3 were removed and the surface was flattened. The removed thickness of the silicon oxide films 2 and 3 was 1 μm in total at the thickest position of the silicon oxide film 2 (the position of the projection 22 in plan view) and the silicon oxide film 3 and the silicon oxide film 2. Thus, the surface 4 in which the silicon oxide film 3 is buried in the concave portion 21 of the silicon oxide film 2 was exposed. FIG. 3 shows this state.

The chemical mechanical polishing is performed with an average particle diameter of 30 nm.
Using an alkaline suspension containing abrasive particles having an average particle diameter of 150 nm by aggregating the silica fine particles, a polyurethane hard pad on the surface layer, and a two-layer structure pad having a soft pad on the underlayer as a polishing cloth, Surface pressure 5 psi (po
und per square inch) for 6 minutes.

Next, the interface 41 between the silicon oxide film 2 and the silicon oxide film 3 is selectively etched by immersing the silicon substrate 1 in an etchant (a mixed aqueous solution of hydrogen fluoride and ammonium fluoride). did. Thereby, as shown in FIG. 4, a groove 5 having a V-shaped cross section was formed at the interface 41. Here, the concentration of hydrogen fluoride in the etching solution is 2.5%, the concentration of ammonium fluoride is 38%,
By setting the temperature to 25 ° C. and the immersion time to 4 minutes, the upper surfaces of the silicon oxide films 2 and 3 are etched by 0.3 μm, the depth of the groove 5 is 0.5 μm, and the groove width at the opening end is 0.3 μm.
μm.

Next, a polycrystalline silicon film 6 is deposited on the silicon oxide films 2 and 3 having the grooves 5 by CVD. Thus, the trench 5 is filled with the polycrystalline silicon 61,
A polycrystalline silicon film 6 having a thickness of 0.3 μm was formed on silicon oxide films 2 and 3. FIG. 5 shows this state.

Next, the surface was removed by performing chemical mechanical polishing under the same conditions as described above, exposing the surface 7 in which the polycrystalline silicon 61 was embedded in the groove 5. This state is shown in FIG.
Shown in

Here, the polishing removes not only the polycrystalline silicon film 6 but also the upper surfaces of the silicon oxide films 2 and 3 which are boundaries with the polycrystalline silicon film 6 by 0.15 μm.
The polycrystalline silicon 61 in the groove 5 had a depth of 0.35 μm and a width of 0.2 μm. As a result, a fine polycrystalline silicon fine line (electronic element) having a width of 0.2 μm was formed on a plane parallel to the substrate surface. That is, according to the method of the present embodiment, processing with a size smaller than 0.6 μm, which is the minimum processing size of the exposure apparatus used for photolithography, was performed.

A second embodiment of the present invention will be described with reference to FIGS. In this embodiment, first, an electrode 8 of a transistor is formed on a silicon substrate 1. A silicon oxide film 9 having a thickness of 400 n was formed thereon by atmospheric pressure CVD.
m, and then heat-treated at 850 ° C. On this silicon oxide film 9, TEOS (Tetraethylorthosilic
Using ate) as a source gas, a silicon oxide film 10 is deposited to a thickness of 300 nm by plasma CVD, left in the air for 30 minutes, and then a silicon oxide film 11 is deposited to a thickness of 300 nm again by plasma CVD. After leaving the silicon oxide film 11 in the air similarly, the silicon oxide film 12 is again formed by plasma CVD to a thickness of 300 nm.
To be deposited. FIG. 7 shows this state. These silicon oxide films 10 to 12 correspond to the laminated insulating film of the present invention.

Next, a resist is applied on the silicon oxide film 12, and a resist pattern having a circle having a diameter substantially equal to the width of the electrode 8 above the electrode 8 is formed by photolithography. After performing dry etching on the silicon oxide films 10 to 12 using this resist pattern as a mask, the resist pattern is removed. Thereby, the silicon oxide films 10 to 12 are formed in a columnar shape.

A resist is applied again on the silicon oxide film 12, and a resist pattern having a circular opening smaller in diameter than the above-mentioned circle is formed on the center of the electrode 8 by photolithography. After performing dry etching on the silicon oxide films 9 to 12 using this resist pattern as a mask, the resist pattern is removed. As a result, circular holes 13 reaching the electrodes 8 are formed in the silicon oxide films 9 to 12. FIG. 8 shows this state.

That is, by this two-step patterning, as shown in FIG. 8, a cylindrical laminated insulating film is formed on the silicon oxide film 9, and its outer peripheral surface 14 and inner peripheral surface 15 are formed of the laminated insulating film. It is exposed as a surface perpendicular to the substrate surface.

Next, the silicon substrate 1 is immersed in an etchant (a mixed aqueous solution of hydrogen fluoride and ammonium fluoride) to form an outer peripheral surface 14 of a cylindrical laminated insulating film (silicon oxide films 10 to 12). And the interface 16 between the adjacent insulating films and the silicon oxide film 12 on the inner peripheral surface 15.
Corner 17 is selectively etched. This allows
As shown in FIG. 9, the outer peripheral surface 14 and the inner peripheral surface 15 of the cylindrical laminated insulating film are formed in a V-shaped cross section.

Here, the hydrogen fluoride concentration of the etching solution is 2.5%, the ammonium fluoride concentration is 38%, the temperature is 25 ° C., and the immersion time is 4 minutes, so that the outer peripheral surface 1
4 and the inner peripheral surface 15, the depth of the unevenness (dimension a in FIG. 9) is 0.5 μm, and the groove width at the open end (FIG. 9).
Is 0.3 μm.

In this state, the exposed surfaces on the substrate (the outer peripheral surface 14 and the inner peripheral surface 15 having an uneven shape, the inner peripheral surface 9A and the upper surface 9B of the silicon oxide film 9, the upper surface 12A of the silicon oxide film 12, the upper surface of the electrode 8 8A), a polycrystalline silicon film is deposited by CVD to form the lower capacitor forming electrode layer 18.
To form

Next, the capacitance forming electrode layer 18 made of polycrystalline silicon is subjected to a heat treatment in oxygen to form a silicon oxide film on its surface, and then a silicon nitride film is deposited by CVD. Is again heat-treated in oxygen to form an oxide film on the surface of the silicon nitride film, thereby forming a capacitance forming insulating film 19 on the entire upper surface of the capacitance forming electrode layer 18. Next, an upper capacitor forming electrode layer 20 is formed on the entire upper surface of the capacitor forming insulating film 19 by depositing polycrystalline silicon on the capacitor forming insulating film 19 by CVD.

In this manner, a capacitor having the shape shown in FIG. 10 is formed on the silicon substrate 1. Since this capacitor is also formed on the uneven surface perpendicular to the substrate surface of the underlying insulating film, the effective area per unit plane is large.

In this embodiment, a cylindrical laminated insulating film is formed on the silicon oxide film 9 and its outer peripheral surface 1 is formed.
4 and the inner peripheral surface 15 are both formed in an uneven shape, and the capacitance is formed along the uneven surface. However, the case where only one of the outer peripheral surface 14 and the inner peripheral surface 15 is uneven is also included in the present invention. Is included. In FIG. 10, when the silicon oxide film 9 is used as a plurality of laminated insulating films and the inner peripheral surface 9A is formed in an uneven shape, and the capacitance is formed along the uneven surface, the effective area per unit plane is further increased. Can be bigger.

[0047]

As described above, claims 1 and 2
According to the microfabrication method, since the minimum processing size of the groove does not depend on the processing technology of photolithography and dry etching, it is possible to easily form a groove having a size equal to or smaller than the minimum processing size that can be achieved by the conventional fine processing.

In particular, according to the method of the first aspect, it is possible to easily form a fine groove in a plane perpendicular to the substrate surface, which is difficult in the conventional fine processing. According to the method of manufacturing an electronic device according to the third aspect, an electrode or a wiring which is smaller than the minimum processing size possible by the conventional fine processing and which is extremely fine can be easily formed. Can be manufactured.

According to the capacitor of the fourth aspect, the effective area per unit plane increases. According to the manufacturing method of the fifth aspect, a capacitor having a large effective area per unit plane can be easily manufactured.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view showing a state where a concave portion is formed in a first insulating film in a first embodiment of the present invention.

FIG. 2 is a longitudinal sectional view showing a state where a second insulating film is formed in the first embodiment of the present invention.

FIG. 3 is a longitudinal sectional view showing a state in which a surface of a first insulating film in which a second insulating film is buried is exposed, in the first embodiment;

FIG. 4 is a longitudinal sectional view showing a state in which a groove is formed at an interface between a first insulating film and a second insulating film in the first embodiment of the present invention.

FIG. 5 is a longitudinal sectional view showing a state in which a polycrystalline silicon film is formed on an insulating film surface having a groove in the first embodiment of the present invention.

FIG. 6 is a longitudinal sectional view showing a state in which a surface in which polycrystalline silicon is buried in a groove is exposed in the first embodiment of the present invention.

FIG. 7 is a longitudinal sectional view showing a state in which a plurality of insulating films are stacked on a substrate in a second embodiment of the present invention.

FIG. 8 is a longitudinal sectional view showing a state in which a surface of a laminated insulating film perpendicular to a substrate surface is exposed in a second embodiment of the present invention.

FIG. 9 is a longitudinal sectional view showing a state in which a surface perpendicular to a substrate surface of a laminated insulating film is formed in an uneven shape in a second embodiment of the present invention.

FIG. 10 is a longitudinal sectional view showing a capacitor manufactured in a second embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 silicon substrate 2 silicon oxide film (first insulating film) 21 concave portion 3 silicon oxide film (second insulating film) 4 exposed surface 41 interface 5 groove 6 polycrystalline silicon film (electronic element forming material) 61 polycrystalline silicon fine wire (Electronic element) 7 Surface in which polycrystalline silicon is buried in groove 8 Transistor electrode 9 Silicon oxide film 10 Silicon oxide film 11 Silicon oxide film 12 Silicon oxide film 14 Outer peripheral surface (surface perpendicular to substrate surface of laminated insulating film) 15 inner peripheral surface (surface perpendicular to the substrate surface of the laminated insulating film) 16 interface 18 capacitance forming electrode layer 19 capacitance forming insulating film 20 capacitance forming electrode layer

Claims (5)

[Claims] After laminating a plurality of insulating films on a substrate, a resist pattern is formed on the insulating film by photolithography, and dry etching using the resist pattern as a mask is perpendicular to the substrate surface of the laminated insulating film. A fine groove is formed in a surface of the insulating film perpendicular to the substrate surface by immersing the exposed surface in an etching solution after exposing the exposed surface. 2. After forming a first insulating film on a substrate, a resist pattern is formed on the insulating film by photolithography, and the resist pattern is used as a mask to dry-etch the substrate surface of the first insulating film. Is formed on a surface parallel to the first insulating film, a second insulating film is formed on the insulating film, and the insulating film is so formed that the surface of the first insulating film in which the second insulating film is buried is exposed. A fine processing method characterized by forming a fine groove in a surface of an insulating film parallel to a substrate surface by removing the film and immersing the exposed surface in an etching solution. 3. A micro-fabrication method according to claim 1 or 2, wherein a fine groove having a V-shaped cross section is formed in the insulating film, and at least the groove is filled in the surface of the insulating film having the groove. A method for manufacturing an electronic element, comprising: depositing an electronic element forming material on a surface of a substrate, and exposing a surface in which the electronic element forming material is embedded in the groove. 4. A surface of an insulating film serving as a base, which is perpendicular to the substrate surface, is formed in an uneven shape, and a capacitor forming electrode layer, a capacitor forming insulating film, and a capacitor forming electrode layer are laminated in this order along the uneven surface. A capacitor characterized in that: 5. A fine groove is formed on a surface of a base insulating film perpendicular to a substrate surface by the fine processing method according to claim 1, and a capacitor forming electrode layer and a capacitor forming insulating film are formed along the groove surface. And a capacitor forming electrode layer are deposited in this order.