JPH11168521A - Orthogonal modulation wave receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily operate a conversion frequency for orthogonal detection at an optional frequency and to realize miniaturization of the receiver at a low cost. SOLUTION: A signal obtained by converting a reception signal into an intermediate frequency band signal at an analog section 10 is sampled by an A/D converter 201, which converts the signal into a digital signal. The digital signal is orthogonally detected by multiplying an output signal of a numerical controlled oscillator 203 controlled by an automatic frequency control circuit 210 with the digital signal at multipliers 202A, 202B of a digital orthogonal detection section 202. harmonics of the detected signal are eliminated at low pass filters 204, 205 and re-timing is taken at a sampling rate being an integer multiple of a symbol rate by a re-sampling circuit 206 controlled by a clock phase signal from a synchronization detection demodulator 209. The re-timing signal is subject to spectral shaping at reception filters 207, 208, demodulated at a synchronization detection demodulator 209, from which demodulation data are outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a quadrature modulated wave receiving apparatus used for digital radio communication, and more particularly, to sampling a received signal after being converted to an intermediate frequency band, so that the sampled digital signal can be subjected to quadrature detection by digital signal processing. Related to a quadrature modulated wave receiving apparatus.

[0002]

2. Description of the Related Art As a conventional quadrature modulated wave receiving apparatus, a technique disclosed in Japanese Patent Application Laid-Open No. 9-83596 is known. Hereinafter, a conventional quadrature modulated wave receiving apparatus will be described with reference to FIG. FIG. 4 is a block diagram showing a configuration of a conventional quadrature modulated wave receiving apparatus. In the figure, a quadrature modulated wave receiver converts an analog signal into an intermediate frequency band and an quasi-synchronous detection of the intermediate frequency band.
And a digital unit 50 that converts the quasi-synchronously detected in-phase component and quadrature-component baseband signals into digital signals, performs synchronous detection, and demodulates the received signal.
The analog unit 40 includes a first frequency converter 401, a synthesizer 402, a band-pass filter (BPF) 403, a second
Frequency converter 404, local oscillator 405, band pass filter (BPF) 406, analog quasi-synchronous detector 407,
Local oscillator 408, low-pass filter (LPF) 409
And 410.

A first frequency converter 401 frequency-converts a modulated received signal (baseband signal) into a signal of a first intermediate frequency band by a signal corresponding to a radio frequency (carrier frequency) oscillated from a synthesizer 402. It has become. The BPF 403 limits the band of the first intermediate frequency converted to the first intermediate frequency to reduce out-of-band noise. The second frequency converter 404 includes a BPF 403
Is converted into a signal of the second intermediate frequency band by the intermediate frequency signal oscillated from the local oscillator 405. The BPF 406 limits the band of the second intermediate frequency converted to the second intermediate frequency, and reduces out-of-band noise. The analog quasi-synchronous detector 407 performs quadrature detection on the signal of the second intermediate frequency band that has passed through the BPF 406 at a fixed frequency oscillated from the local oscillator 408, thereby extracting baseband signals of an in-phase component and a quadrature component. The baseband signals of the in-phase component and the quadrature component detected by the quasi-synchronous detector 407 are output to the digital unit 50 after the harmonic components are removed by the LPFs 409 and 410, respectively.

The digital section 50 includes an A / D converter 50
1, 502, AFC complex multiplier 503, sine / cosine data converter 504, numerically controlled oscillator 505, automatic frequency control circuit (AFC) 506, reception filter (RX)
FIL) 507, 508 and synchronous detection demodulator 509
It has.

[0005] A / D converters 501 and 502 sample the baseband signals of the in-phase component and the quadrature component that have passed through the LPFs 409 and 410 of the analog section 40, convert the baseband signals into digital signals, and output the digital signals to the AFC complex multiplier 503.
The AFC complex multiplier 503 includes A / D converters 501 and 5
02 is multiplied by a sine value or a cosine value output from the sine / cosine data converter 504 with the digital signal of the in-phase component and the quadrature component output from the sine / cosine data converter 504. The reception filters (RX FILs) 507 and 508 shape the spectrum so as to prevent intersymbol interference in digital transmission of a signal output from the AFC complex multiplier 503. Then, the signal whose spectrum has been shaped by the reception filters (RX FIL) 507 and 508 is input to the synchronous detection and demodulation circuit 509. Synchronous detection demodulation circuit 509
Then, frequency error information for performing carrier recovery is extracted from the spectrum-shaped signal, the received signal is demodulated, and demodulated data is output. At the same time, by outputting the frequency error information obtained from the synchronous detection and demodulation circuit 509 to the automatic frequency control (AFC) circuit 506, the automatic frequency control circuit 506 uses the numerical control oscillator (NCO) 11 based on the frequency error information. , And outputs the oscillation frequency to the sine / cosine data converter 504 to generate a reference carrier.

[0006]

In the conventional quadrature modulated wave receiving apparatus as described above, quadrature detection is performed by the analog quasi-synchronous detector 407 in the intermediate frequency band, and sampling is performed by the A / D converters 501 and 502. Since the digital signal is converted into a digital signal and then synchronously detected by the digital section 50, it is necessary to finely adjust the phase and amplitude of the in-phase component signal and the quadrature component signal output from the analog quasi-synchronous detector. However, since the oscillation frequency of the local oscillator used for detection by the analog quasi-synchronous detector is fixed, it is difficult to arbitrarily set the conversion frequency.

An object of the present invention is to convert a received signal into an intermediate frequency band, convert the signal into a digital signal, convert the signal into a digital signal, and perform quadrature detection in this digital signal processing. It is an object of the present invention to provide a quadrature modulated wave receiving apparatus which can easily operate at a frequency and can realize low cost and small size of the apparatus.

[0008]

In order to achieve the above object, a quadrature modulated wave receiving apparatus according to the present invention comprises a frequency converting means for converting a received signal into an intermediate frequency band signal, and an intermediate frequency converted by the frequency converting means. A / D conversion means for sampling a frequency band signal and converting it into a digital signal;
Digital quadrature detection means for multiplying a digital signal converted by the / D conversion means by a reference carrier signal and quadrature detection by digital signal processing to extract baseband signals of an in-phase component and a quadrature component; and the digital quadrature detection means A low-pass filter for removing harmonic components of the baseband signal of the in-phase component and the quadrature component detected by the quadrature detection, and an output signal passing through the low-pass filter at a sampling rate that is an integral multiple of the symbol rate. It comprises a resampling circuit for timing, and demodulating means for demodulating the spectrum of the output signal retimed by the resampling circuit and then outputting demodulated data.

In the present invention, the A / D conversion means samples the received signal in the intermediate frequency band, converts it into a digital signal, multiplies this digital signal by a reference carrier signal, and performs quadrature detection by digital signal processing. Therefore, the conversion frequency in the quadrature detection can be easily operated at an arbitrary frequency, and the cost and size of the device can be reduced.

[0010]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram of a quadrature modulated wave receiving apparatus according to a first embodiment of the present invention. In FIG. 1, a quadrature modulated wave receiving apparatus is roughly divided into an analog section 10 for converting a received signal into an intermediate frequency band, and an intermediate frequency band signal frequency-converted by the analog section 10 into a digital signal. A digital section 20 for orthogonally detecting and resampling the digital signal and demodulating the received signal by synchronous detection.

The analog section 10 includes a first frequency converter 101, a synthesizer 102, a band-pass filter (BP)
F) 103, second frequency converter 104, local oscillator 10
5. A band pass filter (BPF) 106 is provided.
The first frequency converter 101 receives the modulated reception signal (RF
The signal is converted into a signal in the first intermediate frequency band by a signal corresponding to a radio frequency (carrier frequency) oscillated from the synthesizer 102. BPF10
Numeral 3 is for limiting the band of the first intermediate frequency converted to the first intermediate frequency to reduce out-of-band noise. The second frequency converter 104 converts the first intermediate frequency signal that has passed through the BPF 103 into a second intermediate frequency band signal using an intermediate frequency signal oscillated from the local oscillator 105. The BPF 106 limits the band of the second intermediate frequency converted to the second intermediate frequency, and reduces out-of-band noise.

The digital section 20 includes an A / D converter 2
01, digital quadrature detector 202, numerically controlled oscillator 2
03, low-pass filters (LPF) 204 and 205,
The resampling circuit 206 and the reception filter (RX FI)
L) 207 and 208, a synchronous detection demodulator 209, an automatic frequency control circuit (AFC) 210, and a resampling control circuit 211.

The A / D converter 201 samples the second intermediate frequency band signal that has passed through the BPF 106 of the analog section 10 and converts it into a digital signal. The converted second intermediate frequency band signal is a digital signal. Output to quadrature detector 202. Digital quadrature detector 20
2 is a first multiplier 202A, a second multiplier 202B, and π
The second intermediate frequency band signal converted into a digital signal by the A / D converter 201 is divided into two and output to the first multiplier 202A and the second multiplier 202B. The first multiplier 202A multiplies the second intermediate frequency band signal sampled by the A / D converter 7 by the π / 2 phase shifter 202C of the oscillation signal of the numerically controlled oscillator 203 by the π / 2 phase shifter 202C. The second multiplier 202B multiplies the second intermediate frequency band signal sampled by the A / D converter 7 by the oscillation signal of the numerically controlled oscillator 203. To detect the baseband signal of the in-phase component. Also, π / 2
The phase shifter 202C shifts the phase of the oscillation signal of the numerically controlled oscillator 203 by π / 2 and outputs it to the first multiplier 202A.

The low-pass filter (LPF) 204 removes a harmonic component from the baseband signal of the quadrature component output from the first multiplier 202A, and the low-pass filter (LPF) 205 It removes harmonic components from the in-phase component baseband signal output from the square multiplier 202B. The resampling circuit 206
Based on the clock phase error information from the synchronous detection demodulator 209, the output signals of the low-pass filters (LPF) 204 and 205 are sampled at an integer multiple of the symbol rate.
Retiming at a rate. The receive filters (RX FIL) 207 and 208 shape the spectrum of the output signal retimed by the resampling circuit 206 so as to prevent intersymbol interference in digital transmission. The synchronous detector / demodulator 209 reproduces a carrier from the output signals of the reception filters 207 and 208, performs synchronous demodulation of the received signal, and detects frequency error information and clock phase information. The detected frequency error information is output to an automatic frequency control circuit (AFC) 210, and the clock phase information is output to a resampling control circuit 211 of a resampling circuit 206. The automatic frequency control circuit (AFC) 210 controls the oscillation frequency of the numerically controlled oscillator 203 based on the frequency error information. The resampling control circuit 211 corrects the resampling timing of the resampling circuit 206 based on the clock phase information.

Next, the operation of the present embodiment configured as described above will be described. The orthogonally modulated received signal is frequency-converted by a frequency converter 101 into a signal of a first intermediate frequency band.
After the band is limited by the signal 103, the frequency is converted into a signal of the second intermediate frequency band by the frequency converter 104, and the BP
The band is limited by F106, output to the A / D converter 201, sampled, and converted into a digital signal. Here, the center frequency of the second intermediate frequency band signal output from the second frequency converter 104 is f1, and the sampling frequency of the A / D converter 201 is f2. However, the sampling frequency f2 of the A / D converter 201 is
In order to satisfy Nyquist's theorem, it is assumed to be larger than twice the bandwidth B of the second intermediate frequency band signal. 2A shows the frequency spectrum of the second frequency converter 104 band-limited by the BPF 106, FIG. 2B shows the frequency spectrum of the output of the A / D converter 201,
(C) shows the frequency spectrum of the output of the LPFs 204 and 205.

As shown in FIG. 2, the A / D converter 20
A component of the center frequency f1-f2 appears in the digital signal sampled at 1. At this time, assuming that the oscillation frequency of the numerically controlled oscillator 203 is f1-f2, the sampled value sequence subjected to the A / D conversion is subjected to the oscillation frequencies f1-f2 and f1 by the first multiplier 202A and the second multiplier 202B.
By multiplying the oscillation signal obtained by shifting the phase of −f2 by π / 2, it is possible to detect an in-phase component and a quadrature component baseband signal.
However, the sampling frequency f2 of the A / D converter 201
Must be selected such that the aliasing component in the sampling is not superimposed on the desired wave component. Where 2 ×
Assuming that f2> f1, FIG. 2 shows that 2 × f2-f1-B>
The condition f1−f2 or 2 × f2−f1 + B <f1−f2 is derived. Therefore, f2 must satisfy the following conditions. f2> 2/3 × f1 + ／ × B
Alternatively, f2 <2/3 × f1-1 / 3 × B.

The first multiplier 202A and the second multiplier 202
The baseband signal detected by B as an in-phase component and a quadrature component is subjected to re-sampling at an integral multiple of the symbol rate by a resampling circuit 206 after harmonic components are removed by LPFs 204 and 205. Generally, in the synchronous detection demodulator 209,
When performing clock phase detection, the resampling circuit 20
6 is oversampled at twice the symbol rate.

Therefore, the synchronous detection demodulator 209 performs demodulation not only at the signal point but also at the zero cross point which is an intermediate point between the signal points, and determines the delay or advance of the phase from the optimum sampling point. This is output to the resampling control circuit 211 as clock phase information. In the resampling control circuit 211, the synchronous detection demodulator 20
The delay or advance of the clock phase is integrated on the basis of the clock phase information input from 9 and when the value exceeds a certain threshold, the resampling timing of the resampling circuit 206 is corrected. In such a case, A / D
If the sampling rate of the converter 201 is set to an integral multiple of the sampling rate at the retiming of the resampling circuit 206, the resampling circuit 206 may simply perform sampling data thinning. The timing of resampling can be corrected by a simple circuit by shifting the sampling data thinning interval back and forth by one sampling period of the A / D converter 201 in accordance with the delay or advance of the integrated phase.

The baseband signals of the in-phase component and the quadrature component retimed by the resampling circuit 206 are subjected to spectrum shaping by reception filters (RX FILs) 207 and 209 and input to the synchronous detection demodulation circuit 209. The synchronous detection and demodulation circuit 209 performs carrier wave recovery,
It demodulates the received signal and outputs demodulated data. At the same time, it outputs the frequency error information of the input signal of the synchronous detection and demodulation circuit 209 to the automatic frequency control circuit 210 and outputs the clock phase information to the resampling control circuit 211. The automatic frequency control circuit 210 controls the oscillation frequency of the numerically controlled oscillator 203 that outputs the conversion frequency to the digital quadrature detection unit 202 based on the frequency error information obtained from the synchronous detection and demodulation circuit 209.

According to the first embodiment as described above,
Since the digital signal after the signal converted into the intermediate frequency band is sampled by the A / D converter 201 and converted into the digital signal is subjected to quadrature detection by the digital quadrature detector 202, the conventional analog quasi-synchronous detector is used. As in the case where it is used, fine adjustment of the phase and amplitude between the in-phase component signal and the quadrature component signal of the output becomes unnecessary, the adjustment time and cost can be eliminated, and the digital quadrature detection unit is included. By realizing the digital signal processing unit by an integrated circuit, the number of components can be significantly reduced, and the cost and size of the quadrature modulated wave receiver can be easily reduced. Further, the conversion frequency in the quadrature detection unit can be easily operated at an arbitrary frequency by digital signal processing. Further, according to the first embodiment, by changing the conversion frequency supplied to the quadrature detection unit in combination with the automatic frequency control circuit, the conventionally existing AFC complex multiplier can be eliminated, Accordingly, the demodulation circuit can be simplified. In addition, when the quadrature detected in-phase and quadrature signals input to the synchronous detection demodulator are resampled by the resampling circuit, simple clock recovery is performed by controlling the resampling timing based on the clock phase information of the synchronous detection demodulator. A circuit can be provided.

Next, a second embodiment of the present invention will be described. FIG. 3 is a block diagram of a quadrature modulated wave receiving apparatus according to a second embodiment of the present invention. 1 is different from FIG. 1 in that the synchronous detection demodulator in FIG.
And a numerically controlled oscillator and an automatic frequency control circuit in FIG. 1 are constituted by a sine / cosine table ROM 213 and an address decoder 214 for decoding the read address. There.

Referring to FIG. 3, the same components as those in FIG. 1 will be denoted by the same reference numerals. The quadrature modulated wave receiving apparatus will be broadly divided into analog circuits as in FIG. It comprises a unit 10 and a digital unit 20. The analog section 10 has a configuration equivalent to that of the first embodiment. Therefore, the digital section 20 will be mainly described, and the other configuration will not be described. The digital unit 20
A / D converter 201, digital quadrature detector 202, low-pass filters (LPF) 204 and 205, resampling circuit 206, reception filter (RX FIL) 20
7 and 208, a PLL demodulator 212, a sine / cosine table ROM 213, an address decoder 214,
A resampling control circuit 211 is provided.

The A / D converter 201 samples the second intermediate frequency band signal passed through the BPF 106 of the analog section 10 and converts it into a digital signal. The second intermediate frequency band signal converted into the digital signal is converted into a digital signal. Output to quadrature detector 202. Digital quadrature detector 20
2 includes a first multiplier 202A and a second multiplier 202B, and a second intermediate frequency band signal converted into a digital signal by the A / D converter 201 is divided into two to form a first multiplier 202
A and the output to the second multiplier 202B. First multiplier 2
02A is the second intermediate frequency band signal sampled by the A / D converter 7 and the sine / cosine table ROM2.
And a baseband signal having an in-phase component by multiplying by the cosine value output from the second multiplier 13.
02B is the second intermediate frequency band signal sampled by the A / D converter 7 and the sine / cosine table ROM2.
13 is to detect a quadrature baseband signal by multiplying by a sine value output from the block 13.

The low-pass filter (LPF) 204 removes harmonic components from the in-phase component baseband signal output from the first multiplier 202A, and the low-pass filter (LPF) 205 This is to remove harmonic components from the baseband signal of the quadrature component output from the doubler 202B. The resampling circuit 206
Based on the clock phase error information from the PLL demodulator 212, the output signals of the low-pass filters (LPFs) 204 and 205 are retimed at a sampling rate that is an integral multiple of the symbol rate. Receive filter (R
XFILs 207 and 208 spectrally shape the output signal retimed by the resampling circuit 206 so as to prevent intersymbol interference in digital transmission.

The PLL demodulator 212 includes a complex multiplier 212
A, phase detector 212B, loop filter 212C,
An address decoder 212D and a sine / cosine table ROM 212E are provided. The complex multiplier 212A is
The output signals of the reception filters (RX FILs) 207 and 208 are complex-multiplied by the output signals of the sine and cosine values read from the sine / cosine table ROM 212E to extract baseband signals of in-phase and quadrature components. , And its baseband signal is output to the phase detector 212B. Phase detector 212B
Detects the phase of the baseband signal output from the complex multiplier 212A, outputs demodulated data, and detects and outputs frequency error information and clock phase information of the baseband signal. The loop filter 212C smoothes the frequency error information of the baseband signal, converts it into a control value, and converts it into a control value.
14 is output. Address decoder 212
D determines the read address of the sine / cosine table ROM 212E based on the voltage as the frequency error information and the conversion cycle of the digital quadrature detector 202. Sine / cosine table ROM 212
E stores a large number of cosine and sine values corresponding to the frequency error information in a table, and outputs the cosine and sine values addressed by the address decoder 212D to the complex multiplier 212A.

Sine / cosine table ROM 213
Is a table for storing a large number of cosine values and sine values according to the frequency error information, and stores the cosine value and the sine value designated by the address decoder 214 in the first multiplier 20 of the digital quadrature detector 202.
2A and the second multiplier 202B. The address decoder 214 determines the read address of the sine / cosine table ROM 212E based on the smoothed control value as the frequency error information and the conversion cycle of the digital quadrature detector 202. The resampling control circuit 211 controls the sampling timing of the resampling circuit 206 based on the clock phase information output from the phase detector 212B.

The operation of the second embodiment configured as described above will be described. The received signal converted into an intermediate frequency band signal by the analog unit 10 is sampled by the A / D converter 201, converted into a digital signal, and output to the digital quadrature detection unit 202. Then, in the digital quadrature detector 202, the in-phase component and the quadrature component are multiplied by the first multiplier 202A and the second multiplier 202B by the cosine value and the sine value from the sine / cosine table ROM 213, respectively. It is detected. Sine / Cosine Table RO
The read address of M213 is the loop filter 212
The address decoder 214 calculates and specifies the output signal of C and the conversion cycle of the digital quadrature detector 202.
In the sine / cosine table ROM 213, when the number of samples in one sine cycle is 4 × M (M is an integer), and the read address of the sine value is ADsin, the read address of the cosine is designated as ADsin + M. In this case, the sine / cosine table RO
If a data table for 1 + 1/4 cycle is provided in M213, the processing in the address decoder 214 can be simplified.

First multiplier 202A and second multiplier 202
The baseband signal detected by B as an in-phase component and a quadrature component has its harmonic components removed by LPFs 204 and 205, and is retimed by a resampling circuit 206 at a sampling rate that is an integral multiple of the symbol rate.
Generally, when clock phase detection is performed by the phase detector 212B of the PLL demodulation unit 212, the symbol rate 2
Oversampled by a factor of two. Phase detector 212
In B, the phase is detected not only at the signal point but also at the zero crossing point, which is an intermediate point between the signal points, and the delay or advance of the phase from the optimal sampling point is determined, and resampling control is performed as clock phase information. Output to the circuit 211. The resampling control circuit 211 integrates the delay or advance of the clock phase based on the clock phase information input from the phase detector 212B, and if the value exceeds a certain threshold, the resampling timing is determined. to correct. In such a case, if the sampling rate of the A / D converter 201 is set to an integral multiple of the sampling rate in the resampling, the resampling circuit 206
Then, the sampling data may be simply decimated.
The resampling timing correction is realized by shifting the sampling data thinning interval forward or backward by one sampling cycle of the A / D converter 201 in accordance with the delay or advance of the integrated phase. The signal retimed by the re-sampling circuit 206 receives the signal from the reception filter (R
XFIL) 204 and 205 are spectrally shaped and input to PLL demodulation section 212. PLL demodulation unit 2
At 12, the phase of the output signal of the complex multiplier 212A is detected and demodulated, and at the same time, the clock phase information is output to the resampling control circuit 211 and the frequency error information of the received signal is output to the address decoder 31.

According to the second embodiment as described above,
The same effects as those of the first embodiment can be obtained. In addition, the numerically controlled oscillator and the automatic frequency control circuit are constituted by a sine / cosine table ROM and an address decoder for decoding a read address of the sine / cosine table ROM. The AFC complex multiplier and the numerically controlled oscillator that have been used can be eliminated.

[0030]

As described above, according to the present invention, a signal converted into an intermediate frequency band is sampled by A / D conversion means and converted into a digital signal, and the digital signal is subjected to quadrature detection by digital signal processing. With this configuration, fine adjustment of the phase and amplitude between the in-phase component signal and the quadrature component signal of the output as in the case of using the conventional analog quasi-synchronous detector becomes unnecessary, and the adjustment time and cost are reduced. By realizing the digital signal processing section including the digital quadrature detection means by an integrated circuit, the number of parts can be greatly reduced, and the cost and size of the quadrature modulated wave receiver can be reduced. Can be easily realized. Further, according to the present invention, the conversion frequency in the quadrature detector can be easily operated at an arbitrary frequency by digital signal processing. Further, according to the present invention, by changing the conversion frequency supplied to the quadrature detection unit in combination with the automatic frequency control circuit, the conventionally existing AFC complex multiplier can be eliminated. The demodulation circuit can be simplified. Further, according to the present invention, when the quadrature detected in-phase and quadrature signals input to the synchronous detection demodulator are resampled by the resampling circuit, a simple clock can be obtained by controlling the resampling timing based on the clock phase information. A reproduction circuit can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram of a quadrature modulated wave receiving apparatus according to a first embodiment of the present invention.

FIG. 2 is a frequency spectrum diagram of each part in the quadrature modulated wave receiving apparatus according to the first embodiment of the present invention.

FIG. 3 is a block diagram of a quadrature modulated wave receiving apparatus according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional quadrature modulated wave receiving apparatus.

[Explanation of symbols]

101: frequency converter, 102: synthesizer, 1
03, 106... Band-pass filter (BPF), 105
... local oscillator, 201 ... A / D converter, 202 ...
Digital quadrature detector, 202A first multiplier, 20
2B: second multiplier, 202C: π / 2 phase shifter, 20
3 Numerically controlled oscillator (NCO), 204, 205 ...
Low-pass limiting filter (LPF), 206: resampling circuit, 207, 208: reception filter (RX FI)
L), 209: synchronous detection demodulator, 210: automatic frequency control circuit (AFC), 211: resampling control circuit, 212: PLL demodulation unit, 212A: complex multiplier, 212B: phase detector , 212... Loop filter, 212D... Address decoder, 212E.
Sine / cosine table ROM, 213 ... Sine / cosine table ROM, 214 ... Address decoder.

Claims (7)

[Claims] A frequency conversion means for converting a received signal into an intermediate frequency band signal; an A / D conversion means for sampling the intermediate frequency band signal converted by the frequency conversion means and converting the signal into a digital signal; Digital quadrature detection means for multiplying the digital signal converted by the D conversion means by a reference carrier signal and quadrature detection by digital signal processing to extract baseband signals of in-phase and quadrature components; and the digital quadrature detection means A low-pass filter for removing harmonic components of the quadrature-detected in-phase component and the quadrature-component baseband signal, and symbolizing an output signal passed through the low-pass filter as a symbol
A resampling circuit for retiming at a sampling rate that is an integral multiple of a rate; demodulating means for demodulating and demodulating the output signal retimed by the resampling circuit after spectral shaping, and outputting demodulated data. apparatus. 2. The apparatus according to claim 1, wherein said demodulating means reproduces a carrier from the output signal after said spectrum shaping, performs synchronous demodulation of a received signal, and detects frequency error information and clock phase information. The quadrature modulated wave receiving device according to the above. 3. A numerically controlled oscillator for extracting a baseband signal of an in-phase component and a quadrature component by supplying a reference oscillation signal to the digital quadrature detection means, and based on frequency error information from the demodulation means. 3. The quadrature modulated wave receiving apparatus according to claim 1, further comprising an automatic frequency control circuit that controls an oscillation frequency of the numerically controlled oscillator. 4. The digital quadrature detection means comprises:
A first method for detecting a quadrature baseband signal by multiplying the intermediate frequency band signal sampled by the / D conversion means by a signal obtained by shifting the oscillation signal of the numerical control oscillator by π / 2.
2. A multi-function device comprising: a multiplier; and a second multiplier for multiplying an intermediate frequency band signal sampled by the A / D converter and an oscillation signal of the numerically controlled oscillator to detect a baseband signal having an in-phase component. 4. The quadrature modulated wave receiver according to 2 or 3. 5. The quadrature modulation wave receiving apparatus according to claim 1, further comprising a resampling control circuit that controls a sampling timing of the resampling circuit based on clock phase information from the demodulation unit. 6. A complex multiplier for extracting a baseband signal of an in-phase component and a quadrature component by complexly multiplying the output signal after the spectrum shaping by an output signal of a sine value and a cosine value, and A phase detector that detects the phase of the baseband signal output from the complex multiplier, outputs demodulated data, and detects and outputs frequency error information and clock phase information of the baseband signal;
A loop filter for smoothing the frequency error information, converting the control value into a control value, and outputting the control value; a sine / cosine table ROM for storing a large number of cosine values and sine values according to the frequency error information in a table; loop·
The sine / cosine table ROM based on a filter output signal and a conversion cycle of the digital quadrature detection means.
2. The quadrature modulated wave receiving apparatus according to claim 1, further comprising a PLL demodulator including an address decoder that designates a read address of the cosine value and the sine value of the PLL. 7. Frequency error information for extracting a baseband signal of an in-phase component and a quadrature component by multiplying a first multiplier and a second multiplier constituting the digital quadrature detection means by a cosine value and a sine value. And a sine / cosine table ROM for storing a large number of cosine values and sine values in a table in accordance with the above, and a cosine of the sine / cosine table ROM based on the frequency error information and the conversion cycle of the digital quadrature detection means. 3. The quadrature modulated wave receiving apparatus according to claim 1, further comprising an address decoder that specifies a read address of the value and the sine value.