JPH11168235A - Light emitting diode - Google Patents
Light emitting diodeInfo
- Publication number
- JPH11168235A JPH11168235A JP33539097A JP33539097A JPH11168235A JP H11168235 A JPH11168235 A JP H11168235A JP 33539097 A JP33539097 A JP 33539097A JP 33539097 A JP33539097 A JP 33539097A JP H11168235 A JPH11168235 A JP H11168235A
- Authority
- JP
- Japan
- Prior art keywords
- led chip
- substrate
- light emitting
- emitting diode
- electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/85—Packages
- H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls
Landscapes
- Led Device Packages (AREA)
- Led Devices (AREA)
Abstract
(57)【要約】
【課題】 同一面側に正負一対の電極を有するLEDチ
ップを基板の配線パターンに電気的に接続する一方で、
光の取り出し効率を向上する。
【解決手段】 同一面側に正負一対の電極を有するLE
Dチップ13をフリップチップボンディングによりバン
プ15を介して基板11の配線パターン12に電気的に
接続する。LEDチップ13の下面には反射層14を設
ける。LEDチップ13の下面側はアンダーフィル樹脂
16を充填する。LEDチップ13の光出射面側である
上面側に影となる電極が存在せず、発光面積が増大する
と共に、発光層からの下向きの光は反射層14に反射さ
れ、全体として光の取り出し効率が向上する。
[PROBLEMS] To electrically connect an LED chip having a pair of positive and negative electrodes on the same surface side to a wiring pattern of a substrate,
Improves light extraction efficiency. SOLUTION: LE having a pair of positive and negative electrodes on the same surface side
The D chip 13 is electrically connected to the wiring pattern 12 of the substrate 11 via the bump 15 by flip chip bonding. The reflection layer 14 is provided on the lower surface of the LED chip 13. The underside of the LED chip 13 is filled with an underfill resin 16. There is no electrode serving as a shadow on the upper surface side, which is the light emitting surface side of the LED chip 13, so that the light emitting area increases, and the downward light from the light emitting layer is reflected by the reflective layer 14, and the light extraction efficiency as a whole Is improved.
Description
【0001】[0001]
【発明の属する技術分野】本発明は、同一面側に正負一
対の電極を有する発光ダイオード(LED)チップを基
板に電気的に接続して形成される発光ダイオードに関す
るものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting diode (LED) formed by electrically connecting a light emitting diode (LED) chip having a pair of positive and negative electrodes on the same surface to a substrate.
【0002】[0002]
【従来の技術】従来のこの種の発光ダイオードとして、
例えば、特開平9−135040号公報に掲載の技術を
挙げることができる。図8は特開平9−135040号
公報に掲載のLEDを示す断面図である。2. Description of the Related Art As a conventional light emitting diode of this type,
For example, there is a technique described in Japanese Patent Application Laid-Open No. Hei 9-135040. FIG. 8 is a sectional view showing an LED disclosed in Japanese Patent Application Laid-Open No. 9-135040.
【0003】特開平9−135040号公報は、同一面
側に正負一対の電極を設けたLEDチップを開示してい
る。即ち、この発光ダイオードは、所定の配線パターン
2を設けた基板1に、Ag(銀)ペースト4を介してL
EDチップ3を接着している。また、LEDチップ3の
上面3a側の電極(図示略)を、Au(金)ワイヤ等の
ボンディングワイヤ5により基板1の配線パターン2に
結線して電気的に接続している。そして、エポキシ樹脂
等の樹脂モールド6によりLEDチップ3の周囲を封止
して、LEDチップ3を保護している。Japanese Patent Application Laid-Open No. Hei 9-135040 discloses an LED chip having a pair of positive and negative electrodes on the same surface side. That is, the light emitting diode is formed on the substrate 1 provided with the predetermined wiring pattern 2 via the Ag (silver) paste 4.
The ED chip 3 is bonded. Also, an electrode (not shown) on the upper surface 3a side of the LED chip 3 is electrically connected to the wiring pattern 2 of the substrate 1 by a bonding wire 5 such as an Au (gold) wire. The periphery of the LED chip 3 is sealed with a resin mold 6 such as an epoxy resin to protect the LED chip 3.
【0004】この発光ダイオードは、LEDチップ3の
pn接合部の発光層(活性層)より上向きに出た光は、
光出射面としての上面3aから上方に出射する。また、
LEDチップ3の発光層より下向きに出た光は、LED
チップ3下面のペースト4で拡散反射し、その一部が上
向きに反射して、上面3aから出射する。In this light emitting diode, light emitted upward from the light emitting layer (active layer) at the pn junction of the LED chip 3
Light is emitted upward from the upper surface 3a as a light emission surface. Also,
Light emitted downward from the light emitting layer of the LED chip 3 is an LED.
The light is diffusely reflected by the paste 4 on the lower surface of the chip 3, and a part of the light is reflected upward and emitted from the upper surface 3a.
【0005】[0005]
【発明が解決しようとする課題】従来の発光ダイオード
は、LEDチップ3の光出射面である上面3aに電極が
設けられているため、電極が影となる。よって、電極面
積の分だけ発光面積が減少して光の取り出し効率が低下
し、発光効率の点で改善すべき余地がある。また、LE
Dチップ3下面のAgペースト4が経年変化で変色する
ため、下向きの光の反射効率が低下し、光の取り出し効
率が更に低下する可能性がある。また、LEDチップ3
の電極と基板1の配線パターン2との電気的接続にボン
ディングワイヤ5を使用するため、ワイヤボンディング
用のスペースが必要となり、発光ダイオード全体が大型
化する可能性がある。In the conventional light emitting diode, since the electrode is provided on the upper surface 3a, which is the light emitting surface of the LED chip 3, the electrode becomes a shadow. Therefore, the light emitting area is reduced by the electrode area, the light extraction efficiency is reduced, and there is room for improvement in light emitting efficiency. Also, LE
Since the Ag paste 4 on the lower surface of the D chip 3 changes color over time, the reflection efficiency of downward light decreases, and the light extraction efficiency may further decrease. LED chip 3
Since the bonding wire 5 is used for electrical connection between the electrode and the wiring pattern 2 of the substrate 1, a space for wire bonding is required, and the entire light emitting diode may be increased in size.
【0006】そこで、本発明は、同一面側に正負一対の
電極を有するLEDチップを基板の配線パターンに電気
的に接続することができる一方で、光の取り出し効率を
向上することができる発光ダイオードの提供を課題とす
るものである。Accordingly, the present invention provides a light emitting diode which can electrically connect an LED chip having a pair of positive and negative electrodes on the same surface to a wiring pattern on a substrate, while improving the light extraction efficiency. The purpose is to provide
【0007】[0007]
【課題を解決するための手段】請求項1にかかる発光ダ
イオードは、一対の配線パターンを有する基板と、同一
面側に正負一対の電極を有し、前記両電極を前記基板の
両配線パターンにそれぞれバンプを介して電気的に接続
したLEDチップとを具備する。According to a first aspect of the present invention, there is provided a light emitting diode having a substrate having a pair of wiring patterns and a pair of positive and negative electrodes on the same surface side, wherein both electrodes are connected to both wiring patterns of the substrate. LED chips electrically connected via bumps.
【0008】請求項2にかかる発光ダイオードは、一対
の配線パターンを有する基板と、同一面側に正負一対の
電極を有し、前記両電極を前記基板の両配線パターンに
それぞれバンプを介して電気的に接続したLEDチップ
と、前記LEDチップの少なくとも両電極間を封止する
電気絶縁性のアンダーフィル樹脂とを具備する。According to a second aspect of the present invention, there is provided a light emitting diode having a substrate having a pair of wiring patterns and a pair of positive and negative electrodes on the same surface side, wherein both electrodes are electrically connected to both wiring patterns of the substrate via bumps. And an electrically insulative underfill resin that seals between at least both electrodes of the LED chip.
【0009】請求項3にかかる発光ダイオードは、一対
の配線パターンを有する基板と、同一面側に正負一対の
電極を有し、前記両電極を前記基板の両配線パターンに
それぞれバンプを介して電気的に接続したLEDチップ
と、前記LEDチップの少なくとも両電極間を封止する
異方導電性ペーストとを具備する。According to a third aspect of the present invention, there is provided a light emitting diode having a substrate having a pair of wiring patterns and a pair of positive and negative electrodes on the same surface side, wherein both electrodes are electrically connected to both wiring patterns of the substrate via bumps. And an anisotropic conductive paste for sealing at least between both electrodes of the LED chip.
【0010】請求項4にかかる発光ダイオードは、請求
項1乃至請求項3のいずれかの構成において、前記基板
の配線パターンは、基板の長さ方向に間隔を置いて対向
配置される電極部を有し、前記LEDチップは略矩形板
状をなすと共にその対角線方向に前記正負一対の電極を
配置し、前記正負一対の電極を前記配線パターンの両電
極部に対向配置して電気的に接続するものである。According to a fourth aspect of the present invention, in the light emitting diode according to any one of the first to third aspects, the wiring pattern of the substrate includes an electrode portion which is opposed to the substrate at a distance in a longitudinal direction of the substrate. The LED chip has a substantially rectangular plate shape, and the pair of positive and negative electrodes is arranged in a diagonal direction of the LED chip, and the pair of positive and negative electrodes is disposed to face and electrically connect to both electrode portions of the wiring pattern. Things.
【0011】請求項5にかかる発光ダイオードは、請求
項1乃至請求項3のいずれかの構成において、前記基板
の配線パターンは、基板の長さ方向と傾斜する方向に間
隔を置いて対向配置される電極部を有し、前記LEDチ
ップは略矩形板状をなすと共にその対角線方向に前記正
負一対の電極を配置し、前記正負一対の電極を前記配線
パターンの電極部に対向配置して電気的に接続するもの
である。According to a fifth aspect of the present invention, in the light emitting diode according to any one of the first to third aspects, the wiring pattern of the substrate is opposed to the wiring pattern at an interval in a direction inclined with the length direction of the substrate. The LED chip has a substantially rectangular plate shape, and the pair of positive and negative electrodes are arranged diagonally in the LED chip. Is to be connected to.
【0012】請求項6にかかる発光ダイオードは、請求
項1乃至請求項3のいずれかの構成において、前記基板
の配線パターンは、基板の長さ方向に間隔を置いて対向
配置される電極部を有し、前記LEDチップは略長方形
板状をなすと共にその長さ方向に前記正負一対の電極を
配置し、前記正負一対の電極を前記配線パターンの電極
部に対向配置して電気的に接続するものである。According to a sixth aspect of the present invention, in the light emitting diode according to any one of the first to third aspects, the wiring pattern of the substrate includes an electrode portion which is opposed to the wiring pattern at an interval in the longitudinal direction of the substrate. The LED chip has a substantially rectangular plate shape, and the pair of positive and negative electrodes is arranged in the length direction thereof, and the pair of positive and negative electrodes are disposed to face and electrically connect to the electrode portion of the wiring pattern. Things.
【0013】請求項7にかかる発光ダイオードは、請求
項1乃至請求項6のいずれかの構成において、前記基板
をMID基板としたものである。According to a seventh aspect of the present invention, in the light emitting diode according to any one of the first to sixth aspects, the substrate is an MID substrate.
【0014】[0014]
【発明の実施の形態】以下、本発明の実施の形態を説明
する。Embodiments of the present invention will be described below.
【0015】図1は本発明の実施の形態1にかかる発光
ダイオードの全体構成を示す断面図である。また、図2
は本発明の実施の形態1にかかる発光ダイオードの要部
を示す断面図である。FIG. 1 is a sectional view showing the entire structure of the light emitting diode according to the first embodiment of the present invention. FIG.
FIG. 2 is a cross-sectional view illustrating a main part of the light emitting diode according to the first embodiment of the present invention.
【0016】図1に示すように、実施の形態1の発光ダ
イオードは、正負一対の電極を構成する所定の配線パタ
ーン12を有する基板11と、LEDチップ13を備え
る。LEDチップ13の下面にはAuパッド等の金属層
からなる反射層14が、金属蒸着等により全面に形成さ
れている。LEDチップ13は、同一面側(図中下面
側)に正負一対の電極(図示略)を有し、両電極をフリ
ップチップボンディングにより基板11の両配線パター
ン12にそれぞれバンプ15を介して電気的に接続する
ようになっている。As shown in FIG. 1, the light emitting diode according to the first embodiment includes a substrate 11 having a predetermined wiring pattern 12 forming a pair of positive and negative electrodes, and an LED chip 13. On the lower surface of the LED chip 13, a reflective layer 14 made of a metal layer such as an Au pad is formed on the entire surface by metal deposition or the like. The LED chip 13 has a pair of positive and negative electrodes (not shown) on the same surface side (the lower surface side in the figure), and both electrodes are electrically connected to both wiring patterns 12 of the substrate 11 via bumps 15 by flip chip bonding. To connect to.
【0017】図2に示すように、実施の形態1の発光ダ
イオードは、更に、前記LEDチップ13の少なくとも
正負一対の電極間を封止する絶縁性のアンダーフィル樹
脂16を備える。詳細には、前記アンダーフィル樹脂1
6は、エポキシ樹脂等、絶縁性樹脂からなり、LEDチ
ップ13の全周囲を覆い、かつ、LEDチップ13の下
面側と基板11の表面側との隙間を封止している。即
ち、アンダーフィル樹脂16は、LEDチップ13の両
電極間に充填され、それらの電気的絶縁を維持するよう
になっている。なお、実施の形態1の発光ダイオード
も、従来例と同様、LEDチップ13の周囲全体をエポ
キシ樹脂等の樹脂モールド6により封止し、保護してい
る。As shown in FIG. 2, the light emitting diode of the first embodiment further includes an insulating underfill resin 16 for sealing at least between a pair of positive and negative electrodes of the LED chip 13. Specifically, the underfill resin 1
Reference numeral 6 is made of an insulating resin such as an epoxy resin, covers the entire periphery of the LED chip 13, and seals a gap between the lower surface of the LED chip 13 and the surface of the substrate 11. That is, the underfill resin 16 is filled between the two electrodes of the LED chip 13 to maintain their electrical insulation. In the light-emitting diode of the first embodiment, the entire periphery of the LED chip 13 is sealed and protected by a resin mold 6 such as an epoxy resin, similarly to the conventional example.
【0018】ここで、フリップチップボンディングは、
LSI等の半導体製作技術の組立配線工程で使用される
ものであり、バンプ15としては、Auバンプ、はんだ
バンプ等、種々のバンプを使用することができる。な
お、前記基板11としては、ガラスエポキシ樹脂、BT
樹脂等からなる通常の絶縁基板を使用可能である。ま
た、プリント配線12は、エッチング法等、通常の半導
体製作技術の電極配線技術を使用して形成され、例え
ば、Cu+Ni等の下地金属層にAu等の金属めっき層
を積層して形成される。Here, flip chip bonding is
The bump 15 is used in an assembly wiring process of a semiconductor manufacturing technology such as an LSI, and various bumps such as an Au bump and a solder bump can be used as the bump 15. The substrate 11 is made of glass epoxy resin, BT
A normal insulating substrate made of resin or the like can be used. The printed wiring 12 is formed by using an electrode wiring technique of a normal semiconductor manufacturing technique such as an etching method. For example, the printed wiring 12 is formed by stacking a metal plating layer such as Au on a base metal layer such as Cu + Ni.
【0019】同一面側に正負一対の電極を有するLED
としては、例えば、特開平4−10671号公報、特開
平5−21846号公報に掲載の技術を使用することが
できる。このうち、特開平4−10671号公報は、絶
縁物であるサファイア基板上にn−GaN(n型の窒化
ガリウム)層及びi−GaN(i型の窒化ガリウム)層
を順に成長して積層して形成した青色発光LEDを開示
している。このLEDは、正負一対の電極の一方をi−
GaN層の表面に設け、正負一対の電極の他方をi−G
aN層に貫通して設けている。そして、これらの電極を
リードフレームに接合して電気的に接続している。LED having a pair of positive and negative electrodes on the same side
For example, the techniques described in JP-A-4-10671 and JP-A-5-21846 can be used. Among them, Japanese Patent Application Laid-Open No. 4-10671 discloses that an n-GaN (n-type gallium nitride) layer and an i-GaN (i-type gallium nitride) layer are sequentially grown and laminated on a sapphire substrate which is an insulator. Discloses a blue light emitting LED formed by the above method. In this LED, one of a pair of positive and negative electrodes is i-
It is provided on the surface of the GaN layer, and the other of the pair of positive and negative electrodes is an i-G
It is provided through the aN layer. These electrodes are joined to a lead frame for electrical connection.
【0020】また、特開平5−21846号公報は、例
えば、サファイア基板上に、AlN(窒化アルミニウ
ム)からなるバッファ層、GaNからなる高キャリヤ濃
度n+層、GaNからなる低キャリヤ濃度n層、GaN
からなるi層を順に成長積層した青色発光LEDを開示
している。このLEDは、正負一対の電極の一方をi層
の表面中央に設け、正負一対の電極の他方を高キャリヤ
濃度n+層に側面から接続するよう設けている。そし
て、これらの電極をリードフレームに接合して電気的に
接続している。なお、LEDチップ13としては、特開
平4−10671号公報または特開平5−21846号
公報に記載のものの他、同一面側に正負一対の電極を有
する種々のLEDチップを使用可能である。Japanese Patent Laid-Open Publication No. Hei 5-21846 discloses, for example, a buffer layer made of AlN (aluminum nitride), a high carrier concentration n + layer made of GaN, a low carrier concentration n layer made of GaN,
Discloses a blue light-emitting LED in which an i-layer consisting of In this LED, one of the pair of positive and negative electrodes is provided at the center of the surface of the i-layer, and the other of the pair of positive and negative electrodes is connected to the high carrier concentration n + layer from the side. These electrodes are joined to a lead frame for electrical connection. As the LED chip 13, various LED chips having a pair of positive and negative electrodes on the same surface side can be used in addition to those described in JP-A-4-10671 or JP-A-5-21846.
【0021】次に、上記のように構成された実施の形態
1にかかる発光ダイオードの製造方法及び作用を説明す
る。Next, the manufacturing method and operation of the light emitting diode according to the first embodiment configured as described above will be described.
【0022】実施の形態1の発光ダイオードは、まず、
基板11の配線パターン12に導電ペースト(導電性接
着剤)を塗布し、電極にバンプ15を予め付着したLE
Dチップ13を配線パターン12に位置決めして載置す
る。次に、LEDチップ13を基板11に圧着した状態
でバンプ15を硬化し、正負一対の電極を対応する配線
パターン12に電気的に接続する。なお、LEDチップ
の圧着硬化は、例えば、約10kgf/mm2 以上の押圧状態
で、樹脂部温度を摂氏約170乃至200度に30秒程
度維持して行う。その後、アンダーフィル樹脂16を基
板11とLEDチップ13との間の隙間に塗布して浸透
充填し、硬化する。First, the light emitting diode of Embodiment 1
LE in which a conductive paste (conductive adhesive) is applied to the wiring pattern 12 of the substrate 11 and bumps 15 are previously attached to the electrodes
The D chip 13 is positioned and placed on the wiring pattern 12. Next, the bump 15 is cured while the LED chip 13 is pressed against the substrate 11, and the pair of positive and negative electrodes is electrically connected to the corresponding wiring pattern 12. The LED chip is pressurized and cured by, for example, maintaining the temperature of the resin part at about 170 to 200 degrees Celsius for about 30 seconds under a pressing state of about 10 kgf / mm 2 or more. After that, the underfill resin 16 is applied to the gap between the substrate 11 and the LED chip 13, penetratingly filled, and cured.
【0023】これにより、アンダーフィル樹脂16がL
EDチップ13の正負一対の電極間の電気的絶縁を確保
し、それらの間の短絡が防止される。なお、アンダーフ
ィル樹脂16を先に基板12に塗布し、その上にバンプ
15を予め付着したLEDチップ13を位置決めして載
置し、上記と同様の条件にて圧着硬化しても良い。かか
るLEDチップ13の圧着後、エポキシ樹脂等の樹脂モ
ールド6によりLEDチップ13の周囲を封止して、L
EDチップ13を保護することにより、最終製品として
の発光ダイオードが形成される。As a result, the underfill resin 16 becomes L
Electrical insulation between the pair of positive and negative electrodes of the ED chip 13 is ensured, and a short circuit between them is prevented. Note that the underfill resin 16 may be applied to the substrate 12 first, the LED chip 13 with the bump 15 previously attached thereto may be positioned and mounted thereon, and may be press-hardened under the same conditions as described above. After the pressure bonding of the LED chip 13, the periphery of the LED chip 13 is sealed with a resin mold 6 such as an epoxy resin, and
By protecting the ED chip 13, a light emitting diode as a final product is formed.
【0024】このように形成した発光ダイオードは、L
EDチップ13の正負一対の電極が光出射面と反対側の
下面側に位置するため、光出射面である上面13aに光
を遮る影となるものが何もなく、LEDチップ13の上
面13a全体が発光面積となる。また、LEDチップ1
3の下面全体に反射層14を形成し、下向きの光の反射
効率を増大することができる。その結果、LEDチップ
13からの光の取り出し効率を増大して、発光効率乃至
輝度を向上することができる。また、LEDチップ13
の両電極と基板11の両配線パターン12との電気的接
続をフリップチップボンディングにより行うため、従来
のようなワイヤボンディング用のスペースが不要とな
り、発光ダイオード全体を小型化することができる。更
に、LEDチップ13の両電極を直接基板11の両配線
パターン12に接続することができるため、LEDチッ
プ13駆動時の放熱性が向上し、発光ダイオードの信頼
性及び耐久性が向上する。The light emitting diode thus formed has an L
Since the pair of positive and negative electrodes of the ED chip 13 are located on the lower surface side opposite to the light emitting surface, there is no shadow on the upper surface 13a, which is the light emitting surface, and the entire upper surface 13a of the LED chip 13 Is the light emitting area. LED chip 1
3, the reflection layer 14 is formed on the entire lower surface, so that the reflection efficiency of downward light can be increased. As a result, the light extraction efficiency from the LED chip 13 is increased, and the luminous efficiency or luminance can be improved. Also, the LED chip 13
The electrical connection between the two electrodes and the two wiring patterns 12 on the substrate 11 is performed by flip-chip bonding, so that a space for wire bonding as in the related art is unnecessary, and the entire light emitting diode can be reduced in size. Furthermore, since both electrodes of the LED chip 13 can be directly connected to both the wiring patterns 12 of the substrate 11, the heat dissipation during driving the LED chip 13 is improved, and the reliability and durability of the light emitting diode are improved.
【0025】図3は本発明の実施の形態2にかかる発光
ダイオードの要部を示す断面図である。FIG. 3 is a sectional view showing a main part of a light emitting diode according to a second embodiment of the present invention.
【0026】実施の形態2の発光ダイオードは、アンダ
ーフィル樹脂16の代わりに、異方導電性樹脂21を使
用した点において、実施の形態1の発光ダイオードと異
なり、その他の構成は同様であるため、その要部のみ図
示して説明する。即ち、実施の形態2の発光ダイオード
は、異方導電性ペースト21により前記LEDチップ1
3の少なくとも正負一対の電極間を封止している。この
異方導電性ペースト21自体は、エポキシベースの樹脂
に絶縁コート付きAgフィラー等のAg粒子を5〜10
%混入した公知のものである。かかる異方導電性ペース
ト21によりLEDチップ13の全周囲を覆い、かつ、
LEDチップ13と基板11表面の間を封止している。
これにより、配線パターン12を介してLEDチップ1
3の両電極間に電圧を印可すると、異方導電性ペースト
21が、横方向乃至水平方向(図3中左右方向)に電気
的絶縁を維持し、かつ、縦方向乃至垂直方向(図3中上
下方向)に電気的導通を確保するようになっている。な
お、実施の形態2の発光ダイオードも、従来例と同様、
LEDチップ13の周囲全体をエポキシ樹脂等の樹脂モ
ールド6により封止し、保護している。The light emitting diode of the second embodiment differs from the light emitting diode of the first embodiment in that an anisotropic conductive resin 21 is used instead of the underfill resin 16, and the other configuration is the same. , Only the main parts are illustrated and described. That is, the light emitting diode of the second embodiment uses the anisotropic conductive paste 21 for the LED chip 1.
3 at least between the pair of positive and negative electrodes. This anisotropic conductive paste 21 itself is formed by adding 5 to 10 Ag particles such as an Ag filler with an insulating coat to an epoxy-based resin.
%. The entire periphery of the LED chip 13 is covered with the anisotropic conductive paste 21, and
The space between the LED chip 13 and the surface of the substrate 11 is sealed.
Thereby, the LED chip 1 is connected via the wiring pattern 12.
When a voltage is applied between the two electrodes 3, the anisotropic conductive paste 21 maintains electrical insulation in a horizontal direction or a horizontal direction (horizontal direction in FIG. 3) and a vertical direction or a vertical direction (in FIG. 3). (Up and down direction) to ensure electrical continuity. Note that the light emitting diode of Embodiment 2 is also similar to the conventional example.
The entire periphery of the LED chip 13 is sealed and protected by a resin mold 6 such as an epoxy resin.
【0027】次に、上記のように構成された実施の形態
2にかかる発光ダイオードの製造方法及び作用を説明す
る。Next, a description will be given of a method and an operation of manufacturing the light emitting diode according to the second embodiment configured as described above.
【0028】実施の形態2の発光ダイオードは、まず、
基板11の配線パターン12に異方導電性ペースト21
を塗布し、電極にバンプ15を予め付着したLEDチッ
プ13を配線パターン12に位置決めして異方導電性ペ
ースト21を介装した状態で載置する。以後は、実施の
形態1と同様にして、LEDチップ13を圧着してバン
プ15を硬化し、正負一対の電極を対応する配線パター
ン12に電気的に接続する。これにより、異方導電性ペ
ースト21が横方向、即ち、LEDチップ13の両電極
間の電気的絶縁を確保し、それらの間の短絡が防止され
る。同時に、異方導電性ペースト21が縦方向、即ち、
LEDチップ13の正負の電極と基板11の配線パター
ン12との間の電気的導通を確保する。The light emitting diode of Embodiment 2
Anisotropic conductive paste 21 is applied to wiring pattern 12 of substrate 11
Is applied, the LED chip 13 having the bump 15 attached to the electrode in advance is positioned on the wiring pattern 12 and placed with the anisotropic conductive paste 21 interposed therebetween. Thereafter, as in the first embodiment, the LED chip 13 is pressed and the bump 15 is cured, and the pair of positive and negative electrodes is electrically connected to the corresponding wiring pattern 12. Thereby, the anisotropic conductive paste 21 secures the electrical insulation in the horizontal direction, that is, between the two electrodes of the LED chip 13, and the short circuit between them is prevented. At the same time, the anisotropic conductive paste 21 is in the vertical direction,
Electrical conduction between the positive and negative electrodes of the LED chip 13 and the wiring pattern 12 of the substrate 11 is ensured.
【0029】したがって、配線パターン12に対するL
EDチップ13の位置決めが多少正確でない場合でも、
正負電極間での短絡が生じることはなく、かつ、配線パ
ターン12との間では導電性が確保される。また、LE
Dチップ13の各電極に付着したバンプ15の高さがば
らつく場合でも、異方導電性ペースト21のAg粒子が
そのばらつきを吸収するため、配線パターン12との電
気的接続における信頼性が増加する。その結果、位置あ
わせ精度が多少ばらついても良く、位置決め作業を簡略
化することができる。特に、通常のLSIと比較して電
極間ピッチが狭く、電極間の絶縁確保に高信頼性が要求
されるLEDチップ13のフリップチップボンディング
に好適であり、発光ダイオードの動作信頼性を一層向上
して、製品品質を一層向上することができる。Therefore, L for the wiring pattern 12
Even if the positioning of the ED chip 13 is somewhat inaccurate,
A short circuit does not occur between the positive and negative electrodes, and conductivity between the positive and negative electrodes and the wiring pattern 12 is ensured. Also, LE
Even when the height of the bump 15 attached to each electrode of the D chip 13 varies, the Ag particles of the anisotropic conductive paste 21 absorb the variation, so that the reliability in the electrical connection with the wiring pattern 12 increases. . As a result, the positioning accuracy may vary to some extent, and the positioning operation can be simplified. In particular, it is suitable for flip-chip bonding of the LED chip 13 in which the pitch between electrodes is narrower than that of a normal LSI and high reliability is required for securing insulation between the electrodes, and the operation reliability of the light emitting diode is further improved. Thus, product quality can be further improved.
【0030】図4は本発明の実施の形態3にかかる発光
ダイオードの平面図である。FIG. 4 is a plan view of a light emitting diode according to the third embodiment of the present invention.
【0031】実施の形態3は、LEDチップの電極間の
電気的絶縁を確保するための構造を改良したことを特徴
とし、全体構成は実施の形態1及び2と同様である。即
ち、図4に示すように、実施の形態3の発光ダイオード
は、正負一対の電極を構成する所定の配線パターン32
を有する基板31と、LEDチップ33を備える。図示
はしないが、LEDチップ33の下面には実施の形態1
の反射層14と同様の反射層が全面に形成されている。
LEDチップ33は、同一面側(図中下面側)に正負一
対の電極を有し、両電極をフリップチップボンディング
により基板31の両配線パターン32にそれぞれバンプ
35を介して電気的に接続するようになっている。The third embodiment is characterized in that the structure for ensuring electrical insulation between the electrodes of the LED chip is improved, and the overall configuration is the same as in the first and second embodiments. That is, as shown in FIG. 4, the light emitting diode of the third embodiment has a predetermined wiring pattern 32 forming a pair of positive and negative electrodes.
And a LED chip 33. Although not shown, the lower surface of the LED chip 33 is provided with the first embodiment.
A reflective layer similar to the reflective layer 14 is formed on the entire surface.
The LED chip 33 has a pair of positive and negative electrodes on the same surface side (the lower surface side in the figure), and both electrodes are electrically connected to both wiring patterns 32 of the substrate 31 via bumps 35 by flip chip bonding. It has become.
【0032】基本的に、前記基板31、配線パターン3
2、LEDチップ33及びバンプ35は、配線パター3
2の具体的パターン形状及びLEDチップ33の電極位
置を除き、実施の形態1及び2の基板11、配線パター
ン12、LEDチップ13及びバンプ15と同様の構成
とすることができる。一方、これらの具体的構成を詳述
すると、前記基板31は略長方形板状をなす。また、両
配線パターン32は左右対称形状をなすと共に、基板3
1の長さ方向に間隔を置いて対向配置される電極部32
aをそれぞれ有する。前記電極部32aは基板31の長
さ方向に延びる中心線に沿って延設されている。更に、
LEDチップ33は正方形板状をなし、その対角線上
(対角線方向)に前記正負一対の電極を配置している。
そして、電極部32aの先端間の間隔(電極部間ピッ
チ)は、LEDチップ33の電極間の間隔(電極間ピッ
チ)と同一とされている。これにより、LEDチップ3
3を、対角線方向を基板31の長さ方向に延びる中心線
に一致させ、基板31の中央に配置することにより、L
EDチップ33の前記両電極が前記配線パターン32の
両電極部32aの先端部に対向配置される。そして、か
かるLEDチップ33の正負一対の電極を対応する電極
部32aにバンプ35を介して電気的に接続するように
なっている。即ち、実施の形態3は、LEDチップ33
の対角線方向に電極を配置するため、電極間ピッチを広
く取ることができる。また、これに合わせ、配線パター
ン32の電極部32a間ピッチもより広く設定すること
ができる。Basically, the substrate 31, the wiring pattern 3
2. The LED chip 33 and the bump 35 are
Except for the specific pattern shape 2 and the electrode position of the LED chip 33, the configuration can be the same as that of the substrate 11, the wiring pattern 12, the LED chip 13 and the bump 15 of the first and second embodiments. On the other hand, when these specific configurations are described in detail, the substrate 31 has a substantially rectangular plate shape. The two wiring patterns 32 have a symmetrical shape and the substrate 3
Electrodes 32 opposed to each other at intervals in the longitudinal direction
a. The electrode portion 32a extends along a center line extending in the length direction of the substrate 31. Furthermore,
The LED chip 33 has a square plate shape, and the pair of positive and negative electrodes is arranged on a diagonal line (in a diagonal direction).
The distance between the tips of the electrode portions 32a (the pitch between the electrode portions) is the same as the distance between the electrodes of the LED chip 33 (the pitch between the electrodes). Thereby, the LED chip 3
3 is arranged at the center of the substrate 31 so that the diagonal direction coincides with the center line extending in the length direction of the substrate 31 so that L
The two electrodes of the ED chip 33 are arranged to face the front ends of the two electrode portions 32 a of the wiring pattern 32. The pair of positive and negative electrodes of the LED chip 33 are electrically connected to the corresponding electrode portions 32a via the bumps 35. That is, in the third embodiment, the LED chip 33
Since the electrodes are arranged in the diagonal direction, the pitch between the electrodes can be widened. In accordance with this, the pitch between the electrode portions 32a of the wiring pattern 32 can be set wider.
【0033】なお、実施の形態3の発光ダイオードは、
実施の形態1または実施の形態2と同様、アンダーフィ
ル樹脂16または異方導電性ペースト21等により、L
EDチップ33の全周囲を覆い、かつ、LEDチップ3
3の下面側と基板31の表面側との隙間を封止してい
る。また、従来例と同様、LEDチップ33の周囲全体
をエポキシ樹脂等の樹脂モールド6により封止し、保護
している。The light emitting diode of the third embodiment is
As in the first or second embodiment, the underfill resin 16 or the anisotropic conductive paste
The entire periphery of the ED chip 33 and the LED chip 3
The gap between the lower surface of the substrate 3 and the surface of the substrate 31 is sealed. Further, similarly to the conventional example, the entire periphery of the LED chip 33 is sealed and protected by a resin mold 6 such as an epoxy resin.
【0034】上記のように構成した実施の形態3の発光
ダイオードは、実施の形態1または2と同様にして製造
され、同様の作用及び効果を有する。加えて、実施の形
態3の発光ダイオードは、LEDチップ33の対角線方
向に正負一対の電極を配置するため、LEDチップ33
の電極間ピッチ及び配線パターン32の電極部32a間
ピッチがより大きくなる。その結果、実施の形態1また
は2におけるように、LEDチップ33の長さ方向に電
極を配置する場合と比べ、電極間での短絡を一層効果的
に防止して、発光ダイオードの動作信頼性をより向上
し、製品品質を一層向上することができる。The light emitting diode of the third embodiment configured as described above is manufactured in the same manner as in the first or second embodiment, and has the same functions and effects. In addition, since the light emitting diode of the third embodiment has a pair of positive and negative electrodes arranged in a diagonal direction of the LED chip 33, the LED chip 33
And the pitch between the electrode portions 32a of the wiring pattern 32 become larger. As a result, as compared with the case where the electrodes are arranged in the length direction of the LED chip 33 as in Embodiment 1 or 2, the short circuit between the electrodes is more effectively prevented, and the operation reliability of the light emitting diode is improved. It is possible to further improve the product quality.
【0035】図5は本発明の実施の形態4にかかる発光
ダイオードの平面図である。FIG. 5 is a plan view of a light emitting diode according to a fourth embodiment of the present invention.
【0036】実施の形態4は、実施の形態3と同様、L
EDチップの電極間の電気的絶縁を確保するための構造
を改良したことを特徴とし、全体構成は実施の形態1及
び2と同様である。即ち、図5に示すように、実施の形
態4の発光ダイオードは、正負一対の電極を構成する所
定の配線パターン42を有する基板41と、LEDチッ
プ43を備える。図示はしないが、LEDチップ43の
下面には実施の形態1の反射層14と同様の反射層が全
面に形成されている。LEDチップ43は、同一面側
(図中下面側)に正負一対の電極を有し、両電極をフリ
ップチップボンディングにより基板41の両配線パター
ン42にそれぞれバンプ45を介して電気的に接続する
ようになっている。In the fourth embodiment, as in the third embodiment, L
It is characterized in that the structure for ensuring electrical insulation between the electrodes of the ED chip is improved, and the overall configuration is the same as in the first and second embodiments. That is, as shown in FIG. 5, the light emitting diode according to the fourth embodiment includes a substrate 41 having a predetermined wiring pattern 42 forming a pair of positive and negative electrodes, and an LED chip 43. Although not shown, a reflection layer similar to the reflection layer 14 of the first embodiment is formed on the entire lower surface of the LED chip 43. The LED chip 43 has a pair of positive and negative electrodes on the same surface side (the lower surface side in the drawing), and both electrodes are electrically connected to both wiring patterns 42 of the substrate 41 via bumps 45 by flip chip bonding. It has become.
【0037】実施の形態4の基本構成は、実施の形態3
の基本構成と同様であるが、配線パターン42の具体的
パターン形状を実施の形態3の配線パターン32と相違
させている。即ち、基本的に、前記基板41、配線パタ
ーン42、LEDチップ43及びバンプ45は、配線パ
ターン42の具体的パターン形状及びLEDチップ43
の電極位置を除き、実施の形態1及び2の基板11、配
線パターン12、LEDチップ13及びバンプ15と同
様の構成とすることができる。一方、これらの具体的構
成を詳述すると、前記基板41は略長方形板状をなし、
かつ、両配線パターン42は左右対称形状をなすと共
に、基板41の長さ方向と傾斜する方向に間隔を置いて
対向配置される電極部42aをそれぞれ有する。The basic configuration of the fourth embodiment is similar to that of the third embodiment.
However, the specific pattern shape of the wiring pattern 42 is different from that of the wiring pattern 32 of the third embodiment. That is, basically, the substrate 41, the wiring pattern 42, the LED chip 43, and the bump 45 are formed by the specific pattern shape of the wiring pattern 42 and the LED chip 43.
Except for the positions of the electrodes described above, the configuration can be the same as that of the substrate 11, the wiring pattern 12, the LED chip 13, and the bumps 15 of the first and second embodiments. On the other hand, when these specific configurations are described in detail, the substrate 41 has a substantially rectangular plate shape,
In addition, the two wiring patterns 42 are symmetrical in shape and have electrode portions 42a opposed to each other at intervals in the direction inclined with respect to the length direction of the substrate 41.
【0038】即ち、前記電極部42aは、基板41の長
さ方向に延びる中心線と所定角度で互いに離間する方向
に傾斜して延設されている。更に、LEDチップ43は
正方形板状をなし、その対角線上に前記正負一対の電極
を配置している。そして、電極部42aの先端間の間隔
は、LEDチップ43の電極間の間隔と同一とされてい
る。これにより、LEDチップ43を、中心線を基板4
1の長さ方向に延びる中心線に一致させ、基板41の中
央に配置することにより、LEDチップ43の前記両電
極が前記配線パターン42の両電極部42aの先端部に
対向配置される。そして、かかるLEDチップ43の正
負一対の電極を対応する電極部42aにバンプ45を介
して電気的に接続するようになっている。That is, the electrode portion 42a is extended so as to be inclined in a direction away from the center line extending in the length direction of the substrate 41 at a predetermined angle. Further, the LED chip 43 has a square plate shape, and the pair of positive and negative electrodes is arranged on a diagonal line thereof. The distance between the tips of the electrode portions 42a is the same as the distance between the electrodes of the LED chip 43. As a result, the LED chip 43 is connected to the center line of the substrate 4.
The two electrodes of the LED chip 43 are arranged so as to be opposed to the front ends of the two electrode portions 42 a of the wiring pattern 42 by being aligned with the center line extending in the length direction of the first and the center of the substrate 41. The pair of positive and negative electrodes of the LED chip 43 are electrically connected to the corresponding electrode portions 42a via bumps 45.
【0039】即ち、実施の形態4は、実施の形態3と同
様、LEDチップ43の対角線方向に電極を配置するた
め、電極間ピッチを広く取ることができる。また、これ
に合わせ、配線パターン42の電極部42a間ピッチも
より広く設定することができる。更に、配線パターン4
2のパターン形状を変更し、電極部42aを基板41の
長さ方向と傾斜するよう互いに離間する方向に延設した
ため、LEDチップ43を基板41に通常状態(中心線
を一致させた状態)で配置することができる。That is, in the fourth embodiment, as in the third embodiment, since the electrodes are arranged in the diagonal direction of the LED chip 43, the pitch between the electrodes can be widened. In accordance with this, the pitch between the electrode portions 42a of the wiring pattern 42 can be set wider. Furthermore, wiring pattern 4
2 was changed, and the electrode portion 42a was extended in the direction away from each other so as to incline with the length direction of the substrate 41. Therefore, the LED chip 43 was placed on the substrate 41 in the normal state (the center line was aligned). Can be arranged.
【0040】なお、実施の形態4の発光ダイオードは、
実施の形態1または実施の形態2と同様、アンダーフィ
ル樹脂16または異方導電性ペースト21等により、L
EDチップ43の全周囲を覆い、かつ、LEDチップ4
3の下面側と基板41の表面側との隙間を封止してい
る。また、従来例と同様、LEDチップ43の周囲全体
をエポキシ樹脂等の樹脂モールド6により封止し、保護
している。The light emitting diode of the fourth embodiment is
As in the first or second embodiment, the underfill resin 16 or the anisotropic conductive paste
The entire periphery of the ED chip 43 and the LED chip 4
The gap between the lower surface of the substrate 3 and the surface of the substrate 41 is sealed. As in the conventional example, the entire periphery of the LED chip 43 is sealed and protected by a resin mold 6 such as an epoxy resin.
【0041】上記のように構成した実施の形態4の発光
ダイオードは、実施の形態1または2と同様にして製造
され、同様の作用及び効果を有する。加えて、実施の形
態4の発光ダイオードは、LEDチップ43の対角線方
向に正負一対の電極を配置するため、実施の形態3と同
様の効果を発揮する。更に、LEDチップ43を基板4
1に通常状態で配置できるため、LEDチップ43の位
置決め乃至配置作業を通常の方法で行うことができる。
即ち、実質的に配線パターン42のパターン形状を変更
するだけで、実施の形態3と同様の効果を発揮すること
ができる。The light emitting diode of the fourth embodiment configured as described above is manufactured in the same manner as in the first or second embodiment, and has the same functions and effects. In addition, the light emitting diode of the fourth embodiment has the same effect as that of the third embodiment because a pair of positive and negative electrodes is arranged in the diagonal direction of the LED chip 43. Further, the LED chip 43 is attached to the substrate 4
Since the LED chip 43 can be arranged in a normal state, the operation of positioning or arranging the LED chip 43 can be performed by an ordinary method.
That is, the same effect as in the third embodiment can be exerted only by substantially changing the pattern shape of the wiring pattern 42.
【0042】図6は本発明の実施の形態5にかかる発光
ダイオードの平面図である。FIG. 6 is a plan view of a light emitting diode according to the fifth embodiment of the present invention.
【0043】実施の形態5は、実施の形態3及び4と同
様、LEDチップの電極間の電気的絶縁を確保するため
の構造を改良したことを特徴とし、全体構成は実施の形
態1及び2と同様である。即ち、図6に示すように、実
施の形態5の発光ダイオードは、正負一対の電極を構成
する所定の配線パターン52を有する基板51と、LE
Dチップ53を備える。図示はしないが、LEDチップ
53の下面には実施の形態1の反射層14と同様の反射
層が全面に形成されている。LEDチップ53は、同一
面側(図中下面側)に正負一対の電極を有し、両電極を
フリップチップボンディングにより基板51の両配線パ
ターン52にそれぞれバンプ55を介して電気的に接続
するようになっている。The fifth embodiment is similar to the third and fourth embodiments in that the structure for ensuring electrical insulation between the electrodes of the LED chip is improved, and the overall configuration is the same as in the first and second embodiments. Is the same as That is, as shown in FIG. 6, the light emitting diode of the fifth embodiment includes a substrate 51 having a predetermined wiring pattern 52 forming a pair of positive and negative electrodes, and a light emitting diode (LE).
A D chip 53 is provided. Although not shown, a reflection layer similar to the reflection layer 14 of the first embodiment is formed on the entire lower surface of the LED chip 53. The LED chip 53 has a pair of positive and negative electrodes on the same surface side (the lower surface side in the figure), and both electrodes are electrically connected to both wiring patterns 52 of the substrate 51 via bumps 55 by flip chip bonding. It has become.
【0044】実施の形態5の基本構成は、実施の形態3
の基本構成と同様であるが、LEDチップ53の形状を
実施の形態3のLEDチップ33と相違させている。即
ち、基本的に、前記基板51、配線パターン52、LE
Dチップ53及びバンプ55は、配線パターン52の具
体的パターン形状及びLEDチップ53の形状を除き、
実施の形態1及び2の基板11、配線パターン12、L
EDチップ13及びバンプ15と同様の構成とすること
ができる。一方、これらの具体的構成を詳述すると、前
記基板51は略長方形板状をなし、かつ、両配線パター
ン52は左右対称形状をなすと共に、基板51の長さ方
向に間隔を置いて対向配置される電極部52aをそれぞ
れ有する。前記電極部52aは、基板51の長さ方向に
延びる中心線に沿って延設されている。更に、LEDチ
ップ53は長方形板状をなし、長さ方向に前記正負一対
の電極を配置している。そして、電極部52aの先端間
の間隔は、LEDチップ53の電極間の間隔と同一とさ
れている。これにより、LEDチップ53を、長さ方向
に延びる中心線を基板51の長さ方向に延びる中心線に
一致させ、基板51の中央に配置することにより、LE
Dチップ53の両電極が前記配線パターン52の両電極
部52aの先端部に対向配置される。そして、かかるL
EDチップ53の正負一対の電極を対応する電極部52
aに電気的にバンプ55を介して電気的に接続するよう
になっている。即ち、実施の形態5は、LEDチップ5
3の長さ方向に電極を配置するため、電極間ピッチを広
く取ることができる。また、これに合わせ、配線パター
ン52の電極部52a間ピッチもより広く設定すること
ができる。The basic configuration of the fifth embodiment is similar to that of the third embodiment.
However, the shape of the LED chip 53 is different from that of the LED chip 33 of the third embodiment. That is, basically, the substrate 51, the wiring pattern 52, the LE
The D chip 53 and the bump 55 have the same configuration except for the specific pattern shape of the wiring pattern 52 and the shape of the LED chip 53.
Substrate 11, wiring pattern 12, L of first and second embodiments
The same configuration as the ED chip 13 and the bump 15 can be used. On the other hand, when these specific configurations are described in detail, the substrate 51 has a substantially rectangular plate shape, and both the wiring patterns 52 have a symmetrical shape, and are arranged facing each other at intervals in the length direction of the substrate 51. Each has an electrode part 52a to be formed. The electrode portion 52a extends along a center line extending in the length direction of the substrate 51. Further, the LED chip 53 has a rectangular plate shape, and the pair of positive and negative electrodes is arranged in a length direction. The interval between the tips of the electrode portions 52a is the same as the interval between the electrodes of the LED chip 53. Accordingly, the LED chip 53 is arranged at the center of the substrate 51 such that the center line extending in the length direction coincides with the center line extending in the length direction of the substrate 51, so that the LE
The two electrodes of the D chip 53 are arranged to face the front ends of the two electrode portions 52a of the wiring pattern 52. And such L
An electrode section 52 corresponding to a pair of positive and negative electrodes of the ED chip 53;
a to be electrically connected via a bump 55. That is, in the fifth embodiment, the LED chip 5
Since the electrodes are arranged in the length direction of 3, the pitch between the electrodes can be widened. In accordance with this, the pitch between the electrode portions 52a of the wiring pattern 52 can be set wider.
【0045】なお、実施の形態5の発光ダイオードは、
実施の形態1または実施の形態2と同様、アンダーフィ
ル樹脂16または異方導電性ペースト21等により、L
EDチップ53の全周囲を覆い、かつ、LEDチップ5
3の下面側と基板51の表面側との隙間を封止してい
る。また、従来例と同様、LEDチップ53の周囲全体
をエポキシ樹脂等の樹脂モールド6により封止し、保護
している。The light emitting diode of the fifth embodiment is
As in the first or second embodiment, the underfill resin 16 or the anisotropic conductive paste
The entire periphery of the ED chip 53 and the LED chip 5
The gap between the lower surface of the substrate 3 and the surface of the substrate 51 is sealed. As in the conventional example, the entire periphery of the LED chip 53 is sealed and protected by a resin mold 6 such as an epoxy resin.
【0046】上記のように構成した実施の形態5の発光
ダイオードは、実施の形態1または2と同様にして製造
され、同様の作用及び効果を有する。加えて、実施の形
態5の発光ダイオードは、LEDチップ53の長さ方向
に正負一対の電極を配置するため、実施の形態3または
4と同様の効果を発揮する。The light emitting diode of the fifth embodiment configured as described above is manufactured in the same manner as in the first or second embodiment, and has the same functions and effects. In addition, the light emitting diode of the fifth embodiment has the same effect as that of the third or fourth embodiment because a pair of positive and negative electrodes are arranged in the length direction of the LED chip 53.
【0047】図7は本発明の実施の形態6にかかる発光
ダイオードの断面図である。FIG. 7 is a sectional view of a light emitting diode according to a sixth embodiment of the present invention.
【0048】実施の形態6の発光ダイオードは、基板と
してMID基板を使用し、MID発光ダイオードに具体
化されることを特徴とする。即ち、図7に示すように、
実施の形態6の発光ダイオードは、正負一対の電極を構
成する所定の配線パターン62を有する基板61と、L
EDチップ63を備える。前記基板61は厚肉の四角ブ
ロック状をなすと共に上面側の中央を下方に縮径するコ
ーン状の凹部とし、その凹部に前記両配線パターン62
を延設してコーン状の反射面62aを形成している。両
配線パターン62は前記凹部の底面まで延設されてい
る。前記基板61及び配線パターン62の材料としては
実施の形態1と同様のものを使用することができる。ま
た、LEDチップ63は、実施の形態1のLEDチップ
16と同様のものを使用することができる。The light emitting diode of the sixth embodiment uses an MID substrate as a substrate and is embodied as an MID light emitting diode. That is, as shown in FIG.
The light emitting diode of the sixth embodiment includes a substrate 61 having a predetermined wiring pattern 62 forming a pair of positive and negative electrodes;
The ED chip 63 is provided. The substrate 61 has the shape of a thick rectangular block and has a cone-shaped concave portion whose center on the upper surface side is reduced in diameter downward.
Are extended to form a cone-shaped reflecting surface 62a. Both wiring patterns 62 extend to the bottom surface of the recess. As the material of the substrate 61 and the wiring pattern 62, the same materials as in the first embodiment can be used. The same LED chip 63 as the LED chip 16 of the first embodiment can be used.
【0049】なお、実施の形態1と同様、LEDチップ
63の下面にはAuパッド等の金属層からなる反射層6
4が、金属蒸着等により全面に形成されている。また、
LEDチップ63は、同一面側(図中下面側)に正負一
対の電極(図示略)を有し、両電極をフリップチップボ
ンディングにより基板61の両配線パターン62の先端
部にそれぞれバンプ65を介して電気的に接続するよう
になっている。バンプ65は実施の形態1のバンプ15
と同様のものを使用することができる。更に、実施の形
態6の発光ダイオードも、前記LEDチップ63の少な
くとも正負一対の電極間を封止する絶縁性のアンダーフ
ィル樹脂66を備える。前記アンダーフィル樹脂66
は、実施の形態1のアンダーフィル樹脂16と同様の材
料からなり、LEDチップ63の全周囲を覆い、かつ、
LEDチップ63の下面側と基板61の凹部の底面との
隙間を封止している。そして、実施の形態6の発光ダイ
オードは、前記反射面62aにより形成される凹部内
に、エポキシ樹脂等の注型樹脂67を充填し、発光ダイ
オード63等を封止し、保護している。As in the first embodiment, the reflection layer 6 made of a metal layer such as an Au pad is provided on the lower surface of the LED chip 63.
4 is formed on the entire surface by metal evaporation or the like. Also,
The LED chip 63 has a pair of positive and negative electrodes (not shown) on the same surface side (the lower surface side in the figure), and the both electrodes are connected to the tips of both wiring patterns 62 of the substrate 61 by bumps 65 by flip chip bonding. To be electrically connected. The bump 65 is the bump 15 of the first embodiment.
The same can be used. Further, the light emitting diode of the sixth embodiment also includes an insulating underfill resin 66 for sealing at least a pair of the positive and negative electrodes of the LED chip 63. The underfill resin 66
Is made of the same material as the underfill resin 16 of the first embodiment, covers the entire periphery of the LED chip 63, and
The gap between the lower surface side of the LED chip 63 and the bottom surface of the concave portion of the substrate 61 is sealed. In the light emitting diode according to the sixth embodiment, the recess formed by the reflection surface 62a is filled with a casting resin 67 such as an epoxy resin to seal and protect the light emitting diode 63 and the like.
【0050】次に、上記のように構成された実施の形態
6にかかる発光ダイオードの製造方法及び作用を説明す
る。Next, a method of manufacturing the light emitting diode according to the sixth embodiment configured as described above and its operation will be described.
【0051】実施の形態6の発光ダイオードは、まず、
1ショットモールド法等の通常のMID基板成形技術に
より基板61を成形し、基板61に配線パターン62を
形成する。次に、実施の形態1と同様にして、LEDチ
ップ63をバンプ65を介して配線パターン62に電気
的に接続すると共に、アンダーフィル樹脂66をLED
チップ6の下面側に充填して硬化する。その後、基板6
1の反射面62aにより形成される凹部に注型樹脂67
を充填して硬化させる。これにより、図7に示す最終製
品としてのMID発光ダイオードが形成される。The light emitting diode of Embodiment 6
The substrate 61 is molded by a normal MID substrate molding technique such as a one-shot molding method, and a wiring pattern 62 is formed on the substrate 61. Next, in the same manner as in the first embodiment, the LED chip 63 is electrically connected to the wiring pattern 62 via the bump 65, and the underfill resin 66 is
The lower surface of the chip 6 is filled and hardened. Then, the substrate 6
The casting resin 67 is provided in the recess formed by the first reflection surface 62a.
Fill and cure. Thus, an MID light emitting diode as a final product shown in FIG. 7 is formed.
【0052】このように形成した発光ダイオードは、実
施の形態1と同様の効果を発揮する。加えて、基板61
の配線パターン62の反射面62aがLEDチップ63
から側方に出射する光を上方に反射する。その結果、発
光ダイオード全体の発光効率乃至輝度を一層増大するこ
とができる。The light emitting diode thus formed exhibits the same effects as in the first embodiment. In addition, the substrate 61
The reflection surface 62a of the wiring pattern 62 of the LED chip 63
The light emitted laterally from is reflected upward. As a result, the luminous efficiency or luminance of the entire light emitting diode can be further increased.
【0053】ところで、上記実施の形態4及び5の発光
ダイオードのLEDチップ43,53は、以下の例のよ
うにして実施してもよい。The LED chips 43 and 53 of the light emitting diodes according to the fourth and fifth embodiments may be implemented as in the following example.
【0054】図9は本発明の実施の形態4にかかる発光
ダイオードのLEDチップの形状例を示す平面図であ
る。図10は図9のLEDチップを電極が位置する対角
線方向に切断して示す断面図である。FIG. 9 is a plan view showing an example of the shape of an LED chip of a light emitting diode according to Embodiment 4 of the present invention. FIG. 10 is a cross-sectional view showing the LED chip of FIG. 9 cut in a diagonal direction where electrodes are located.
【0055】この形状例は、実施の形態4のLEDチッ
プ43の具体的構成の一例を示したものであり、図9及
び10の例のLEDチップ43は、平面正方形状の半導
体部43aを備えている。半導体部43aの同一面側
(図10中上面側)の対角線方向には正負一対の電極4
3b,43cが配置される。なお、両電極43b,43
cは段差をおいて半導体部43aに配置される。電極4
3bは、その表面(図10中上面)のうち、前記電極4
3cと対角線方向反対側の一部を円形状に残して絶縁膜
43dにより被覆されている。前記円形状部は円形孔4
3eとされ、その円形孔43eから前記電極43b表面
が露出して、外部と電気的に接続自在とされている。な
お、絶縁膜43dは、電極43bの表面から側面にかけ
てその全体を被覆すると共に、電極43bに隣接する半
導体部43aの段差面(図10中垂直面)全体を被覆し
ている。これにより、絶縁膜43dは、電極43b及び
電極43c間の電気的絶縁を完全に確保している。This example of the shape shows an example of a specific configuration of the LED chip 43 of the fourth embodiment. The LED chip 43 of the examples of FIGS. 9 and 10 includes a semiconductor part 43a having a square planar shape. ing. In the diagonal direction on the same surface side (the upper surface side in FIG. 10) of the semiconductor portion 43a, a pair of positive and negative electrodes 4
3b and 43c are arranged. In addition, both electrodes 43b, 43
c is arranged in the semiconductor section 43a with a step. Electrode 4
3b is the electrode 4 of the surface (upper surface in FIG. 10).
It is covered with an insulating film 43d while leaving a part on the diagonal opposite side to 3c in a circular shape. The circular portion is a circular hole 4
3e, the surface of the electrode 43b is exposed from the circular hole 43e, and can be electrically connected to the outside. The insulating film 43d covers the entire surface from the surface to the side surface of the electrode 43b, and also covers the entire step surface (vertical surface in FIG. 10) of the semiconductor portion 43a adjacent to the electrode 43b. Thereby, the insulating film 43d completely secures electrical insulation between the electrode 43b and the electrode 43c.
【0056】実施の形態4と同様、電極43bを露出す
る円形孔43eと電極43cとの間隔は、基板41の電
極部42aの先端間の間隔と同一とされている。これに
より、LEDチップ43を、中心線を基板41の長さ方
向に延びる中心線に一致させ、基板41の中央に配置す
ることにより、LEDチップ43の電極43bの円形孔
43eからの露出部及び電極43cが、前記配線パター
ン42の両電極部42aの先端部に対向配置される。そ
して、LEDチップ43の電極43bの円形孔43eか
らの露出部及び電極43cを対応する電極部42aにバ
ンプ45を介して電気的に接続することができる。As in the fourth embodiment, the distance between the circular hole 43e exposing the electrode 43b and the electrode 43c is the same as the distance between the tips of the electrode portions 42a of the substrate 41. Thereby, by aligning the center line of the LED chip 43 with the center line extending in the length direction of the substrate 41 and disposing the LED chip 43 in the center of the substrate 41, the exposed portion of the electrode 43b of the LED chip 43 from the circular hole 43e and An electrode 43c is disposed opposite to the tip of both electrode portions 42a of the wiring pattern 42. Then, the exposed portion of the electrode 43b of the LED chip 43 from the circular hole 43e and the electrode 43c can be electrically connected to the corresponding electrode portion 42a via the bump 45.
【0057】図11は本発明の実施の形態5にかかる発
光ダイオードのLEDチップの形状例を示す平面図であ
る。図12は図11のLEDチップを電極が位置する長
さ方向に切断して示す断面図である。FIG. 11 is a plan view showing an example of the shape of the LED chip of the light emitting diode according to the fifth embodiment of the present invention. FIG. 12 is a cross-sectional view showing the LED chip of FIG. 11 cut in a length direction where electrodes are located.
【0058】この形状例は、実施の形態5のLEDチッ
プ53の具体的構成の一例を示したものであり、図11
及び12の例のLEDチップ53Aは実施の形態5のL
EDチップ53に対応するものであり、平面長方形状の
半導体部53aを備えている。半導体部53aの同一面
側(図12中上面側)の長さ方向には正負一対の電極5
3b,53cが配置される。なお、両電極53b,53
cは段差をおいて半導体部53aに配置される。電極5
3bは、その表面(図12中上面)のうち、前記電極5
3cと長さ方向反対側の一部を円形状に残して絶縁膜5
3dにより被覆されている。前記円形状部は円形孔53
eとされ、その円形孔53eから前記電極53b表面が
露出して、外部と電気的に接続自在とされている。な
お、絶縁膜53dは、電極53bの表面から側面にかけ
てその全体を被覆すると共に、電極53bに隣接する半
導体部53aの表面(図12中水平面)及び段差面(図
12中垂直面)全体を被覆している。これにより、絶縁
膜53dは、電極53b及び電極53c間の電気的絶縁
を完全に確保している。This example of the shape shows an example of a specific configuration of the LED chip 53 of the fifth embodiment.
The LED chips 53A of the examples of FIGS.
It corresponds to the ED chip 53 and includes a semiconductor part 53a having a rectangular shape in a plane. A pair of positive and negative electrodes 5 is arranged in the longitudinal direction on the same surface side (the upper surface side in FIG. 12) of the semiconductor portion 53a.
3b and 53c are arranged. In addition, both electrodes 53b, 53
c is arranged in the semiconductor section 53a with a step. Electrode 5
3b is the electrode 5 of the surface (upper surface in FIG. 12).
The insulating film 5 is formed by leaving a part on the side opposite to the longitudinal direction of the insulating film 3c in a circular shape.
Coated with 3d. The circular portion is a circular hole 53
The surface of the electrode 53b is exposed from the circular hole 53e, and is electrically connectable to the outside. The insulating film 53d covers the entire surface from the surface to the side surface of the electrode 53b, and also covers the entire surface (horizontal plane in FIG. 12) and the entire step surface (vertical plane in FIG. 12) of the semiconductor portion 53a adjacent to the electrode 53b. doing. Thus, the insulating film 53d completely secures electrical insulation between the electrode 53b and the electrode 53c.
【0059】実施の形態5と同様、電極53bを露出す
る円形孔53eと電極53cとの間隔は、基板51の電
極部52aの先端間の間隔と同一とされている。これに
より、LEDチップ53Aを、長さ方向に延びる中心線
を基板51の長さ方向に延びる中心線に一致させ、基板
51の中央に配置することにより、LEDチップ53A
の電極53bの円形孔53eからの露出部及び電極53
cが、前記配線パターン52の両電極部52aの先端部
に対向配置される。そして、LEDチップ53Aの電極
53bの円形孔53eからの露出部及び電極53cを対
応する電極部52aにバンプ55を介して電気的に接続
することができる。As in the fifth embodiment, the distance between the circular hole 53e exposing the electrode 53b and the electrode 53c is the same as the distance between the tips of the electrode portions 52a of the substrate 51. Thereby, the LED chip 53A is arranged at the center of the substrate 51 by aligning the center line extending in the length direction with the center line extending in the length direction of the substrate 51.
Exposed portion of the electrode 53b from the circular hole 53e and the electrode 53
“c” is disposed opposite to the tip of both electrode portions 52 a of the wiring pattern 52. Then, the exposed portion of the electrode 53b of the LED chip 53A from the circular hole 53e and the electrode 53c can be electrically connected to the corresponding electrode portion 52a via the bump 55.
【0060】なお、図11及び図12の例では、電極5
3cの面積が電極53bの露出部の面積に対して大き
く、電極53c及び電極53bの露出部をそれぞれ単一
のバンプ55により配線パターン52に接続すると、バ
ンプ55との電気的接続面積が異なることになる。した
がって、この場合、図11中二点鎖線で示すように、面
積の大きい方の電極53cに複数個(例えば2個)のバ
ンプ55を形成して、電極53b、53c間の電気的接
続面積の差を吸収してもよい。In the examples of FIGS. 11 and 12, the electrode 5
The area of 3c is larger than the area of the exposed portion of the electrode 53b, and when the exposed portions of the electrode 53c and the electrode 53b are connected to the wiring pattern 52 by a single bump 55, the electrical connection area with the bump 55 is different. become. Therefore, in this case, as shown by a two-dot chain line in FIG. 11, a plurality of (for example, two) bumps 55 are formed on the electrode 53c having the larger area, and the electric connection area between the electrodes 53b and 53c is reduced. The difference may be absorbed.
【0061】図13は本発明の実施の形態5にかかる発
光ダイオードのLEDチップの別の形状例を示す平面図
である。図14は図13のLEDチップを電極が位置す
る長さ方向に切断して示す断面図である。FIG. 13 is a plan view showing another example of the shape of the LED chip of the light emitting diode according to the fifth embodiment of the present invention. FIG. 14 is a cross-sectional view of the LED chip of FIG. 13 cut along a length direction where electrodes are located.
【0062】この別の形状例も、実施の形態5のLED
チップ53の具体的構成の一例を示したものであり、図
13及び14の例のLEDチップ53Bは実施の形態5
のLEDチップ53に対応するものであり、図11及び
図12の例のLEDチップ53Aとほぼ同様の構成を有
している。即ち、LEDチップ53Bは、LEDチップ
53Aと同様、半導体部53a、正負一対の電極53
b,53cを備えている。一方、LEDチップ53B
は、電極53bの露出部分(前記円形孔53e対応部
分)に円板状の介装導電材53fを載置固着している。
そして、電極53b表面(図14中上面)は、前記介装
導電材53f部分を残して絶縁膜53gにより被覆され
ている。絶縁膜53gは、前記介装導電材53fの表面
(図14中条面)の周縁部を被覆し、円形孔53hを形
成している。その円形孔53hから前記介装導電材53
f表面が露出して、外部と電気的に接続自在とされてい
る。なお、絶縁膜53gは、電極53bの表面から側面
にかけてその全体を被覆すると共に、電極53bに隣接
する半導体部53aの表面(図14中水平面)及び段差
面(図14中垂直面)全体を被覆している。これによ
り、絶縁膜53gは、電極53b及び電極53c間の電
気的絶縁を完全に確保している。Another example of the shape is also the LED of the fifth embodiment.
14 shows an example of a specific configuration of the chip 53. The LED chip 53B in the example of FIGS.
And has substantially the same configuration as the LED chip 53A of the example of FIG. 11 and FIG. That is, similarly to the LED chip 53A, the LED chip 53B includes a semiconductor portion 53a and a pair of positive and negative electrodes 53.
b, 53c. On the other hand, the LED chip 53B
The disk-shaped interposed conductive material 53f is placed and fixed on the exposed portion of the electrode 53b (the portion corresponding to the circular hole 53e).
The surface of the electrode 53b (upper surface in FIG. 14) is covered with an insulating film 53g except for the interposed conductive material 53f. The insulating film 53g covers the peripheral portion of the surface (the striation in FIG. 14) of the interposed conductive material 53f, and forms a circular hole 53h. The interposed conductive material 53 is inserted through the circular hole 53h.
The f surface is exposed, and can be electrically connected to the outside. The insulating film 53g covers the entire surface from the surface to the side surface of the electrode 53b, and also covers the entire surface (horizontal plane in FIG. 14) and the entire step surface (vertical plane in FIG. 14) of the semiconductor portion 53a adjacent to the electrode 53b. doing. Thus, the insulating film 53g completely secures electrical insulation between the electrode 53b and the electrode 53c.
【0063】実施の形態5と同様、電極53bに接続す
る介装導電材53fを露出する円形孔53hと電極53
cとの間隔は、基板51の電極部52aの先端間の間隔
と同一とされている。これにより、LEDチップ53B
を、長さ方向に延びる中心線を基板51の長さ方向に延
びる中心線に一致させ、基板51の中央に配置すること
により、LEDチップ53Bの介装導電材53fの円形
孔53hからの露出部及び電極53cが、前記配線パタ
ーン52の両電極部52aの先端部に対向配置される。
そして、LEDチップ53Bの介装導電材53fの円形
孔53hからの露出部及び電極53cを対応する電極部
52aにそれぞれバンプ55を介して電気的に接続する
ことができる。このとき、電極53bは介装導電材53
fによりバンプ55を介して対応する電極部52aに電
気的に接続される。As in the fifth embodiment, the circular hole 53h exposing the interposed conductive material 53f connected to the electrode 53b and the electrode 53
The interval between the electrodes c and c is the same as the interval between the tips of the electrode portions 52a of the substrate 51. Thereby, the LED chip 53B
The center line extending in the length direction is made coincident with the center line extending in the length direction of the substrate 51, and is disposed at the center of the substrate 51, so that the interposed conductive material 53f of the LED chip 53B is exposed from the circular hole 53h. The part and the electrode 53c are arranged to face the distal ends of both electrode parts 52a of the wiring pattern 52.
Then, the exposed portion of the interposed conductive material 53f of the LED chip 53B from the circular hole 53h and the electrode 53c can be electrically connected to the corresponding electrode portion 52a via the bump 55, respectively. At this time, the electrode 53b is
By f, it is electrically connected to the corresponding electrode part 52a via the bump 55.
【0064】なお、LEDチップ53Aの場合と同様、
電極53cの面積が介装導電材53の露出面積に対して
大きく、バンプ55との電気的接続面積が異なる場合、
図13中一点鎖線で示すように、面積の大きい方の電極
53cに複数個のバンプ55を形成してもよい。As in the case of the LED chip 53A,
When the area of the electrode 53c is larger than the exposed area of the interposed conductive material 53 and the electrical connection area with the bump 55 is different,
13, a plurality of bumps 55 may be formed on the electrode 53c having a larger area.
【0065】ところで、上記実施の形態3及び4のLE
Dチップ33,43は略矩形板状であれば良く、正方形
板状以外にも長方形板状等の形状としても良い。この場
合も、LEDチップ33,43の対角線方向に正負一対
の電極を配置するため、電極を長さ方向に配置する場合
より電極間ピッチを大きく取ることができ、同様の効果
がある。Incidentally, the LEs of the third and fourth embodiments are used.
The D chips 33 and 43 may have a substantially rectangular plate shape, and may have a rectangular plate shape or the like other than the square plate shape. Also in this case, since the pair of positive and negative electrodes is arranged in the diagonal direction of the LED chips 33 and 43, the pitch between the electrodes can be made larger than when the electrodes are arranged in the length direction, and the same effect is obtained.
【0066】また、実施の形態6の発光ダイオードは、
実施の形態2と同様、LEDチップ63の下面側に、ア
ンダーフィル樹脂66に代えて異方導電性ぺースト21
を充填し、同様の効果を付与しても良い。また、実施の
形態6の発光ダイオードは、実施の形態3乃至5のいず
れかと組み合わせて実施しても良い。例えば、実施の形
態3または4のように、発光ダイオード63の対角線方
向に正負一対の電極を配置し、配線パターン62のパタ
ーン形状(特に電極部32a,42aに対応する先端部
形状)を実施の形態3または4のようにし、LEDチッ
プ63の両電極間の電気的絶縁を確保し、動作信頼性を
一層向上してもよい。或いは、実施の形態5のように、
発光ダイオード63を長方形板状として、同様に動作信
頼性を向上しても良い。The light emitting diode of the sixth embodiment is
As in the second embodiment, the anisotropic conductive paste 21 is provided on the lower surface side of the LED chip 63 instead of the underfill resin 66.
And the same effect may be imparted. Further, the light emitting diode of Embodiment 6 may be implemented in combination with any of Embodiments 3 to 5. For example, as in the third or fourth embodiment, a pair of positive and negative electrodes are arranged in a diagonal direction of the light emitting diode 63, and the pattern shape of the wiring pattern 62 (particularly, the tip shape corresponding to the electrode portions 32a and 42a) is implemented. As in the form 3 or 4, electrical insulation between both electrodes of the LED chip 63 may be ensured to further improve operation reliability. Alternatively, as in Embodiment 5,
The light emitting diode 63 may have a rectangular plate shape to similarly improve the operation reliability.
【0067】[0067]
【発明の効果】以上のように、請求項1の発光ダイオー
ドは、一対の配線パターンを有する基板と、同一面側に
正負一対の電極を有し、前記両電極を前記基板の両配線
パターンにそれぞれバンプを介して電気的に接続したL
EDチップとを具備する。As described above, the light-emitting diode according to the first aspect of the present invention has a substrate having a pair of wiring patterns and a pair of positive and negative electrodes on the same surface side, and the two electrodes are connected to both wiring patterns of the substrate. L electrically connected via each bump
An ED chip.
【0068】したがって、LEDチップの正負一対の電
極が光出射面と反対側の下面側に位置するため、光出射
面である上面に光を遮る影となるものが何もなく、LE
Dチップの上面全体が発光面積となる。その結果、LE
Dチップからの光の取り出し効率を増大して、発光効率
乃至輝度を向上することができる。また、LEDチップ
の両電極と基板の両配線パターンとの電気的接続をバン
プを介したフリップチップボンディングにより行うた
め、従来のようなワイヤボンディング用のスペースが不
要となり、発光ダイオード全体を小型化することができ
る。更に、LEDチップの両電極を直接基板の両配線パ
ターンに接続することができるため、LEDチップ駆動
時の放熱性が向上し、発光ダイオードの信頼性及び耐久
性が向上する。Therefore, since the pair of positive and negative electrodes of the LED chip are located on the lower surface opposite to the light emitting surface, there is no shadow on the upper surface, which is the light emitting surface, to block the light.
The entire upper surface of the D chip is a light emitting area. As a result, LE
The light extraction efficiency from the D chip can be increased, and the luminous efficiency or luminance can be improved. Further, since electrical connection between both electrodes of the LED chip and both wiring patterns of the substrate is performed by flip-chip bonding via bumps, a space for wire bonding as in the related art is unnecessary, and the entire light emitting diode can be miniaturized. be able to. Furthermore, since both electrodes of the LED chip can be directly connected to both wiring patterns of the substrate, the heat dissipation during driving of the LED chip is improved, and the reliability and durability of the light emitting diode are improved.
【0069】請求項2の発光ダイオードは、一対の配線
パターンを有する基板と、同一面側に正負一対の電極を
有し、前記両電極を前記基板の両配線パターンにそれぞ
れバンプを介して電気的に接続したLEDチップと、前
記LEDチップの少なくとも両電極間を封止する電気絶
縁性のアンダーフィル樹脂とを具備する。According to a second aspect of the present invention, there is provided a light emitting diode having a substrate having a pair of wiring patterns and a pair of positive and negative electrodes on the same surface side, wherein both electrodes are electrically connected to both wiring patterns of the substrate via bumps. And an electrically insulating underfill resin for sealing between at least both electrodes of the LED chip.
【0070】したがって、LEDチップの正負一対の電
極が光出射面と反対側の下面側に位置するため、光出射
面である上面に光を遮る影となるものが何もなく、LE
Dチップの上面全体が発光面積となる。その結果、LE
Dチップからの光の取り出し効率を増大して、発光効率
乃至輝度を向上することができる。また、LEDチップ
の両電極と基板の両配線パターンとの電気的接続をバン
プを介したフリップチップボンディングにより行うた
め、従来のようなワイヤボンディング用のスペースが不
要となり、発光ダイオード全体を小型化することができ
る。更に、LEDチップの両電極を直接基板の両配線パ
ターンに接続することができるため、LEDチップ駆動
時の放熱性が向上し、発光ダイオードの信頼性及び耐久
性が向上する。加えて、アンダーフィル樹脂によりLE
Dチップの両電極間の電気的絶縁が確保され、動作信頼
性が向上する。Therefore, since the pair of positive and negative electrodes of the LED chip is located on the lower surface side opposite to the light emitting surface, there is no shadow on the upper surface, which is the light emitting surface, and there is no shadow.
The entire upper surface of the D chip is a light emitting area. As a result, LE
The light extraction efficiency from the D chip can be increased, and the luminous efficiency or luminance can be improved. Further, since electrical connection between both electrodes of the LED chip and both wiring patterns of the substrate is performed by flip-chip bonding via bumps, a space for wire bonding as in the related art is unnecessary, and the entire light emitting diode can be miniaturized. be able to. Furthermore, since both electrodes of the LED chip can be directly connected to both wiring patterns of the substrate, the heat dissipation during driving of the LED chip is improved, and the reliability and durability of the light emitting diode are improved. In addition, LE with underfill resin
Electrical insulation between both electrodes of the D chip is ensured, and operation reliability is improved.
【0071】請求項3の発光ダイオードは、一対の配線
パターンを有する基板と、同一面側に正負一対の電極を
有し、前記両電極を前記基板の両配線パターンにそれぞ
れバンプを介して電気的に接続したLEDチップと、前
記LEDチップの少なくとも両電極間を封止する異方導
電性ペーストとを具備する。A light emitting diode according to a third aspect of the present invention has a substrate having a pair of wiring patterns and a pair of positive and negative electrodes on the same surface side, and the two electrodes are electrically connected to both wiring patterns of the substrate via bumps. And an anisotropic conductive paste for sealing at least between both electrodes of the LED chip.
【0072】したがって、LEDチップの正負一対の電
極が光出射面と反対側の下面側に位置するため、光出射
面である上面に光を遮る影となるものが何もなく、LE
Dチップの上面全体が発光面積となる。その結果、LE
Dチップからの光の取り出し効率を増大して、発光効率
乃至輝度を向上することができる。また、LEDチップ
の両電極と基板の両配線パターンとの電気的接続をバン
プを介したフリップチップボンディングにより行うた
め、従来のようなワイヤボンディング用のスペースが不
要となり、発光ダイオード全体を小型化することができ
る。更に、LEDチップの両電極を直接基板の両配線パ
ターンに接続することができるため、LEDチップ駆動
時の放熱性が向上し、発光ダイオードの信頼性及び耐久
性が向上する。加えて、異方導電性ペーストによりLE
Dチップの両電極間の電気的絶縁が確保されると共に、
LEDチップの電極と対応する基板の配線パターンとの
電気的導通が確保される。その結果、発光ダイオードの
動作信頼性が一層向上する。Therefore, since the pair of positive and negative electrodes of the LED chip are located on the lower surface side opposite to the light emitting surface, there is no shadow on the upper surface, which is the light emitting surface, and there is no shadow.
The entire upper surface of the D chip is a light emitting area. As a result, LE
The light extraction efficiency from the D chip can be increased, and the luminous efficiency or luminance can be improved. Further, since electrical connection between both electrodes of the LED chip and both wiring patterns of the substrate is performed by flip-chip bonding via bumps, a space for wire bonding as in the related art is unnecessary, and the entire light emitting diode can be miniaturized. be able to. Furthermore, since both electrodes of the LED chip can be directly connected to both wiring patterns of the substrate, the heat dissipation during driving of the LED chip is improved, and the reliability and durability of the light emitting diode are improved. In addition, LE with anisotropic conductive paste
While ensuring electrical insulation between both electrodes of the D chip,
Electrical conduction between the electrodes of the LED chips and the corresponding wiring patterns on the substrate is ensured. As a result, the operation reliability of the light emitting diode is further improved.
【0073】請求項4の発光ダイオードは、請求項1乃
至請求項3のいずれかの構成において、前記基板の配線
パターンは、基板の長さ方向に間隔を置いて対向配置さ
れる電極部を有し、前記LEDチップは略矩形板状をな
すと共にその対角線方向に前記正負一対の電極を配置
し、前記正負一対の電極を前記配線パターンの両電極部
に対向配置して電気的に接続するものである。According to a fourth aspect of the present invention, in the light-emitting diode according to any one of the first to third aspects, the wiring pattern of the substrate has an electrode portion which is opposed to the substrate at an interval in the length direction of the substrate. The LED chip has a substantially rectangular plate shape and the pair of positive and negative electrodes are arranged in a diagonal direction of the LED chip, and the pair of positive and negative electrodes are disposed opposite to and electrically connected to both electrode portions of the wiring pattern. It is.
【0074】したがって、請求項1乃至請求項3のいず
れかの効果に加えて、LEDチップの電極間ピッチがよ
り大きくなる。その結果、電極間での短絡を効果的に防
止して、発光ダイオードの動作信頼性をより向上し、製
品品質を一層向上することができる。Therefore, in addition to the effect of any one of the first to third aspects, the pitch between the electrodes of the LED chip becomes larger. As a result, a short circuit between the electrodes can be effectively prevented, the operation reliability of the light emitting diode can be further improved, and the product quality can be further improved.
【0075】請求項5の発光ダイオードは、請求項1乃
至請求項3のいずれかの構成において、前記基板の配線
パターンは、基板の長さ方向と傾斜する方向に間隔を置
いて対向配置される電極部を有し、前記LEDチップは
略矩形板状をなすと共にその対角線方向に前記正負一対
の電極を配置し、前記正負一対の電極を前記配線パター
ンの電極部に対向配置して電気的に接続するものであ
る。According to a fifth aspect of the present invention, in the light emitting diode according to any one of the first to third aspects, the wiring pattern of the substrate is opposed to the wiring pattern at an interval in a direction inclined with the length direction of the substrate. The LED chip has a substantially rectangular plate shape, and the pair of positive and negative electrodes is arranged in a diagonal direction of the LED chip. Connect.
【0076】したがって、請求項1乃至請求項3のいず
れかの効果に加えて、LEDチップの電極間ピッチがよ
り大きくなる。その結果、電極間での短絡を効果的に防
止して、発光ダイオードの動作信頼性をより向上し、製
品品質を一層向上することができる。更に、配線パター
ンのパターン形状を変更するだけで、LEDチップを基
板に通常状態(中心線を一致させた状態)で配置するこ
とができる。その結果、LEDチップの位置決め乃至配
置作業を通常の方法で行うことができる。Therefore, in addition to the effect of any one of the first to third aspects, the pitch between the electrodes of the LED chip becomes larger. As a result, a short circuit between the electrodes can be effectively prevented, the operation reliability of the light emitting diode can be further improved, and the product quality can be further improved. Further, the LED chip can be arranged on the substrate in a normal state (a state in which the center lines are aligned) only by changing the pattern shape of the wiring pattern. As a result, the operation of positioning or arranging the LED chips can be performed by a normal method.
【0077】請求項6の発光ダイオードは、請求項1乃
至請求項3のいずれかの構成において、前記基板の配線
パターンは、基板の長さ方向に間隔を置いて対向配置さ
れる電極部を有し、前記LEDチップは略長方形板状を
なすと共にその長さ方向に前記正負一対の電極を配置
し、前記正負一対の電極を前記配線パターンの電極部に
対向配置して電気的に接続するものである。According to a sixth aspect of the present invention, in the light emitting diode according to any one of the first to third aspects, the wiring pattern of the substrate has an electrode portion opposed to the substrate at an interval in the length direction of the substrate. The LED chip has a substantially rectangular plate shape, and the pair of positive and negative electrodes is disposed in the length direction thereof, and the pair of positive and negative electrodes is disposed opposite to the electrode portion of the wiring pattern to be electrically connected. It is.
【0078】したがって、請求項1乃至請求項3のいず
れかの効果に加えて、LEDチップの電極間ピッチがよ
り大きくなる。その結果、電極間での短絡を効果的に防
止して、発光ダイオードの動作信頼性をより向上し、製
品品質を一層向上することができる。Therefore, in addition to the effects of any one of the first to third aspects, the pitch between the electrodes of the LED chip becomes larger. As a result, a short circuit between the electrodes can be effectively prevented, the operation reliability of the light emitting diode can be further improved, and the product quality can be further improved.
【0079】請求項7の発光ダイオードは、請求項1乃
至請求項6のいずれかの構成において、前記基板をMI
D基板としたものである。したがって、請求項1乃至請
求項6のいずれかの効果に加えて、基板の配線パターン
がLEDチップから側方に出射する光を上方に反射す
る。その結果、発光ダイオード全体の発光効率乃至輝度
を一層増大することができる。According to a seventh aspect of the present invention, in the light emitting diode according to any one of the first to sixth aspects, the substrate is provided with an MI.
This is a D substrate. Therefore, in addition to the effect of any one of the first to sixth aspects, the wiring pattern of the substrate reflects upwardly light emitted laterally from the LED chip. As a result, the luminous efficiency or luminance of the entire light emitting diode can be further increased.
【図1】 図1は本発明の実施の形態1における発光ダ
イオードの全体構成を示す断面図である。FIG. 1 is a cross-sectional view illustrating an overall configuration of a light emitting diode according to Embodiment 1 of the present invention.
【図2】 図2は本発明の実施の形態1における発光ダ
イオードの要部を示す断面図である。FIG. 2 is a cross-sectional view illustrating a main part of the light-emitting diode according to Embodiment 1 of the present invention.
【図3】 図3は本発明の実施の形態2における発光ダ
イオードの要部を示す断面図である。FIG. 3 is a sectional view showing a main part of a light emitting diode according to a second embodiment of the present invention.
【図4】 図4は本発明の実施の形態3における発光ダ
イオードの平面図である。FIG. 4 is a plan view of a light emitting diode according to Embodiment 3 of the present invention.
【図5】 図5は本発明の実施の形態4における発光ダ
イオードの平面図である。FIG. 5 is a plan view of a light emitting diode according to Embodiment 4 of the present invention.
【図6】 図6は本発明の実施の形態5における発光ダ
イオードの平面図である。FIG. 6 is a plan view of a light emitting diode according to a fifth embodiment of the present invention.
【図7】 図7は本発明の実施の形態6における発光ダ
イオードの断面図である。FIG. 7 is a sectional view of a light emitting diode according to a sixth embodiment of the present invention.
【図8】 図8は特開平9−135040号公報に掲載
の発光ダイオードを示す断面図である。FIG. 8 is a sectional view showing a light emitting diode disclosed in Japanese Patent Application Laid-Open No. Hei 9-135040.
【図9】 図9は本発明の実施の形態4にかかる発光ダ
イオードのLEDチップの形状例を示す平面図である。FIG. 9 is a plan view showing a shape example of an LED chip of a light emitting diode according to a fourth embodiment of the present invention.
【図10】 図10は図9のLEDチップを電極が位置
する対角線方向に切断して示す断面図である。FIG. 10 is a cross-sectional view showing the LED chip of FIG. 9 cut in a diagonal direction where electrodes are located.
【図11】 図11は本発明の実施の形態5にかかる発
光ダイオードのLEDチップの形状例を示す平面図であ
る。FIG. 11 is a plan view showing a shape example of an LED chip of a light emitting diode according to a fifth embodiment of the present invention.
【図12】 図12は図11のLEDチップを電極が位
置する長さ方向に切断して示す断面図である。FIG. 12 is a cross-sectional view of the LED chip of FIG. 11 cut along a length direction where electrodes are located.
【図13】 図13は本発明の実施の形態5にかかる発
光ダイオードのLEDチップの別の形状例を示す平面図
である。FIG. 13 is a plan view showing another example of the shape of the LED chip of the light emitting diode according to the fifth embodiment of the present invention.
【図14】 図14は図13のLEDチップを電極が位
置する長さ方向に切断して示す断面図である。FIG. 14 is a cross-sectional view showing the LED chip of FIG. 13 cut along a length direction where electrodes are located.
11,31,41,51,61、 基板 12,32,42,52,62 配線パターン 13,33,43,53,53A,53B,63 L
EDチップ 15,35,45,55,65 バンプ 16 アンダーフィル樹脂 21 異方導電性ペースト 32a,42a,52a 電極部11, 31, 41, 51, 61, substrate 12, 32, 42, 52, 62 wiring pattern 13, 33, 43, 53, 53A, 53B, 63L
ED chip 15, 35, 45, 55, 65 Bump 16 Underfill resin 21 Anisotropic conductive paste 32a, 42a, 52a Electrode
───────────────────────────────────────────────────── フロントページの続き (72)発明者 上村 俊也 愛知県西春日井郡春日町大字落合字長畑1 番地 豊田合成株式会社内 (72)発明者 高橋 祐次 愛知県西春日井郡春日町大字落合字長畑1 番地 豊田合成株式会社内 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Toshiya Uemura 1 Ochiai Nagahata, Kasuga-cho, Nishi-Kasugai-gun, Aichi Prefecture Inside Toyota Gosei Co., Ltd. Toyoda Gosei Co., Ltd.
Claims (7)
板の両配線パターンにそれぞれバンプを介して電気的に
接続したLEDチップとを具備することを特徴とする発
光ダイオード。1. A substrate having a pair of wiring patterns, and an LED chip having a pair of positive and negative electrodes on the same surface side, wherein both electrodes are electrically connected to both wiring patterns of the substrate via bumps, respectively. A light-emitting diode comprising:
板の両配線パターンにそれぞれバンプを介して電気的に
接続したLEDチップと、 前記LEDチップの少なくとも両電極間を封止する電気
絶縁性のアンダーフィル樹脂とを具備することを特徴と
する発光ダイオード。2. A substrate having a pair of wiring patterns, and an LED chip having a pair of positive and negative electrodes on the same surface side and electrically connecting both electrodes to both wiring patterns of the substrate via bumps, respectively. A light-emitting diode, comprising: an electrically insulating underfill resin that seals at least between both electrodes of the LED chip.
板の両配線パターンにそれぞれバンプを介して電気的に
接続したLEDチップと、 前記LEDチップの少なくとも両電極間を封止する異方
導電性ペーストとを具備することを特徴とする発光ダイ
オード。3. A substrate having a pair of wiring patterns, and an LED chip having a pair of positive and negative electrodes on the same surface side and electrically connecting both electrodes to both wiring patterns of the substrate via bumps, respectively. A light-emitting diode, comprising: an anisotropic conductive paste for sealing at least between both electrodes of the LED chip.
方向に間隔を置いて対向配置される電極部を有し、前記
LEDチップは略矩形板状をなすと共にその対角線方向
に前記正負一対の電極を配置し、前記正負一対の電極を
前記配線パターンの両電極部に対向配置して電気的に接
続することを特徴とする請求項1乃至請求項3のいずれ
か1つの請求項に記載の発光ダイオード。4. The wiring pattern of the substrate has electrode portions which are opposed to each other at intervals in the longitudinal direction of the substrate, and the LED chip has a substantially rectangular plate shape and the pair of positive and negative electrodes is arranged diagonally. 4. The electrode according to claim 1, wherein the pair of positive and negative electrodes are disposed so as to be opposed to both electrode portions of the wiring pattern and are electrically connected to each other. 5. Light emitting diode.
方向と傾斜する方向に間隔を置いて対向配置される電極
部を有し、前記LEDチップは略矩形板状をなすと共に
その対角線方向に前記正負一対の電極を配置し、前記正
負一対の電極を前記配線パターンの電極部に対向配置し
て電気的に接続することを特徴とする請求項1乃至請求
項3のいずれか1つの請求項に記載の発光ダイオード。5. The wiring pattern of the substrate has electrode portions that are opposed to each other at intervals in a direction oblique to the length direction of the substrate, and the LED chip has a substantially rectangular plate shape and a diagonal direction thereof. 4. The method according to claim 1, wherein the pair of positive and negative electrodes is disposed on the first electrode, and the pair of positive and negative electrodes are disposed opposite to the electrode portion of the wiring pattern to be electrically connected. A light-emitting diode according to the item.
方向に間隔を置いて対向配置される電極部を有し、前記
LEDチップは略長方形板状をなすと共にその長さ方向
に前記正負一対の電極を配置し、前記正負一対の電極を
前記配線パターンの電極部に対向配置して電気的に接続
することを特徴とする請求項1乃至請求項3のいずれか
1つの請求項に記載の発光ダイオード。6. The wiring pattern of the substrate has electrode portions which are opposed to each other at intervals in the length direction of the substrate, and the LED chip has a substantially rectangular plate shape and the positive and negative electrodes are arranged in the length direction. 4. The device according to claim 1, wherein a pair of electrodes are disposed, and the pair of positive and negative electrodes are disposed to face and electrically connect to the electrode portion of the wiring pattern. 5. Light emitting diode.
とする請求項1乃至請求項6のいずれか1つの請求項に
記載の発光ダイオード。7. The light emitting diode according to claim 1, wherein the substrate is an MID substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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JP33539097A JPH11168235A (en) | 1997-12-05 | 1997-12-05 | Light emitting diode |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP33539097A JPH11168235A (en) | 1997-12-05 | 1997-12-05 | Light emitting diode |
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JPH11168235A true JPH11168235A (en) | 1999-06-22 |
Family
ID=18288015
Family Applications (1)
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JP33539097A Pending JPH11168235A (en) | 1997-12-05 | 1997-12-05 | Light emitting diode |
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