JPH11167081A - Variable frequency pixel clock - Google Patents

Abstract

PROBLEM TO BE SOLVED: To correct pixel intervals and the expansion of pixel spot by an inexpensive means. SOLUTION: The variable frequency pixel clock, constituted having a direct digital synthesizer 70, a reference table 60 which gives frequency information to the direct digital synthesizer 70, a 1st oscillator which supplies a reference signal to the direct digital synthesizer 70, and counters 52 and 53 which supplies position information showing the position of a beam along a scanning line to the reference table 60 and generating a series of frequencies programmed so as to compensate variation in beam speed along a scanning line, outputs an output signal having a frequency corresponding to the beam position by the direct digital synthesizer 70.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency-variable pixel clock, and more particularly to a frequency-variable pixel clock used in a high-speed digital photo manufacturing (photo finishing) apparatus. REFERENCE TO RELATED APPLICATIONS: This patent application was filed by William R. Markis on April 21, 1997, and describes an oscillator system with a correction frequency modulation mechanism (OSCIL-LATOR).
SYSTEM WITH CORRECTIVE FREQUENCY MODULATION), a related application to US patent application Ser. No. 08 / 837,633.

[0002]

2. Description of the Related Art In a high-speed digital photograph manufacturing apparatus, a three-color laser scanner is used, and a scanned image is taken into a memory by the laser scanner, thereby enabling image processing. Finally, a hard copy printout is produced on the photosensitive receiving medium. FIG. 1 shows three laser sources 12, 13 and 13 emitting red, green and blue rays, respectively.
A system 10 is shown comprising The laser beam is directed to acousto-optic modulators 16, 17, and 1 respectively controlled by a pixel data stream output from printer circuit 20 tuned to pixel clock signal 22.
Go through 8. The laser beams obtained from the three acousto-optic modulators are optically combined by a combiner 24 and focused on a rotating polygon mirror 26. Then, the laser beam is changed to f-θ by the polygon mirror.
The web 30 is scanned through a lens 30 onto a web-like receiving medium 28 to form a print line.

[0003] The devices used to scan the beam can take various forms. FIG. 1 shows a polygon scanner composed of a mirror having a polygonal shape that rotates many times per second. Polygon scanners have wobble, pyramid error,
And various functional limitations such as non-linear spot speed. Other types of mirror scanners include linear, ramp-driven galvanometers.
r) is raised. This device consists of a single mirror located near the center of rotation. This type of mirror scanner minimizes the sway associated with polygon scanners, but has the disadvantage of being a reciprocating device and of low speed. As a third type of mirror scanner,
Resonant scanner is raised. The resonance scanner comprises a mirror on a curved member driven by a sinusoidal electrical signal to oscillate at the mechanical resonance frequency of the member itself. These devices have the advantages of a linear, galvanometer driven in the form of a ramp and have a scanning speed equal to or higher than that of a polygon mirror. However, since the rotational speed of the resonance scanner changes, the scanning speed is given an angular speed that varies sinusoidally according to the position where the laser beam is scanned. By changing the scanning speed of the laser beam in this manner, the pixel interval changes non-linearly as shown in FIG. At both ends of the scanning line, the pixel interval is narrower than at the center of the scanning line. Such a problem of the pixel interval similarly occurs in the polygon scanner.

[0004] In the f-θ lens, lens distortion is used to realize a pixel arrangement that is directly given at a certain angle during a predetermined period during which an input beam is scanned. Therefore, the pixel spacing problem associated with resonance scanners involves the function of an f-theta lens as an element. Further, since the f-θ lens 30 has a different effect on light beams having different wavelengths, the three laser beams output from the acousto-optic modulators 16, 17, and 18 are respectively changed to the receiving medium 28.
The apparent scanning speed across the top will be different from the apparent scanning speed of the other beams. Another problem with the polygon scanner is that, as shown in FIG. 3, pixels of different sizes are formed along the scanning line due to a change in speed according to the position on the scanning line. The difference in apparent scan speed along the scan line is between 8% and 1%.
May reach 1%.

[0005] By adjusting the output speed of the crystal oscillator,
Attempts have been made to compensate for apparent scanning speed differences between the beams. Crystal oscillators have an output frequency that is stable over time and temperature, making them unsuitable for applications requiring a frequency change of more than 1/2%. Therefore, as described above, 8% to 11%
The application of a crystal oscillator alone is not sufficient to provide compensation for scan speeds that produce as much as a% difference.

An oscillator having a stable frequency is formed using a phase locked loop. The phase-locked loop includes a reference oscillator, a voltage-controlled variable frequency oscillator, and a frequency divider (frequency divider) for adjusting the output frequency of the variable frequency oscillator so as to be substantially equal to the output frequency of the reference oscillator. And a phase comparator for comparing the phase of the output of the reference oscillator with the phase of the output of the variable frequency oscillator. The variable frequency oscillator is controlled according to the comparison output of the phase comparator. When the frequency divider or the frequency divider (frequency multiplier) is fixed, the frequency of the frequency variable oscillator is locked, so that a signal having a desired frequency can be reliably obtained.

In the oscillator according to the related art having the above-described lock mechanism, it is possible to change the frequency at which the frequency variable oscillator is locked by changing the division ratio of the frequency divider. However, if the desired frequency at which the tunable oscillator should be locked is relatively large compared to the output frequency of the reference oscillator, and thus the output frequency of the tunable oscillator needs to be divided by a large number, Response time becomes undesirably long. When the response time of the frequency divider becomes longer, the frequency lock function of the variable frequency oscillator becomes unstable, and the response speed becomes slower.

[0008] One attempt to solve the above problem by changing the pixel clock having an oscillator system with a correcting frequency modulation function is disclosed in a pending patent application.
As described in 8 / 837,633, this attempt has been somewhat successful. However, the above solution requires device setup and hardware alignment to avoid positioning problems.

The problem of pixel spacing and pixel expansion (pixel gr
Other means of correcting the owth) problem include the use of f-theta lenses designed to correct these problems. However, this solution is expensive since complex lenses require as many as seven components and are very expensive.

It is an object of the present invention to provide an improved pixel clock which eliminates the above-mentioned disadvantages inherent in the prior art pixel clock. Another object of the present invention is to implement correction of pixel spacing and correction of extension of a pixel spot by inexpensive means.

[0011]

SUMMARY OF THE INVENTION The present invention has a long-term average accuracy close to that of a crystal oscillator, and has a function of changing the frequency a plurality of times within a scan line based on a predetermined function. An oscillator circuit is provided.

In accordance with one aspect of the present invention, a series of pre-programmed frequencies is provided by a frequency variable pixel clock to compensate for beam speed variations along a scan line. The pixel clock is a direct digital synthesizer (direct digital synthesizer),
It has a reference table for giving frequency information to the direct digital synthesizer, and a first oscillator for giving a reference signal to the direct digital synthesizer. The counter gives information indicating the position of the beam on the scanning line to the lookup table. Then, an output signal having a frequency corresponding to the position of the beam is output by the direct digital synthesizer.

According to another feature of the present invention, a pixel clock signal is output from the frequency variable pixel clock circuit to an image scanner to control the pixel speed at various writing locations along the scan line. You. This circuit is a direct digital synthesizer,
A reference table for providing frequency information to the direct digital synthesizer. A reference signal is provided to the direct digital synthesizer by the first oscillator, and information indicating a beam position on a scanning line is provided to a lookup table by a counter. And
An output signal corresponding to the position of the beam is output by the direct digital synthesizer. The contents, objects and advantages of the present invention will become more apparent from the following detailed description of preferred embodiments of the present invention.

[0014]

BRIEF DESCRIPTION OF THE DRAWINGS In the following detailed description of the preferred embodiments of the invention, reference is made to the accompanying drawings. FIG. 1 is a schematic diagram showing a laser printer in which an oscillator system according to the present invention is used. FIG. 2 is a graph showing pixel intervals formed on an image plane by a resonance scanner when the pixel clock is not corrected. FIG. 3 is a graph showing pixel extension given as a function of position on a scan line in a system without correction for a polygon scanner. FIG. 4 is a schematic diagram showing a three-color laser writer according to the present invention. FIG. 5 is a block diagram showing an oscillator system according to a preferred embodiment of the present invention. FIG.
FIG. 5 is a diagram showing timings for loading to a direct digital synthesizer. FIG. 7 shows a lookup table (LU
It is a figure which shows some frequency correction values loaded in T). FIG. 8 is a graph showing the relationship between frequency and time for the pixel clock signal for the red, green, and blue channels, respectively.

In the following, in particular, elements which form part of the device according to the invention or which cooperate directly with the device according to the invention will be described. It will be understood that elements not specifically shown or described may take various forms well known to those skilled in the art. In the following, the present invention will be described on the assumption that the present invention is applied to a three-color scanning laser system used in a high-speed digital photograph manufacturing apparatus. However, the present invention is applicable to other systems using a frequency variable pixel clock. It should be noted that it is applicable.

FIG. 4 shows a three-color laser writer 11 according to the present invention. The red laser 12, the green laser 13, and the blue laser 14 are in a gas state or a solid state, respectively. Each laser has
A coupling 34 consisting of a coupler and an optical fiber is mounted, which allows the laser to be located at a remote location. The acousto-optic modulators 16 and 1 to which a signal is input from the printer circuit 20 by a coupler and an optical fiber
The laser beam is directed to 7 and 18. Continuous pixel data is applied to each line, and all three colors are written simultaneously. Thereafter, the individual beams are introduced into a beam combiner 39 comprising a fold mirror 38 and a prism 40. The combined beam is applied to a collimating lens (co
The light passes through an llimating lens 42 and a fold mirror 38 and is directed to a resonance scanner 44. The resonance scanner 44 scans the combined beam with a sinusoidally varying velocity. And the combined beam is f-
is introduced into the θ lens 30. With this f-θ lens 30, all three colors are focused on the film phase drum 46.

FIG. 5 shows a single channel 45 of the frequency variable pixel clock 23 in a multi-channel three-color system.
It is shown. Since blocks 51, 52, 53, 54 and 55 make up the timing of the system, these blocks are therefore common in all channels and will be described in detail below.

The preferred embodiment is constructed with a direct digital synthesizer (DDS) 70, and particularly for this device, timing and loading.
Needs to be set in detail. One such direct digital synthesizer is manufactured by Analog Devices as part number AD9850DDS. This type of device requires a master clock 55 that provides a timing signal that can be used to tune the output signal 22 to various frequencies. Master clock 5
An oscillator 5 oscillates at an arbitrary frequency up to 125 MHz.

To set the output frequency from the DDS 70, a 5-byte adjustment word is sent from the LUT 60 to the DDS 70. The code in byte units is sent from the LUT 60 to the DDS 70 one byte at a time via the 8-bit bus 68. The transfer clock signal (W_CLK) is sent from the logic circuit 54 to the DDS, and each bytecode is timed and input by this signal, and the internal register of the DDS is advanced to input the next bytecode. Further, an internal transfer clock signal (FQ_U), which is another signal input from the logic circuit 54,
D) causes all five bytes of code to be transferred internally to other registers within DDS 70, and the register pointer for the next five bytes to be reset. FIG. 6 shows the load timing when the above-described processing is performed on the DDS.

The LUT 60 is set such that the lower three sets of address lines formed by the byte counter 53 controlling eight addresses are always active. As a result, new data is continuously transmitted to DDS7.
0 is transferred. When the lower three address bits in the byte counter 53 wrap around to zero,
The count of the position counter 52, which is a 12-bit counter, is advanced by one. As a result, the address of the upper 12 bits of the LUT is changed so as to indicate a new 5-byte code. Here, the LUT 60 generates an 8-byte code for every position, while the DDS 70 only accepts a 5-byte code for each update, and the last 3
Note that bytes are ignored.

Stated another way, the loading procedure for LUT 60 is implemented using two counters 52,53. The byte counter 53 is in a free running state, whereby the address of the LUT circulates constantly between codes within a 3-bit range. When the byte counter 53 wraps around 000, the count of the position counter 52 advances by one.
As a result, eight new addresses are generated for the next cycle of the byte counter 53. The LUT 60 is updated with this new address, and 5 bytes in the code contain valid data. Since a code different from the code of the previous address can be set in these new addresses, different frequencies can be output. Until the active scan line reaches its end, the position counter 52 continues counting as described above. The position counter 52 is then reset to zero at the end of the active scan line and maintains its value at zero until it receives a line start signal 56 indicating the beginning of a new line. Upon receiving the line start signal, the position counter 52 can count again. The frequency update signal FQ_UD (T) is tuned to the wraparound of the byte counter 53, so that the bytecode is transferred in an appropriate order.

The LUT 60 is loaded with a code for generating an appropriate frequency corresponding to the scanning line position when sent to the DDS 70. Typically, the code is loaded into a look-up table (LUT) 60 using a bus separator 64 by a computer not shown.

Since the counting of the position counter 52 is controlled by the line start signal 56 of the system, position accuracy is assured. Scan image processing system (scan ima
In the field of ging systems, it is necessary to synchronize the pixel clock to a spatial position on a scan line.
Usually, such a synchronization step is realized by a "line start" signal generated by a scanning beam passing through a fixed detector. This establishes a precise relationship between the data transfer function over time and the physical scan function over space for each scan line. Various methods are already known for the configuration of the oscillator synchronized with the scanning start signal.

The position counter 52 outputs the position clock 51
The selection of the frequency of the position clock is not limited because it is advanced by one for each cycle. However, in order to facilitate the generation of the pattern of the lookup table, the average value of the output of the frequency-variable pixel clock 23 is fixed. Need to have a relationship. In one embodiment of the system, the nominal frequency of the pixel clock is close to 14 MHz, so that the frequency of the position clock is 14 MHz or 28 MHz.
z is preferred. This makes it possible to generate a new frequency every eight pixels or every four pixels. In addition, the logical block 54 allows the LUT 6
0 and all of the required timing signals in the DDS 70 are provided.

In operation of the device, the appropriate numbers required to generate the desired set of frequencies are loaded into the LUT 60 by the host computer. FIG. 7 shows a part of a set of frequencies used in the operation test. FIG. 8 shows red, green,
For a blue laser beam and a blue laser beam, a graph showing the relationship between frequency and time given by a frequency variable pixel clock in an operation test is shown.

The output from DDS 70 is provided as a cosine wave having the desired frequency to modify the pixel spacing along the scan line. The cosine wave signal 71 is then passed through a low pass filter 72 to form a clock edge used in a digital system. This filter removes most digital sampling noise from the signal. Thereafter, the filtered signal is passed through an internal comparator in the DDS 70 to be converted into a square wave. This rectangular wave becomes the pixel clock signal 22 sent to the printing system.

Although the present invention has been described in detail herein with particular reference to certain preferred embodiments,
It will be understood that various changes and modifications are possible within the spirit and scope of the invention. For example, while the above embodiments are directed to a resonance scanner, the present invention is similarly applicable to a polygon scanner or any other device that requires a pixel clock.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a laser printer in which an oscillator system according to the present invention is used.

FIG. 2 is a graph showing pixel intervals formed on an image plane by a resonance scanner when a pixel clock is not corrected.

FIG. 3 is a graph showing pixel extension given as a function of position on a scan line in a system without correction for a polygon scanner.

FIG. 4 is a schematic view showing a three-color laser writer according to the present invention.

FIG. 5 is a block diagram showing an oscillator system according to a preferred embodiment of the present invention.

FIG. 6 is a diagram showing timings for loading to a direct digital synthesizer.

FIG. 7 is a diagram showing a part of a frequency correction value loaded in a lookup table (LUT).

FIGS. 8 (a), (b) and (c) are graphs showing the relationship between frequency and time for a pixel clock signal for red, green and blue channels, respectively.

[Explanation of symbols]

 Reference Signs List 10 laser system 11 laser writer 12 red laser 13 green laser 14 blue laser 16, 17, 18 acousto-optic modulator 20 printer circuit 22 pixel clock signal 23 frequency variable pixel clock 30 f-θ lens 34 coupler and optical fiber 38 fold mirror 39 Beam combiner 40 Prism 42 Collimating lens 44 Resonance scanner 45 Channel 51 Position clock 52 Position counter 53 Byte counter 54 Logic circuit 55 Master clock 60 Lookup table 64 Bus separator 68 8-bit bus 70 Direct digital synthesizer 72 Low pass filter

 ──────────────────────────────────────────────────続 き Continued on front page (72) Inventor Thomas Seaweaver 14551 New York, USA Soudas Pilgrim Port Road 4639

Claims (1)

[Claims] 1. A variable frequency pixel clock for generating a series of frequencies programmed to compensate for beam speed variations along a scan line, the direct digital synthesizer providing frequency information to the direct digital synthesizer. A reference table; a first oscillator for providing a reference signal to the direct digital synthesizer; and a counter for providing position information indicating a position of the beam along the scanning line to the reference table. A frequency variable pixel clock, wherein an output signal having a frequency corresponding to the beam position is output by a digital synthesizer.