JPH11163699A - Output buffer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an output buffer circuit capable of facilitating circuit design and effectively reducing noise. SOLUTION: This circuit is provided with the driver 14 of the output final stage of an open drain type. Further, it is provided with a charge-up circuit 16 for charging up a control signal line for controlling the ON/OFF of the driver 14 of the output final stage corresponding to output signals Vin from an internal circuit, a first discharge circuit 18 for discharging the control signal line exclusively of the charge-up circuit 16 corresponding to the output signals Vin from the internal circuit and at least one second discharge circuit 20 for discharging the control signal line exclusively of the charge-up circuit 16 by the control of the first discharge circuit 18.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an open drain type or open source type output buffer circuit having a slew rate control function.

[0002]

2. Description of the Related Art High-speed interfaces such as GTL (Gunning Transceiver Logic) and GTL + use open-drain or open-source output buffer circuits. It is conventionally known that such a high-speed output buffer circuit has a slew rate control function in order to prevent generation of noise such as overshoot or ringing. Hereinafter, a conventional output buffer circuit having a slew rate control function will be described.

FIG. 4 is a circuit diagram showing an example of a conventional output buffer circuit. The output buffer circuit 36 shown in FIG.
Is an open drain type output buffer circuit having a slew rate control function disclosed in Japanese Patent Application Laid-Open No. 4-225275, and basically includes a pre-driver 38 and a driver 40 at the final output stage. Also, pre-driver 3
8 is a charge-up circuit 42, a discharge circuit 4
4. It has a feedback circuit 46.

In the output buffer circuit 36, first, a charge-up circuit 42 charges up a node A for controlling on / off of a driver 40 at an output final stage according to a node Vin which is an output signal from an internal circuit. In the illustrated example, a P-type MOS transistor (hereinafter, referred to as PMOS) 48 is used. The source of the PMOS 48 is connected to the power supply, the gate is connected to the node Vin, and the drain is connected to the node A.

On the other hand, the discharge circuit 44
Discharges the node A exclusively from the above-described charge-up circuit 42 in accordance with a node Vin which is an output signal from an internal circuit. In the illustrated example,
N-type MOS transistor (hereinafter referred to as NMOS) 50
Is used. The source of the NMOS 50 is connected to the ground, the gate is connected to the node Vin,
Its drain is connected to node A.

The feedback circuit 46 feeds back the output of the driver 40 at the final output stage to the node A. In the illustrated example, the input / output terminal (source or drain) is connected between the output terminal Vout and the node A. Two NMOSs 52 and 54 connected in series and a node A
And two inverters 56 and 58 serving as delay circuits connected in series between the inverter and a node B (gate of the NMOS 54). The gate of the NMOS 52 is connected to the node Vin.

The driver 40 at the final output stage drives the output terminal Vout according to the node A. In the illustrated example, an open drain type NMOS 60 is used. The source of the NMOS 60 is connected to the ground, the gate is connected to the node A, and the drain is connected to the output terminal Vout. The output terminal Vout is connected to a terminating power supply VTT via a terminating resistor Rt, and the transmission line 34 to which the output terminal Vout is connected is terminated at a predetermined potential.

Next, referring to the graph shown in FIG.
The operation of the output buffer circuit 36 will be described. Here, the graph of FIG. 5 shows a change in the potential of the node A when the NMOS 60, which is the driver 40 at the final output stage, changes from on to off. , The horizontal axis indicates time (t).

In the output buffer circuit 36, when the node Vin changes from low level to high level,
That is, the slew rate control function operates when the output terminal Vout changes from low level to high level. In the illustrated output buffer circuit 36, first, the node V
When in is at a low level, P
MOS 48 is on, NMOS of discharge circuit 44
50 is off.

That is, the node A is charged up through the PMOS 48 of the charge-up circuit 42, and the NMOS 60, which is the driver 40 at the final output stage, is completely turned on. At this time, the output terminal Vout is low level,
That is, the potential is determined by the resistance division of the terminating resistance Rt and the ON resistance of the NMOS 60. Also,
The node B is also at the high level, the NMOS 52 of the feedback circuit 46 is off, and the NMOS 54 is on.

In this state, when the node Vin changes from the low level to the high level, the PMOS 48 of the charge-up circuit 42 is turned off, and the NMO of the discharge circuit 44 is turned off.
S50, the NMOS 52 of the feedback circuit 46 is turned on. At this time, the node A is discharged via the NMOS 50 and transitions from the high level to the low level. However, the node B changes from the high level after a delay time in which the low level of the node A propagates through the inverters 56 and 58. Transition to low level.

That is, the inverter 5 serving as a delay circuit
During a time (T) corresponding to the delay time of 6, 58, the NMOSs 52, 54 of the feedback circuit 46 are turned on and the output terminal Vout is electrically connected to the node A. Rt and NMOS50,5
The intermediate potential (V0) determined by the resistance division of the on-resistances of the transistors 2, 54 does not completely turn off the NMOS 60, which is the driver 40 at the final output stage. Therefore, NMOS
60 does not turn off suddenly.

When the node B goes low after a time corresponding to the delay time of the inverters 56 and 58, the NMOS 54 of the feedback circuit 46 is turned off, and the feedback path connecting the output terminal Vout and the node A is cut off. You. Therefore, the potential of the node A is discharged via the NMOS 50 of the discharge circuit 44 and becomes completely low level, so that the NMOS 60 which is the driver 40 of the final output stage is completely turned off.

Thus, the transmission line 34 is charged to a high level, that is, charged up to a predetermined potential by the terminating power supply VTT and the terminating resistor Rt. As described above, according to the output buffer circuit 36 in the illustrated example, since the feedback circuit 46 is provided, the driver 4 at the final output stage is provided.
It is stated that overshoot and ground bounce when the NMOS 60 which is 0 transitions from on to off can be suppressed.

As described above, in the output buffer circuit 36, the inverters 56 and 58 of the feedback circuit 46 are provided.
The output terminal Vout is electrically connected to the gate of the NMOS 60, which is the driver 40 at the final output stage, by using the delay time of (1), and the slew rate is controlled by forming a feedback path. Therefore, in the output buffer circuit 36, the adjustment of the delay time of the inverters 56 and 58 is very important.

However, since the delay times of the inverters 56 and 58 fluctuate greatly under the influence of fluctuations in process, voltage, temperature and the like, there is a problem that a sufficient slew rate effect may not be obtained. . Further, since the waveform of the output terminal Vout is fed back to the node A, the effect of noise generated at the output terminal Vout is received by the NMOS 60 of the driver 40 at the final stage of the output, which again generates new noise. There was also a disadvantage.

In the output buffer circuit 36,
When a feedback path is configured, the transistor size of the NMOSs 52 and 54 needs to be relatively large in order to obtain an intermediate potential by dividing the resistance of the node A to obtain an appropriate slew rate effect. Therefore, NMOS
The gate capacitances of the inverters 58 and 54 are increased.
There is also a problem that circuit design is difficult, for example, the load capacity of an internal circuit for driving the node Vin increases.

[0018]

SUMMARY OF THE INVENTION An object of the present invention is to provide an output buffer circuit in which the circuit design is easy and the noise can be effectively reduced in view of the problems based on the prior art. is there.

[0019]

In order to achieve the above object, the present invention provides an open drain type output buffer circuit having a slew rate control function, wherein the open drain type output last stage driver comprises: In response to an output signal from an internal circuit, a charge-up circuit that charges up a control signal line that controls on / off of the driver at the final stage of output, and in response to an output signal from the internal circuit,
A first discharge circuit for discharging the control signal line exclusively with the charge-up circuit, and at least discharging the control signal line exclusively with the charge-up circuit by controlling the first discharge circuit; And an output buffer circuit having one second discharge circuit.

Here, in the first discharge circuit, a first N-type MOS transistor having a gate connected to an output signal of the internal circuit and a drain connected to the control signal line; A resistor element having one terminal connected to the source of the type MOS transistor and the other terminal connected to the ground, the second discharge circuit having a gate biased to a potential at which the transistor conducts; A source is a P-type MOS transistor connected to the control signal line, and a gate is the first N-type M transistor.
It is preferable to have a second N-type MOS transistor connected to a connection point between an OS transistor and the resistance element, a drain connected to the drain of the P-type MOS transistor, and a source connected to the ground.

Further, it is preferable that the resistance element is an always-on N-type MOS transistor having a drain connected to a source of the first N-type MOS transistor and a source connected to the ground.

The present invention is also an open source type output buffer circuit having a slew rate control function,
A driver for the open-source type output final stage, a discharge circuit for discharging a control signal line for controlling on / off of the driver for the output final stage according to an output signal from an internal circuit, and an output signal from the internal circuit. A first charge-up circuit that charges up the control signal line exclusively with the discharge circuit, and the control signal is controlled exclusively by the first charge-up circuit so that the control signal line is exclusively used by the discharge circuit. At least one second charge-up circuit for charging up the line.

Here, the first charge-up circuit has a first P-type MOS transistor having a gate connected to an output signal of the internal circuit and a drain connected to the control signal line; A resistance element having one terminal connected to the source of the P-type MOS transistor and the other terminal connected to the power supply, wherein the second charge-up circuit has a gate biased to a potential at which the transistor conducts. A source is connected to the control signal line, an N-type MOS transistor, and a gate is the first P-type MOS transistor.
It is preferable to have a second P-type MOS transistor connected to a connection point between a transistor and the resistance element, a drain connected to a drain of the N-type MOS transistor, and a source connected to a power supply.

Preferably, the resistance element is a normally-on P-type MOS transistor having a drain connected to a source of the first P-type MOS transistor and a source connected to a power supply.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an output buffer circuit according to the present invention will be described in detail based on a preferred embodiment shown in the accompanying drawings.

FIG. 1 is a circuit diagram showing an embodiment of an output buffer circuit according to the present invention. The output buffer circuit 10 shown in FIG. 1 is an example of an open drain type output buffer circuit used in a high-speed interface such as GTL or GTL +.
And a driver 14 at the final output stage. The pre-driver 12 has a charge-up circuit 16 and first and second discharge circuits 18 and 20.

In the output buffer circuit 10, first, the charge-up circuit 16 sets a node (control signal line) C for controlling on / off of the driver 14 at the final output stage in accordance with a node Vin which is an output signal from an internal circuit. In the illustrated example, a P-type MOS transistor (hereinafter, referred to as PMOS) 22 is used for charging up. The source of the PMOS 22 is connected to the power supply, the gate is connected to the node Vin, and the drain is connected to the node C.

Further, the first discharge circuit 18
The charge-up circuit 16 discharges the node C exclusively in accordance with the node Vin, and includes two N-type MOS transistors (hereinafter, referred to as NMOS) 24 and 26 in the illustrated example. The source of the NMOS 26 is connected to the ground, the gate is connected to the power supply, and the drain is connected to the source of the NMOS 24. The gate of the NMOS 24 is connected to the node Vin,
Its drain is connected to node C.

The second discharge circuit 20 discharges the node C exclusively from the charge-up circuit 16 under the control of the first discharge circuit 18, and has a PMOS 28 and an NMOS 30 in the illustrated example. The source of the NMOS 30 is connected to the ground,
Its gate is connected to the node D (the drain of the NMOS 26), and its drain is connected to the drain of the PMOS 28. The source of the PMOS 28 is connected to the node C, and the gate is connected to the ground.

The driver 14 at the final output stage drives the output terminal Vout according to the node C. In the illustrated example, an open drain type NMOS 32 is used. The source of the NMOS 32 is connected to the ground, the gate is connected to the node C, and the drain is connected to the output terminal Vout. The output terminal Vout is connected to a terminal power supply VTT via a terminal resistor Rt, and the transmission line 34 to which the output terminal Vout is connected is, for example, 1.2.
It is terminated at a potential of ~ 2.0V.

It should be noted that the present invention is not limited to the illustrated example.
This can be applied to a case where 2 is divided into a plurality of NMOSs. In addition, the charge-up circuit 16 and the first and second discharge circuits 18 and 20 may be divided into a plurality of parts, and the path of charge-up by the charge-up circuit 16 may be divided into two or more. The discharge paths of the second discharge circuits 18 and 20 may each be divided into two or more paths.

In the illustrated example, the first discharge circuit 18 uses the always-on NMOS 26 whose gate is connected to the power supply. However, the present invention is not limited to this.
A resistance element may be used instead of the NMOS 26. Further, in the illustrated example, P
Although the gate of the MOS 28 is connected to the ground, the present invention is not limited to this.
It suffices if the voltage is biased to a potential at which the transistor 28 conducts.

In the illustrated example, an example of an open drain type output buffer circuit is shown. However, the present invention is not limited to this, and the present invention can be applied to an open source type output buffer circuit. For example, as shown in FIG. 2, an open source type output buffer circuit to which the present invention is applied
Open drain type output buffer circuit 10 shown in FIG.
, The power supply and ground, the PMOS and NMOS, and the charge-up and discharge are reversed.

The output buffer circuit 10 of the present invention is basically configured as described above. Next, the operation of the output buffer circuit 10 of the present invention will be described with reference to the graph shown in FIG. Here, the graph of FIG. 3 shows a change in the potential of the node C when the NMOS 32 which is the driver 14 at the final stage of the output changes from on to off, and the vertical axis in the figure indicates the potential (V) of the node C. , The horizontal axis indicates time (t).

In the output buffer circuit 10 shown in FIG.
First, when the node Vin is at a low level, the PMOS 22 of the charge-up circuit 16 is on and the NMOS 24 of the first discharge circuit 18 is off. Also,
Since the NMOS 26 of the first discharge circuit 18 is always on, the node D is discharged via the NMOS 26 and is at a low level, and the NMOS 30 of the second discharge circuit 20 is off.

Accordingly, the node C is charged up through the PMOS 22, and the NMOS 32, which is the driver 14 at the final output stage, is completely turned on. At this time, the output terminal Vout is at low level, that is, the terminating resistance Rt and NM
The potential is determined by resistance division with the on-resistance of the OS 32, for example, 0.1 to 0.6V. The second
The PMOS 28 of the discharge circuit 20 is connected to the node C
Is turned on when it becomes higher than the threshold voltage (Vth) of the PMOS 28.

In this state, when the node Vin changes from the low level to the high level, the PMOS 22 of the charge-up circuit 16 is turned off, the NMOS 24 of the first discharge circuit 18 is turned on, and the node C is connected to the first discharge first. It is discharged slowly via the NMOSs 24 and 26 of the circuit 18. At this time, node D
The intermediate potential is determined by the resistance division of the on-resistance of the NMOSs 24 and 26, and the second discharge circuit 20
NMOS 30 is turned on.

The NMOS of the second discharge circuit 20
When the node 30 is turned on, the node C is connected to the P of the second discharge circuit 20 in addition to the first discharge circuit 18.
Discharged at high speed via MOS 28 and NMOS 30. After that, the potential of the node C is
, The on-resistance of the PMOS 28 increases, and at the same time, the on-resistance of the NMOS 30 increases due to the decrease in the gate potential of the NMOS 30,
The amount of current flowing through the second discharge circuit 20 gradually decreases.

When the potential of the node C becomes lower than the threshold voltage of the PMOS 28, the PMOS 28 is turned off. Thereafter, the node C is gradually discharged again only through the first discharge circuit 18, and the NMOS C is discharged.
32 turns off. Thereby, the transmission line 34 is charged up to a predetermined potential, for example, 1.2 to 2.0 V by the terminating resistor Rt.

As described above, the output buffer circuit 1 of the present invention
0, the output last stage driver 14
Until the change in drain current (ΔId / ΔVg) becomes close to the threshold voltage where the change in drain current is the largest with respect to the change in gate voltage in S32, the first and second discharge circuits 18 and 2
0 to quickly discharge node C, and
After the vicinity of the threshold voltage, the first discharge circuit 1
8, the node C is gently discharged to turn off the driver 14 at the final output stage.

Therefore, according to the output buffer circuit 10 of the present invention, an increase in the delay time of the output buffer circuit can be minimized, high-speed operation can be performed, and noise such as overshoot and ringing can be prevented. can do.

Further, the output buffer circuit of the present invention does not feed back the output terminal Vout to the gate of the driver at the output final stage as in the conventional output buffer circuit 36 shown in FIG. It is not affected, and has the advantage that it does not require a feedback path or a delay circuit as compared with the conventional output buffer circuit 36, so that circuit design is easy, and it is less susceptible to variations in process, voltage, and temperature. There is.

The current driving capability of the first discharge circuit 18 may be appropriately determined according to the required slew rate, and the current driving capability of the second discharge circuit 20 is determined by increasing the delay time of the output buffer circuit. It is preferable to make a large adjustment in order to prevent this. Further, the threshold voltage of the PMOS 28 of the second discharge circuit 20 may be appropriately adjusted according to the gate voltage (potential of the node C) at which the change in the drain current becomes the largest with respect to the change in the gate voltage.

Although the output buffer circuit of the present invention has been described in detail, the present invention is not limited to the above-described embodiment.
Of course, various improvements and modifications may be made without departing from the spirit of the present invention.

[0045]

As described above in detail, the output buffer circuit of the present invention basically includes, in the case of an open drain type output buffer circuit, a driver of an open drain type output last stage and an internal circuit. A charge-up circuit that charges up a control signal line that controls on / off of a driver at an output final stage according to an output signal of the output circuit, and a control signal line that is exclusively used as a charge-up circuit according to an output signal from an internal circuit , And at least one second discharge circuit that discharges a control signal line exclusively from the charge-up circuit under the control of the first discharge circuit. In the output buffer circuit according to the present invention, the control signal line is controlled by the first and second discharge circuits until the change in the drain current becomes close to the threshold voltage at which the change in the drain current becomes the largest with respect to the change in the gate voltage of the driver at the output final stage. Is discharged at a high speed, and after the vicinity of the threshold voltage, the control signal line is slowly discharged only by the first discharge circuit, and the driver at the final output stage is turned off. According to the output buffer circuit of the present invention, circuit design is easy, and it is hardly affected by fluctuations in process, voltage, and temperature. For example, even in a high-speed interface or the like, increase in delay time is minimized.
Generation of noise can be effectively prevented.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating an output buffer circuit according to an embodiment of the present invention;

FIG. 2 is a configuration circuit diagram of another embodiment of the output buffer circuit of the present invention.

FIG. 3 is a graph showing an operation of the output buffer circuit according to the embodiment of the present invention.

FIG. 4 is a circuit diagram illustrating an example of a conventional output buffer circuit.

FIG. 5 is a graph showing an example of the operation of a conventional output buffer circuit.

[Explanation of symbols]

10, 36 Output buffer circuit 12, 38 Pre-driver 14, 40 Last output stage driver 16, 42 Charge-up circuit 18, 20, 44 Discharge circuit 22, 28, 48 P-type MOS transistor (PMO
S) 24, 26, 30, 32, 50, 52, 54, 60 N
Type MOS transistor (NMOS) 34 Transmission line Vin Output signal from internal circuit Vout Output terminal VTT Termination power supply Rt Termination resistor

Claims (6)

[Claims] 1. An open drain type output buffer circuit having a slew rate control function, wherein the open drain type output last stage driver and the output last stage driver according to an output signal from an internal circuit. A charge-up circuit for charging up a control signal line for controlling on / off of the first circuit, and a first discharge circuit for discharging the control signal line exclusively with the charge-up circuit in response to an output signal from the internal circuit. By controlling the first discharge circuit,
An output buffer circuit, comprising: at least one second discharge circuit that discharges the control signal line exclusively with the charge-up circuit. A first N-type MOS transistor having a gate connected to an output signal of the internal circuit and a drain connected to the control signal line; and a first N-type MOS transistor having a drain connected to the control signal line. A resistor element having one terminal connected to the source of the MOS transistor and the other terminal connected to the ground, wherein the second discharge circuit has a gate biased to a potential at which the transistor conducts; Are connected to a connection point between the first N-type MOS transistor and the resistance element, and a drain is connected to a drain of the P-type MOS transistor. 2. The output buffer circuit according to claim 1, further comprising a second N-type MOS transistor having a source connected to the ground. 3. The resistance element has a drain connected to the first N
3. The output buffer circuit according to claim 2, wherein the output buffer circuit is an N-type MOS transistor which is connected to the source of the type MOS transistor and whose source is connected to the ground, and which is always on. 4. An open source type output buffer circuit having a slew rate control function, wherein the open source type output last stage driver and the output last stage driver according to an output signal from an internal circuit. A discharge circuit that discharges a control signal line that controls on / off of a first charge-up circuit that charges up the control signal line exclusively with the discharge circuit in accordance with an output signal from the internal circuit; An output buffer circuit comprising: at least one second charge-up circuit that charges up the control signal line exclusively with the discharge circuit under the control of the first charge-up circuit. 5. The first charge-up circuit, wherein a first P-type MOS transistor having a gate connected to an output signal of the internal circuit and a drain connected to the control signal line; A resistor element having one terminal connected to the source of the type MOS transistor and the other terminal connected to a power supply, wherein the second charge-up circuit has a gate biased to a potential at which the transistor is conductive. An N-type MOS transistor having a source connected to the control signal line, a gate connected to a connection point between the first P-type MOS transistor and the resistance element, and a drain connected to a drain of the N-type MOS transistor 5. The output buffer circuit according to claim 4, further comprising a second P-type MOS transistor having a source connected to a power supply. 6. The resistance element has a drain connected to the first P
6. The output buffer circuit according to claim 5, wherein the output buffer circuit is a normally-on P-type MOS transistor connected to a source of the type MOS transistor and having a source connected to a power supply.