JPH11163129A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a highly productive manufacturing method of an embedded layer by a method, wherein when a multilayered wiring structure is realized, breakage of wire due to a through-hole and the step coverage of an embedded metal, is prevented and an IC is planarized. SOLUTION: First, an Al wiring circuit 3 is provided in the interlayer connecting method of an IC having a multilayered wiring structure. Then, after the formation of a SiO2 interlayer insulating film 1, a through-hole is provided, and the Al wiring circuit is exposed. Then, an Al sheet metal layer 5 is provided on the entire surface of the interlayer insulating film 1. Then, a plate metal layer 6 is provided by electroplating Cu. Subsequently, the entire surface of a wafer is polished using a chemical mechanical polishing method, the slight interlayer insulating film of the plated metal layer, on the upper layer of the wafer, and the sheet metal layer are removed, and the surface almost flat with an embedded electrode layer 7 is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a multi-layered wiring structure, which significantly improves the productivity of semiconductor devices, essentially contributes to flattening, and also eliminates reliability defects due to step coverage. It is a suggestion. More particularly, the present invention relates to a method of manufacturing an embedded electrode layer when connecting a lower wiring circuit to an upper wiring circuit or the like via a through hole.

[0002]

2. Description of the Related Art As a semiconductor integrated circuit (referred to as an IC) is used in various fields, one of the objects is to form a fine pattern to reduce a chip size. However, in order to make the IC easy to use, to increase the reliability of the IC, and to increase the functions of the IC, there is a phenomenon that the law of scaling is not always applied. That is, if the thickness direction such as the thickness of the wiring or the interlayer insulating film is reduced, the wiring resistance and the wiring delay increase, causing deterioration in characteristics and reliability, and deviating from the scaling law.

In particular, as the number of multilayer wirings increases, it becomes necessary to flatten the interlayer insulating film and to flatten the metal buried electrode layer in the vertical connection portion in any region with little unevenness. When a certain degree of progress has been observed in the planarization of the interlayer insulating film, the degree of integration has been remarkably improved, but the next problem is to increase the density of interlayer connections by miniaturizing through holes. That is, in order to advance the miniaturization of the through hole, the aspect ratio must be eventually increased.

Further, if a through hole is formed by a dry etcher and a metal layer is formed by sputtering, disconnection often occurs due to step coverage, and the problem returns to the basic problem of an IC. In the first place, the sputter basically involves colliding ions such as Ar with an Al target and receiving particles ejected from the Al target on a semiconductor substrate. Since particles jumping out of the target have a short mean free path, many particles collide with each other and scatter, so that the film has excellent uniformity. As mentioned above, if you try to reach the inside of a through hole with a high aspect ratio and attach metal by sputtering,
Due to the short mean free path, the step coverage is deteriorated, and it is said that a process with a Al coverage of 0.1 at the surface edge portion and the vertical portion of the through hole is a good process.

[0005] Furthermore, the productivity of the sputtering apparatus is very poor. That is, although it is common to the devices using the vacuum system in general, there are many troubles, and a lot of normal maintenance is required, and the operation rate of the device is poor. The peeling of the metal adhered to the inside of the device causes pinholes, short circuits, etc. The present invention proposes a method for manufacturing a multilayer wiring, particularly a buried electrode layer, that is, an interlayer connection of a wiring circuit between upper and lower layers as described above. There have been many proposals in which flatness was sought and the step coverage was wiped off, but each had its own drawbacks. An example of the manufacturing method will be described with reference to FIGS. FIG. 3A shows a circuit element provided on the semiconductor substrate 14.
The wiring circuit 12 connected to the desired area is taken out.
The fact that the surface of the semiconductor substrate 14 is covered with an insulating film
As a matter of course, the buried metal layer 1 is called in advance at a position where interlayer connection is to be planned between the upper and lower layers.
3 is provided. Next, after the interlayer insulating film 11 is provided, a resist layer 15 is applied, and a dry etcher is used to select a condition having the same etching rate as that of the resist layer 15 and the underlying interlayer insulating film 11, and non-selectively etch the entire surface. I do. As a result, as shown in FIG. 3B, the protrusions of the interlayer insulating film 11 are etched and flattened simultaneously with the resist layer 15, the pillars are exposed as the buried electrode layer 13, and finally the resist layer 15 is removed. Formed.

[0006]

The above-described method is very effective for flattening and can achieve almost perfect flattening. However, the pillars must be selectively grown in the through-holes, or once deposited over the entire surface, followed by a selective etch. In the selective growth, the metal is limited to W or the like, and the selective etching requires a long process. As described above, even though there are various methods, in fact, some of the above-mentioned three drawbacks always have to be found and the ultimate method cannot be found.

SUMMARY OF THE INVENTION The present invention is intended to realize flattening of an interlayer insulating film and a buried metal layer, improvement of step coverage caused by deposition of metal by sputtering, and realization of a method with as high productivity as possible. is there.

[0008]

SUMMARY OF THE INVENTION The present invention is a method in which three defects are improved as compared with the above-mentioned conventional method, and a step of forming a thin sheet metal layer after forming a through hole, and finally, It is constituted by a step of providing a plating metal layer to be an embedded electrode and polishing of a wafer by chemical mechanical polishing (CMP).
Deposition of a metal layer by plating eliminates the disadvantage of step coverage, and CMP is polished in parallel if a correct attachment to a polishing plate is performed correctly, thereby realizing a flat wafer.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail with reference to FIGS. 1 (A) and 1 (B) and FIGS. 2 (A) and 2 (B). According to the present invention, as shown in FIG. 1A, a wiring circuit 3 to which a desired portion of each circuit element provided on a semiconductor substrate 4 is connected is taken out. Except for a special case, in the process of forming the wiring circuit 3, all the circuit elements are incorporated in the semiconductor substrate 4, so that they are provided on the surface of the semiconductor substrate 4 for electrical isolation. It is provided on the insulating film. As described above, the multi-layered wiring is often formed in two or more layers since the IC needs to have a relatively large area since the pattern often deviates from the law of scaling in the IC, and a wiring circuit is provided after this step. For this reason, a film called an interlayer insulating film mainly for the purpose of insulating between adjacent layers is provided. Naturally, a through hole 2 perforated in the interlayer insulating film 1 is provided so that the upper and lower layers are electrically connected. Will be Here, an example of specific numerical values is shown.
Is SiO2, the thickness is 1.2 μm, the size of the through hole is 0.75 μm square, the wiring circuit is Al and the thickness is 0.8
μm.

Next, as shown in FIG. 1B, a sheet metal layer 5 is provided to cover the interlayer insulating film 1, the exposed portion of the wiring circuit 3, and the side wall of the through hole 2. The sheet metal layer was made of Al and had a thickness of 0.3 μm. Sheet metal layer 5
Al is suitable, but thin, so good results were obtained with Cr and Ni. Furthermore, since this sheet metal layer only functions as one electrode at the time of plating, which will be described later, even if there is a thin portion due to variation or an extremely defective portion, fill it with a metal layer so that the through hole is filled. No effect.

Next, a plating solution containing mainly a plating solution mainly composed of copper sulfate or a surfactant is charged into a plating tank, and a plating metal layer 6 is formed on the surface of the sheet metal layer 5 as shown in FIG. Is provided. Although the plating technique has been completed and need not be particularly described in detail, it is important to control the content of the PH or Cu component of the plating solution, the amount of the surfactant, or the temperature. The drawings are schematically shown, and the actual cross-sectional shape is not completely flat as shown in the figure, and the shape of the through hole slightly influences the shape, and a concave portion may be formed. However, according to the present invention, it is necessary that the thickness of the plated metal layer 6 sufficiently exceeds the interlayer insulating film 1, and specifically, the conditions are set to obtain 1.2 μm. Further, as the plating metal layer, copper is exemplified, but Au, Ag, and Ni are suitable for the present invention, but Cu is most suitable as an economic effect.

Finally, the semiconductor substrate 4 is bonded to a polishing plate and rotated by a chemical mechanical polishing method, and polishing is performed simultaneously with etching. As a result, as shown in FIG. 2B, the plated metal layer 6 and the sheet metal layer 5 existing on the surface are chemically and mechanically cut from the upper portion of the semiconductor substrate 4 to expose the interlayer insulating film 1. The intended embedded electrode layer 7 is obtained.

[0013]

According to the present invention, the buried electrode layer can be provided by removing all of the three drawbacks mentioned first. That is, the flattening of the semiconductor substrate can be achieved almost entirely by applying a chemical mechanical poly method.
In addition, since stepped coverage does not occur in principle because plating metal is used, it is appropriate to provide a sheet metal layer by sputtering, but in this case it is as thin as 0.3 μm and it is simply used as a barrier metal. Even if a break occurs, there is no effect. Further, since the plating method is used, a very large number of substrates can be plated at the same time, and productivity is remarkably increased. The three deficiencies mentioned earlier have been resolved.

[0014] Further, with respect to Cu plating, there is no migration symptom as a feature, so that both fine patterning and improvement of reliability can be achieved at the same time.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view for explaining the present invention.

FIG. 2 is a schematic sectional view for explaining the present invention.

FIG. 3 is a schematic cross-sectional view for explaining a conventional example.

Claims (1)

[Claims] 1. A step of providing a wiring circuit made of a conductive material connected to a desired region of a semiconductor element or another wiring circuit in a buried electrode of an interlayer connection part in a multi-layer wiring structure, a semiconductor substrate surface including the wiring circuit Providing an exposed portion in the wiring circuit by providing a through-hole exposing a desired region of the wiring circuit by piercing the interlayer insulating film, and providing an exposed portion in the wiring circuit. A step of providing a sheet metal layer covering the exposed portion and the side wall of the through hole, a step of covering at least the sheet metal layer with a plating metal layer attached by plating, and a step of chemically and mechanically polishing the interlayer insulating film. The plated metal layer and seal metal layer are removed, and the through holes provided in the interlayer insulating film are filled with the wiring circuit, sheet metal, and plated metal layer. Forming the embedded buried electrode layer at the same level as the interlayer insulating film.