JPH11162990A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable guttering of polluted heavy metal to be performed by simple method, and cope with micronization and promotion of high density, by introducing high-concentration impurities into a place positioned in the center area of a pattern, and introducing low-concentration impurities into the peripheral region of the region where they are introduced. SOLUTION: An element isolating insulating film 2 is made selectively on a silicon substrate 1. A low-concentration channel stopper region 3 and a high- concentration channel stopper region 4 are made at the surface of the silicon substrate 1 under this element isolating insulating film 2. Here, the high- concentration channel stopper region 4 is made in the region positioned at the center of the element isolating region, and the low-concentration channel stopper region 3 is made in the region positioned in the periphery of the element isolating region. Then, a diffused layer 5 is made in a self alignment manner in the element insulating film 2 at the surface of the silicon substrate 1. Moreover, the low-concentration channel stopper region 3 is made to contact with the diffused layer 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a structure of a semiconductor device capable of easily gettering contaminated heavy metals and a method of manufacturing the same.

[0002]

2. Description of the Related Art Fine structure and high density of semiconductor devices are being vigorously promoted. In this miniaturization, a semiconductor element formed with a size of 0.15 μm is currently used, and a semiconductor device such as a memory device or a logic device based on this size is being developed.

[0003] Such miniaturization is the most effective method for achieving high performance or multifunction by high integration, high speed, or low power consumption of a semiconductor device, and is indispensable for the manufacture of a semiconductor device in the future. is there. In order to reduce power consumption of a semiconductor device, it is particularly necessary to reduce junction leakage of a diffusion layer formed on a semiconductor substrate. In addition, it is essential to increase the reliability of an insulating film that is reduced in thickness with miniaturization of a semiconductor device.

However, with the miniaturization of such semiconductor elements, heavy metal contamination becomes a more important problem together with fine particles introduced in a manufacturing process. In particular, when the density of a semiconductor device formed on a semiconductor substrate increases, a large stress occurs around the semiconductor element, and contaminated heavy metals are captured (called gettering) by the semiconductor element. When a small amount of heavy metals such as Fe, Cu, and Ni are mixed in the manufacturing process of the semiconductor device, these heavy metals are gettered in the element isolation region where the thick insulating film is formed. In particular, gettering tends to occur at the end of such an element isolation region. This is because stress concentrates on this end.

[0005] Then, it becomes difficult to reduce the junction leakage of the diffusion layer as described above, and the reliability of a thin insulating film such as a gate oxide film decreases.

Hereinafter, LOCOS (Local Oxid), which is widely used as a method of forming an element isolation region, is described below.
The operation of silicon method will be described with reference to FIGS.

[0007] As shown in FIG.
The protective insulating film 22 and the mask insulating film 23 are formed in a predetermined pattern on the surface of the semiconductor device 1. Here, the protective insulating film 22 is formed of a silicon oxide film, and the mask insulating film 23 is formed of a silicon nitride film or the like having high oxidation resistance.

[0008] Then, the exposed surface of the silicon substrate 21 is thermally oxidized using the mask insulating film 23 as an oxidation mask. Thus, as shown in FIG. 9B, the element isolation insulating film 24 is formed. This element isolation insulating film 24 is a silicon oxide film having a thickness of about 200 nm. This thermal oxidation causes the element isolation insulating film 24 to go under the mask insulating film 23. That is, a well-known bird's beak is formed at the end of the element isolation insulating film 24.

Then, as shown in FIG. 9C, the mask insulating film 23 is selectively removed. Thus, the protective insulating film 22 and the element isolation insulating film 24 are formed on the surface of the silicon substrate 21. Thereafter, a gate oxide film, a gate electrode, a source / drain diffusion layer and the like are formed, and a MOS transistor constituting a semiconductor device is formed.

In such an element isolation region, as shown in FIG. 10, a channel stopper region 25 is formed immediately below an element isolation insulating film 24 formed on the surface of a silicon substrate 21. When the silicon substrate 21 is of a P-type conductivity type, boron impurities having an impurity concentration of about 10 ¹⁶ atoms / cm ³ are introduced into the channel stopper region 25 almost uniformly.
When the silicon substrate 21 is of the N-type conductivity type, a phosphorus impurity is introduced into the channel stopper region 25.

The purpose of the formation of the channel stopper region is mainly to prevent the surface of the silicon substrate under the element isolation insulating film 24, which is a thick insulating film, from being inverted and the element isolation function being lost.

[0012]

As the size of the semiconductor device becomes smaller, it becomes necessary to reduce the bird's beak formed at the end of the element isolation insulating film 24. For this reason, the stress at the end of the element isolation insulating film is increased, and a large stress is generated on the surface of the silicon substrate 21 immediately below the edge.

The heavy metal mixed in the semiconductor device manufacturing process is gettered in the region where the large stress is formed. Heavy metals such as Fe are also gettered by an element isolation insulating film which is a silicon oxide film. In this way, the heavy metal collected in the element isolation region increases the junction leak of the diffusion layer formed near the element isolation region or decreases the insulating property of the insulating film formed near the element isolation region. I will let you.

Such a problem occurs not only in the element isolation region having the normal LOCOS structure but also in the element isolation region having the trench structure.

As means for solving such a problem, LOCOS described in JP-A-62-48028 is disclosed.
There is a method of introducing crystal defects into a silicon substrate at the center of the structure. However, in this method, since a large number of secondary defects occur on the surface of the silicon substrate, when the semiconductor element becomes finer and the element isolation region becomes narrower, conversely,
It has an adverse effect on semiconductor devices.

Further, the gettering in this method is a gettering of the heavy metal only for the supersaturation, and cannot getter the heavy metal of the solid solution in the silicon substrate. For this reason, in this method, as the manufacturing line of the semiconductor device becomes clean, its effectiveness is reduced.

An object of the present invention is to provide a semiconductor device which solves all of the above problems, enables gettering of contaminated heavy metals by a simple method, and can cope with miniaturization or high density, and a method of manufacturing the same. It is in.

[0018]

According to the present invention, there is provided a semiconductor device according to the present invention, wherein a semiconductor substrate is provided immediately below an insulating film formed in a predetermined pattern shape on a surface of the semiconductor substrate, and is located in a central region of the pattern shape. At this point, high-concentration impurities are introduced, and low-concentration impurities are introduced into a region around the region into which the high-concentration impurities are introduced.

The insulating film formed in the pattern shape becomes an element isolation insulating film formed in an element isolation region of the semiconductor device, and the region into which the high concentration impurity and the low concentration impurity are introduced becomes a channel stopper region. . Here, the high concentration impurity and the low concentration impurity are boron impurities, and the concentration of the high concentration impurity is 10 ¹⁸ atoms / cm 2.
It is set to be ³ or more. Alternatively, the concentration ratio is set so that the concentration ratio between the high concentration impurity and the low concentration impurity is 10 ² or more. Alternatively, the high concentration impurities and the low concentration impurities are phosphorus impurities.

Further, a method of manufacturing a semiconductor device according to the present invention
Forming an oxidation-resistant mask insulating film having a predetermined opening on the surface of the semiconductor substrate; and performing a first ion implantation for low-concentration impurities on the surface of the semiconductor substrate through the opening. Forming a sidewall insulating film on the side wall of the opening after the first ion implantation, and performing a second ion implantation for high-concentration impurities using the mask insulating film and the sidewall insulating film as an ion implantation mask; When,
Removing the sidewall insulating film, and thermally oxidizing the semiconductor substrate in the opening using the mask insulating film as an oxidation mask to form an element isolation insulating film.

Alternatively, in the method of manufacturing a semiconductor device according to the present invention, a step of forming an oxidation-resistant mask insulating film having a predetermined opening on a surface of a semiconductor substrate; Forming a second ion implantation for high-concentration impurities using the mask insulating film and the side wall insulating film as an ion implantation mask, and removing the side wall insulating film, and then forming a semiconductor through the opening. Performing a first ion implantation for a low concentration impurity on a surface of the substrate; and thermally oxidizing the semiconductor substrate in the opening using the mask insulating film as an oxidation mask to form an element isolation insulating film. .

The contaminant heavy metal mixed in the manufacturing process of the semiconductor device collects near the thick insulating film formed on the surface of the semiconductor substrate. This is because a large stress is generated in this region. Alternatively, heavy metals such as Fe are easily gettered by an insulating film such as a silicon oxide film.

Therefore, in a structure which is a main part of the present invention and has a region formed on the semiconductor substrate under the insulating film, into which a high-concentration impurity is introduced, and a peripheral region into which a low-concentration impurity is introduced, The contaminated heavy metal is likely to be segregated in the region where the high concentration impurity is introduced. As a result, the region into which the high-concentration impurity is introduced effectively functions as a gettering region for the contaminated heavy metal, and the heavy metal collected near the thick insulating film is captured.

[0024]

Next, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of an element isolation region for describing an embodiment of the present invention.

As shown in FIG. 1, an element isolation insulating film 2 is selectively formed on a silicon substrate 1. A low-concentration channel stopper region 3 and a high-concentration channel stopper region 4 are formed below the element isolation insulating film 2 and on the surface of the silicon substrate 1. Here, the high concentration channel stopper region 4 is formed in a region located at the center of the element isolation region, and the low concentration channel stopper region 3 is formed in a region located at the periphery of the element isolation region.

For example, when the conductivity type of the silicon substrate 1 is P-type, a high-concentration boron impurity is introduced into the high-concentration channel stopper region 4. Then, into the low-concentration channel stopper region 3, as described later, a low-concentration boron impurity of two digits or less of the boron impurity of the high-concentration channel stopper region 4 is introduced.

Then, a diffusion layer 5 is formed on the surface of the silicon substrate 1 and in a self-alignment manner with the element isolation insulating film 2 in a self-aligned manner. Here, an impurity of a conductivity type opposite to that of the silicon substrate 1 is introduced into the diffusion layer 5. Normally, as shown in FIG. 1, the low concentration channel stopper region 3 is formed so as to be in contact with the diffusion layer 5.

Next, as a second embodiment of the present invention, a method of manufacturing a structure of an element isolation region of the present invention will be described with reference to FIGS. Here, FIGS. 2 and 3
3A to 3C are cross-sectional views in the order of manufacturing steps for explaining the present invention.
Hereinafter, the same components as those described in FIG. 1 are denoted by the same reference numerals.

As shown in FIG. 2A, a silicon oxide film having a thickness of about 20 nm is formed on the surface of a P-type silicon substrate 1 by a thermal oxidation method, and a protective insulating film 6 is provided. . Then, a film thickness of 200 nm is formed on the protective insulating film 6.
About a silicon nitride film is stacked and deposited, an opening is provided by photolithography and dry etching, and a mask insulating film 7 is formed. Here, the silicon nitride film is deposited by a chemical vapor deposition (CVD) method. The size of the opening is about 0.6 μm.

Next, as shown in FIG. 2B, first ions 8 are ion-implanted into the entire surface, and a first channel stopper is implanted. Here, the first ions 8 are boron ions, the implantation energy is 40 keV, and the dose is set to about 10 ¹² ions / cm ² . And
Heat treatment is performed. Thus, the low-concentration channel stopper region 3 described above is formed.

Next, as shown in FIG. 2C, a sidewall insulating film 9 is formed on the side wall of the opening provided in the mask insulating film 7. The sidewall insulating film 9 is formed by first forming a silicon oxide film having a thickness of about 200 nm on the entire surface by CV.
It is deposited by the D method, and subsequently, is formed by performing overall etching (etchback) by anisotropic reactive ion etching (RIE). Thus, the sidewall insulating film 9 having a thickness of about 200 nm is formed.

Next, as shown in FIG. 3A, the mask insulating film 7 and the side wall insulating film 9 are used as an implantation mask.
Second ions 10 are implanted into the entire surface, and a second channel stopper is implanted. Here, the second ion 1
0 is also a boron ion, and the implantation energy is 50 keV.
And the dose is set to about 10 ¹⁴ ions / cm ² . Then, a heat treatment is performed. Thus, the high concentration channel stopper region 4 is formed. Here, since the thickness of the sidewall insulating film 9 is about 200 nm, the high concentration channel stopper region 4 is formed in a region narrower by about 200 nm on one side than the low concentration channel stopper region 3.

Next, as shown in FIG. 3B, the side wall insulating film 9 formed on the side wall of the opening of the mask insulating film 7 is removed with a chemical such as a hydrofluoric acid solution. Then, thermal oxidation is performed using the mask insulating film 7 as a mask,
As shown in FIG. 3C, an element isolation insulating film 2 is formed on the low concentration channel stopper region 3 and the high concentration channel stopper region 4. Here, the element isolation insulating film 2 is a silicon oxide film having a thickness of about 300 nm.

Next, the mask insulating film 7 is removed with a chemical such as hot phosphoric acid. Then, the diffusion layer 5 illustrated in FIG. 1 is formed by the ion implantation of the arsenic impurity and the heat treatment.

Next, the effects of the present invention and the conditions of the present invention will be described with reference to FIG. FIG. 4 is a graph for explaining the relationship between the boron concentration of the high-concentration channel stopper region 4 (referred to as P ⁺ region) and the gettering ability of heavy metals. Here, the horizontal axis of the graph indicates the above boron concentration, and the vertical axis indicates the leak current of the N ⁺ P junction.

As can be seen from FIG. 4, when the concentration of boron in the P ⁺ region becomes 10 ¹⁸ atoms / cm ³ or more, the junction leak rapidly decreases. As described above, in the second embodiment of the present invention, it can be said that when the high-concentration channel stopper region 4 contains a boron impurity having a concentration of 10 ¹⁸ atoms / cm ³ or more, it becomes very effective.

The heavy metal gettering ability of such an element isolation region strongly depends on the boron concentration ratio between the high concentration channel stopper region 4 and the low concentration channel stopper region 3 (referred to as P region). This will be described with reference to FIG.

FIG. 5 is a graph for explaining the relationship between the ratio of P ⁺ region boron concentration / P region boron concentration and the gettering ability of heavy metals. Here, the horizontal axis of the graph represents the value of P ⁺ region boron concentration / P region boron concentration, and the vertical axis represents the leakage current of the N ⁺ P junction.

As can be seen from FIG. 5, when the value of P ⁺ region boron concentration / P region boron concentration becomes 10 ² or more, the junction leakage rapidly decreases. As described above, according to the second embodiment of the present invention, the boron impurity concentration of the low-concentration channel stopper region 3 is increased.
Becomes effective when the concentration is less than 1/100 of the boron impurity concentration. This is because the contaminated heavy metal is distributed between the high-concentration channel stopper region 4 and the low-concentration channel stopper region 3, so that the relative ratio of the boron concentration between the high-concentration channel stopper region 4 and the low-concentration channel stopper region 3 is important. Because it becomes.

Next, as a third embodiment of the present invention, another method of manufacturing the structure of the element isolation region of the present invention will be described with reference to FIGS. Here, FIGS. 6 and 7 are cross-sectional views in the order of manufacturing steps for explaining the present invention. Hereinafter, the same components as those described in the second embodiment are denoted by the same reference numerals.

As shown in FIG. 6A, a silicon oxide film having a thickness of about 20 nm is formed on the surface of an N-type silicon substrate 1 by a thermal oxidation method, and a protective insulating film 6 is provided. . Then, a film thickness of 500 nm is formed on the protective insulating film 6.
About a silicon nitride film is stacked and deposited, an opening is provided by photolithography and dry etching, and a mask insulating film 7 is formed. Here, the silicon nitride film is deposited by a CVD method.

Next, as shown in FIG. 6B, a side wall insulating film 9 is formed on the side wall of the opening provided in the mask insulating film 7 in the same manner as described in the second embodiment. It is formed.

Next, as shown in FIG. 6C, the mask insulating film 7 and the side wall insulating film 9 are used as an implantation mask.
Third ions 11 are implanted into the entire surface, and first, a second channel stopper implantation is performed. Here, the third ions 11 are phosphorus ions, and the implantation energy is 50
KeV and the dose is set to about 10 ¹³ ions / cm ² . Then, a heat treatment is performed. Thus, the high concentration channel stopper region 4a is formed.

Next, as shown in FIG. 7A, the sidewall insulating film 9 formed on the side wall of the opening of the mask insulating film 7 is removed with a chemical such as a hydrofluoric acid solution. Then, as shown in FIG. 7B, thermal oxidation is performed using the mask insulating film 7 as a mask, and the element isolation insulating film 2 is formed. Here, the element isolation insulating film 2 is a silicon oxide film having a thickness of about 250 nm.

Next, as shown in FIG. 7C, fourth ions 12 are ion-implanted over the entire surface, and a first channel stopper is implanted. Here, the fourth ions 12 are phosphorus ions, the implantation energy is 300 keV, and the dose is set to about 10 ¹² ions / cm ² . Then, a heat treatment is performed. Thus, the low concentration channel stopper region 3a is formed.

Then, the mask insulating film 7 is removed by a chemical such as hot phosphoric acid, and the diffusion layer 5 described in FIG. 1 is formed by ion implantation of boron impurities and heat treatment.

Next, a fourth embodiment of the present invention will be described with reference to the drawings. FIG. 8 is a sectional view of an element isolation region for describing an embodiment of the present invention. This embodiment is a case where the present invention is applied to trench element isolation.

As shown in FIG. 8, a well 13 is formed on the surface of the silicon substrate 1, and a trench 14 is formed in a predetermined region of the well 13. The trench 14 is filled with a buried insulating film 15. This buried insulating film 15 becomes the above-described element isolation insulating film. A high concentration channel stopper region 16 is formed below the buried insulating film 15 and at the bottom of the trench 14.

Then, the gate oxide film 1 is formed on the surface of the well 13.
7 and a gate electrode 18 are formed, and a diffusion layer 19 is formed. Thus, a MOS transistor is formed.

Next, the effects of the present invention will be described below. Here, in order to quantitatively grasp the effect, after arsenic impurities for the diffusion layer are ion-implanted, Fe ions are ion-implanted on the surface of the silicon substrate as a contaminating heavy metal, and a heat treatment is performed to reduce junction leakage. Measured. Table 1 shows a breakdown of the sample in the case where the element isolation region of the present invention was formed in the second embodiment. Here, the sample of the related art has the element isolation region described in the related art.

[0051]

[Table 1]

The results are shown in Table 2. here,
Junction leakage occurs when a reverse bias of 5 V is applied at room temperature
Is the value of As can be seen from Table 2, the method of the present invention
Junction leakage is significantly reduced. In particular, for sample 4,
Work is reduced to 1/100 or less of the conventional case.
You. In sample 4, P⁺Area boron concentration is 10¹⁸ original
Child / cm^ThreeDegree and P⁺Area boron concentration /
P region boron concentration ratio is 10^TwoIt is about.

[0053]

[Table 2]

Next, effects in the case of the element isolation region of the present invention described in the third embodiment will be described with reference to Tables 3 and 4.

Also in this case, in order to quantitatively grasp the effect, after boron impurities for the diffusion layer are ion-implanted, Fe ions are ion-implanted on the surface of the silicon substrate as a contaminating heavy metal, and heat treatment is performed. Junction leakage was measured. Table 3 shows a breakdown of the sample in the case where the element isolation region of the present invention was formed in the third embodiment. Here, the sample of the related art has the element isolation region described in the related art.

[0056]

[Table 3]

The results are shown in Table 4. Also in this case, the junction leakage is a value when a reverse bias of 5 V is applied at room temperature. As can be seen from Table 4, the junction leak is reduced to about 1/1000 of the conventional case by the method of the present invention.

[0058]

[Table 4]

Similarly, the effect of the present invention was quantitatively measured based on the reliability of the gate oxide film. Here, the thickness of the gate oxide film was set to 10 nm, and its reliability was evaluated. As a result, in the evaluation of the charge amount until the gate oxide film causes dielectric breakdown, it was found that the present invention can withstand a charge amount four times or more that of the conventional case.

In the above embodiment, the case where the high concentration channel stopper region and the low concentration channel stopper region are formed immediately below the element isolation insulating film has been described. It is to be noted that the present invention is not limited to the element isolation insulating film, and that the same effect can be obtained even if the insulating film is formed immediately below the thick insulating film formed on the silicon substrate surface. .

[0061]

As described above, according to the present invention, in the semiconductor substrate immediately below the insulating film formed in a predetermined pattern shape on the surface of the semiconductor substrate, the high position is located at the central region of the above pattern shape. A high-concentration impurity is introduced, and a low-concentration impurity is introduced into a region around the region into which the high-concentration impurity is introduced.

The insulating film formed in the above-described pattern shape becomes an element isolation insulating film formed in the element isolation region of the semiconductor device, and the region into which the high concentration impurities and the low concentration impurities are introduced is a channel stopper region. Used as In this case, the concentrations of the high concentration impurity and the low concentration impurity are set to be appropriate amounts.

In this manner, heavy metals which are mixed in the manufacturing process of the semiconductor device and are likely to collect in the element isolation region are effectively gettered in the region where the high concentration impurity is introduced. And the junction leak of the diffusion layer formed near the element isolation region is significantly reduced, or
The insulating property of the thin insulating film formed near the element isolation region is greatly improved.

Further, according to the method of the present invention, no crystal defects are introduced into the semiconductor substrate, and the method works effectively even if the semiconductor element becomes finer and the element isolation region becomes narrower. In the present invention, since the heavy metal segregates in the region into which the high-concentration impurity is introduced, gettering of a heavy metal having a supersaturation or more can be performed, unlike the related art. For this reason, in the method of the present invention, even if the manufacturing line of the semiconductor device becomes clean, its effectiveness is not reduced.

[Brief description of the drawings]

FIG. 1 is a sectional view of an element isolation region for explaining a first embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a second embodiment of the present invention in the order of manufacturing steps.

FIG. 3 is a cross-sectional view illustrating a second embodiment of the present invention in the order of manufacturing steps.

FIG. 4 is a graph for explaining effective conditions in the embodiment.

FIG. 5 is a graph for explaining effective conditions in the embodiment.

FIG. 6 is a sectional view illustrating a third embodiment of the present invention in the order of manufacturing steps.

FIG. 7 is a cross-sectional view illustrating a third embodiment of the present invention in the order of manufacturing steps.

FIG. 8 is a cross-sectional view of an element isolation region for explaining a fourth embodiment of the present invention.

FIG. 9 is a cross-sectional view illustrating a conventional technique in the order of manufacturing steps of an element isolation region.

FIG. 10 is a sectional view of an element isolation region for explaining a conventional technique.

[Explanation of symbols]

 1, 21 Silicon substrate 2, 24 Device isolation insulating film 3, 3a Low concentration channel stopper region 4, 4a, 16 High concentration channel stopper region 5, 19 Diffusion layer 6, 22 Protective insulating film 7, 23 Mask insulating film 8 First 9 Side wall insulating film 10 Second ion 11 Third ion 12 Fourth ion 13 Well 14 Trench 15 Buried insulating film 17 Gate oxide film 18 Gate electrode 25 Channel stopper region

Claims (7)

[Claims] 1. A semiconductor substrate immediately below an insulating film formed in a predetermined pattern on a surface of a semiconductor substrate, wherein a high-concentration impurity is introduced at a position located in a central region of the pattern, wherein the high-concentration impurity is introduced. A low-concentration impurity is introduced into a peripheral region of the region into which the impurity is introduced. 2. The method according to claim 1, wherein the insulating film formed in the pattern shape is an element isolation insulating film formed in an element isolation region of the semiconductor device, and the region into which the high-concentration impurities and the low-concentration impurities are introduced is a channel stopper region. The semiconductor device according to claim 1, wherein: 3. The high concentration impurity and the low concentration impurity are boron impurities, and the concentration of the high concentration impurity is 10 ¹⁸
The semiconductor device according to claim 1, wherein the semiconductor device is set to be at least atoms / cm ³ . 4. The semiconductor device according to claim 1, wherein a concentration ratio between the high concentration impurity and the low concentration impurity is set to be 10 ² or more. 5. The semiconductor device according to claim 1, wherein said high concentration impurity and said low concentration impurity are phosphorus impurities. 6. A step of forming an oxidation-resistant mask insulating film having a predetermined opening on a surface of a semiconductor substrate, and a first ion implantation for low-concentration impurities into the surface of the semiconductor substrate through the opening. And forming a sidewall insulating film on the side wall of the opening after the first ion implantation, and using the mask insulating film and the sidewall insulating film as an ion implantation mask to form a second Ion-implanting, and after removing the sidewall insulating film, thermally oxidizing the semiconductor substrate in the opening using the mask insulating film as an oxidation mask to form an element isolation insulating film. A method for manufacturing a semiconductor device. 7. A step of forming an oxidation-resistant mask insulating film having a predetermined opening on a surface of a semiconductor substrate; and forming a sidewall insulating film on a side wall of the opening to form the mask insulating film and the side wall. Performing a second ion implantation for high-concentration impurities using the insulating film as an ion implantation mask; and removing the sidewall insulation film, and then removing the low-concentration impurities on the surface of the semiconductor substrate through the opening. Manufacturing a semiconductor device, comprising: performing a first ion implantation; and thermally oxidizing a semiconductor substrate in the opening using the mask insulating film as an oxidation mask to form an element isolation insulating film. Method.