JPH11154848A - Flit-flop - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a flip-flop which internally solves clock delays and prevents data-through from occurring. SOLUTION: In a flip-flop that consists of a master flip-flop (inverters 1 and 2 and switches 5 and 6), a slave flip-flop (inverters 3 and 4 and switches 7 and 8) and a latch hold designating circuit (clock buffer 9), even when a clock delays against data, data through does not occur when the latch hold designating circuit designates that a holding state with respect to respective flip-flops is longer than a latch state and that both become a holding state. Thus it is not necessary to arrange a delay element externally and to take into consideration those delay relations, resulting in facilitating of design.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a flip-flop, and more particularly, to a flip-flop suitable for use in an LSI.

[0002]

2. Description of the Related Art FIG. 8 shows a conventional flip-flop of this type, and FIG. 9 shows an example of a configuration in which the flip-flop is used for an LSI. The master flip-flop and the slave flip-flop connect the pair of inverters 91 and 92 and the inverters 93 and 94 in a feedback manner, respectively, and cut off the switches 95 and 97 that enable external input to each loop and disconnect each loop. Switches 96 and 98 are provided, and a D input is supplied to a loop on the side of the master flip-flop. An output of the loop on the side of the master flip-flop is input to a loop on the side of the slave flip-flop. The output of the loop on the flip-flop side is output to the outside as a Q output.

The clock input is through and the switch 9
6 and a switch 97 and inverted by an inverter 99 and supplied to a switch 95 and a switch 98. In such a configuration, when the clock input is high, the loop of the master flip-flop is closed and the external input is shut off, and the slave flip-flop is externally input and the loop is opened. Therefore, a hold instruction is given to the master flip-flop and a latch instruction is given to the slave flip-flop.

When the clock input is low, the loop of the slave flip-flop is closed and the external input is cut off, and the master flip-flop is externally input and the loop is opened. Therefore, a hold instruction is given to the slave flip-flop and a latch instruction is given to the master flip-flop.

That is, the latch and hold of these master flip-flop and slave flip-flop are appropriately inverted based on one clock signal.

By the way, assuming a shift register,
A plurality of such flip-flops with synchronized clocks will be connected in series. However, if the delay of the signal on the clock line cannot be ignored due to the increase in wiring resistance and wiring capacitance due to miniaturization as in LSI, the clock may enter later than the data, which may cause data through. . Therefore, as shown in FIG. 9, the flip-flops 100 are connected in series, and the delay lines 101 are interposed in the data lines.

[0007]

In the above-mentioned conventional flip-flop, the delay element 101 is connected to the data line.
The problem is that the design is cumbersome, and there is still a need to verify after the layout, and if there is an error in the verification, it is necessary to start over from the logical design again. was there.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a flip-flop capable of internally eliminating clock delay and preventing data through.

[0009]

According to a first aspect of the present invention, there is provided a flip-flop comprising a master flip-flop and a slave flip-flop which perform a latch operation and a hold operation by a clock input. While generating its inverted output, the same clock input is output as a hold instruction signal in the master flip-flop and a latch instruction signal in the slave flip-flop,
When outputting the inverted output as a latch instruction signal in the master flip-flop and a hold instruction signal in the slave flip-flop, a latch / hold instruction circuit for making the state of the hold instruction longer than the state of the latch instruction is provided.

[0010] In the first aspect of the present invention, the master flip-flop and the slave flip-flop are configured by connecting a pair of inverters in a feedback manner in a loop, and the latch-hold instructing circuit is provided for the clock input. And outputs the same clock input as a hold instruction signal in the master flip-flop and a latch instruction signal in the slave flip-flop while generating an inverted output, and outputs an inverted output to the latch instruction signal in the master flip-flop and the slave flip-flop. Output as a hold instruction signal in the loop. However, the latch hold instruction circuit makes the hold instruction state longer than the latch instruction state.

For example, the fact that the hold instruction state is long in the master flip-flop means that the master flip-flop continues the hold instruction state even during the period of transition between the latch instruction state and the hold instruction state in the slave flip-flop. No slew occurs.

According to a second aspect of the present invention, there is provided a flip-flop comprising a master flip-flop and a slave flip-flop which perform a latching operation and a holding operation in response to a clock input, while generating an inverted output of the clock input. In outputting the clock input as the hold instruction signal in the master flip-flop and the latch instruction signal in the slave flip-flop, and outputting the inverted output as the latch instruction signal in the master flip-flop and the hold instruction signal in the slave flip-flop, And a latch / hold instructing circuit for generating a state in which a hold instruction is given to both flip-flops.

[0013] In the second aspect of the present invention, the latch / hold instruction circuit outputs a latch instruction signal and a hold instruction signal that are respectively inverted for each of the master flip-flop and the slave flip-flop. Will be. However, the latch hold instruction circuit generates a state in which a hold instruction is given to both flip-flops, so that no data through occurs.

Further, according to a third aspect of the present invention, in the flip-flop according to any one of the first and second aspects, the latch and hold instruction circuit includes two pairs of clock signals which are in an inverting relationship with each other. Generate one of them while the other performs two inversions during one settling period, and one pair issues a latch instruction and a hold instruction for the master flip-flop, and the other pair produces a slave flip-flop. And a latch instruction and a hold instruction for the loop.

According to the third aspect of the present invention, the latch and hold instruction circuit generates two pairs of clock signals which are in a mutually inverted relationship. Since one of them inverts twice during the other's stable period, one pair issues a latch instruction and a hold instruction for the master flip-flop, and the other pair issues a latch instruction and a hold instruction for the slave flip-flop. Is performed, a period that overlaps each other occurs. Then, both flip-flops enter the hold instruction state, and the hold instruction state becomes longer than the latch instruction state.

According to a fourth aspect of the present invention, in the flip-flop according to the third aspect, the latch and hold instruction circuit includes an inverter connected in series in four stages, and an input of a first stage and an output of a last stage are connected to each other. A hold instruction signal and a latch instruction signal of the master flip-flop that provide a long hold instruction as an AND output and a NAND output while being used as a set of inputs, and an AND output using the first stage output and the three stage output as one set of inputs And a NAND output to generate a latch instruction signal and a hold instruction signal for the slave flip-flop.

In the invention according to claim 4 configured as described above, a system in which inverters are connected in series in four stages and an AND output is provided as a set of input of the first stage and output of the last stage, and There is a system that takes the AND output as a set of inputs using the output of (1) and the output of the three stages, and it can be seen that the latter repeats the inversion twice within the former stable period. Therefore,
If the former AND output and NAND output are used, a hold instruction signal and a latch instruction signal of the master flip-flop that give a longer hold instruction can be obtained, and if the latter AND output and NAND output are used, the slave repeats inversion between them. It can be a latch instruction signal and a hold instruction signal of the flip-flop.

According to a fifth aspect of the present invention, in the flip-flop according to the third aspect, the latch and hold instruction circuit includes a delay element connected in series in two stages, and inputs and outputs the input and output of the serial circuit. The hold instruction signal and the latch instruction signal of the master flip-flop that give a long hold instruction as an AND output and a NAND output while the output of the delay element at the first stage is inverted through and output to latch the slave flip-flop. An instruction signal and a hold instruction signal are used.

In the invention according to claim 5, the delay element is connected in series in two stages and the input and output of the delay element are AND-outputted, and the delay element is output in the first stage. Then, since it is known that the latter repeats inversion twice during the former stable period, the former can obtain an AND output and a NAND output to provide a longer hold instruction, so that the hold instruction signal and the latch instruction signal of the master flip-flop can be obtained. The latter can be inverted as a through signal and output to provide a latch instruction signal and a hold instruction signal for the slave flip-flop.

Further, according to a sixth aspect of the present invention, in the flip-flop according to the third aspect, the latch and hold instruction circuit cross-connects two NOR elements and connects one of the remaining inputs to one of the remaining inputs. Supplies a clock input and supplies the same clock input via an inverter to the other, and uses one of the outputs and the inverted output to use one of the sets to hold the master flip-flop with a long hold instruction signal in a hold state. And a latch instruction signal, and the other set is output to the slave flip-flop as a latch instruction signal and a hold instruction signal.

Also in the invention according to claim 6, the two NOR elements are cross-connected, a clock input is supplied to one of the remaining inputs, and an inverter is supplied to the other. By supplying the same clock input via the above, a relationship is established in which the other repeats the inversion twice during the stable period while the respective inversions are repeated. One set can output a long hold instruction signal and a latch instruction signal in a long hold state to the master flip-flop, and the other set can output a latch instruction signal and a hold instruction signal to the slave flip-flop.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a flip-flop according to an embodiment of the present invention.

In the figure, a master flip-flop and a slave flip-flop respectively connect a pair of inverters 1 and 2 and inverters 3 and 4 in a feedback manner in a loop form, and have switches 5 and 5 which enable external input to each loop. 7 and switches 6 and 8 for disconnecting each loop, and supplies a D input to the loop on the master flip-flop side and outputs the output of the loop on the master flip-flop side to the loop on the slave flip-flop side. And outputs the output of the loop on the slave flip-flop side as a Q output to the outside.

The clock input is input to a clock buffer 9 to form two independent clocks e and g, and to connect inverters 9a and 9b to these to form clocks f and h having opposite polarities. , Switches 5 to 8. The clock e is supplied to the switch 8 as a hold instruction signal for the slave flip-flop, and the inverted clock f is supplied to the switch 8 as a latch instruction signal for the slave flip-flop.
The clock g is supplied to the switch 5 as a latch instruction signal of the master flip-flop, and a clock h, which is an inverted output thereof, is supplied to the switch 6 as a hold instruction signal of the master flip-flop.

FIG. 2 shows an example of the configuration of the clock buffer 9. In the case of the clock buffer 9, the inverters 11 to 14 are connected in series, an external clock input is supplied to the first-stage inverter 11, and the clock input and the output of the last-stage inverter 14 are connected to an AND circuit 15 And its output is used as a clock e. The output f of the NAND circuit is shown in the drawing to mean the output inverted by the inverter 9a. Also, the inverted output of the first-stage inverter 11 and the three-stage inverter 13
Is output to the AND circuit 16 and the output is used as the clock g. In this example, the output h of the NAND circuit is shown in the drawing in the sense of the output inverted by the inverter 9b.

FIG. 3 shows a timing chart of the clock buffer 9, wherein the inverted output of the inverter 11 is point a, the inverted output of the inverter 12 is point b, the inverted output of the inverter 13 is point c, and the inverted output of the inverter 14 is shown. Is displayed as point d.

As shown in the figure, by making the delayed clock d inverted in four stages and the original clock x AND, the clock e having a shorter high-level period in the original clock x can be obtained. can get. In addition, the clock a of the output of the first-stage inverter 11 and the clock c of the output of the third-stage inverter 13 which are sequentially delayed are ANDed, so that the original clock x is inverted with respect to the original clock x. G whose polarity is inverted between the rising edge of the clock e and the rising edge of the clock e output from the AND circuit 15
Is obtained.

The clocks e and g are mutually inverted twice during the stable period of one of the clocks e and the clocks f and h are inverted by the inverters 9a and 9b, respectively. As a result, a latch instruction and a hold instruction for the master flip-flop are issued, and a latch instruction and a hold instruction for the slave flip-flop are issued. That is, the hold instruction period is longer than the latch instruction period, and the hold states overlap, so that data through does not occur.

Next, FIG. 4 shows another example of the configuration of the clock buffer 9. In the case of this clock buffer 9,
The two delay elements 21 and 22 are connected in series, and an external clock input is supplied to the delay element 21 at the preceding stage.
The clock input and the output of the delay element 22 at the subsequent stage are supplied to the AND circuit 23, and the output is used as the clock e. The output f of the NAND circuit is shown in the drawing to mean the output inverted by the inverter 9a. Further, the output of the delay element 21 in the preceding stage is inverted by the inverter 24 to obtain the clock g. Also in this example, the output h of the NAND circuit is shown in the drawing in the sense of the output inverted by the inverter 9b.

FIG. 5 is a timing chart of the clock buffer 9, in which the output of the delay element 21 is indicated as point b and the output of the delay element 22 is indicated as point d.

As shown in the figure, by setting the clock d delayed in two stages and the original clock x to AND, a clock e having a shorter high-level period in the original clock x can be obtained. Also, two delay elements 2
By inverting the output between 1 and 22 by the inverter 24, the polarity between the rising of the original clock x and the rising of the clock e of the output of the AND circuit 15 while being inverted with respect to the original clock x. An inverted clock g is obtained.

That is, the clock e and the clock g, which are exactly the same as the example shown in FIG. 2, can be obtained. Therefore, the clock e and the clock g are inverted twice each other during the stable period of one of the clocks e and the clocks f and h, which are mutually inverted by the inverters 9a and 9b, respectively. In other words, the latch instruction and the hold instruction for the master flip-flop are issued, and the latch instruction and the hold instruction for the slave flip-flop are issued. That is, the hold instruction period is longer than the latch instruction period, and the hold states overlap, so that data through does not occur.

FIG. 6 shows still another configuration example of the clock buffer 9. This clock buffer 9
In the case of, the outputs of the other NOR elements 31 and 32 are used as one inputs of the two NOR elements 31 and 32 and the delay elements 33 and 34
The clock x is supplied to the other input of one of the NOR elements 31 while the inverter 3 is connected to the other input of the other of the NOR elements 32.
5 is supplied with a clock x. Also in this case, the outputs f and h of the OR circuit are shown in the drawing in the sense of the outputs inverted by the inverters 9a and 9b.

FIG. 7 is a timing chart of the clock buffer 9, in which the inverted output of the inverter 35 is indicated by point a, the output of the delay element 33 is indicated by point d, and the output of the delay element 34 is indicated by point c. . As shown in the figure, clocks e and g, which are exactly the same as the example shown in FIG. 2 in terms of timing, are obtained. Therefore, the clock e and the clock g are inverted twice each other during the stable period of one of the clocks e and the clocks f and h, which are mutually inverted by the inverters 9a and 9b, respectively. In other words, the latch instruction and the hold instruction for the master flip-flop are issued, and the latch instruction and the hold instruction for the slave flip-flop are issued. That is, the hold instruction period is longer than the latch instruction period, and the hold states overlap, so that data through does not occur.

As described above, the master flip-flop (inverters 1 and 2 and switches 5 and 6), the slave flip-flops (inverters 3 and 4 and switches 7 and 8) and the latch / hold instruction circuit (clock buffer 9) for them are provided. In the configured flip-flop,
When the latch hold instruction circuit makes the hold state of each flip-flop longer than the latch state, or instructs both to be in the hold state, the clock is delayed with respect to the data. Also, since data through does not occur, there is no need to arrange a delay element externally, and it is not necessary to consider the delay relationship between them, so that the design becomes easy.

The case where four stages of inverters are used as delay elements has been described above. However, it is obvious that the same operation as described above is performed when there are six stages of inverters or more. Also,
The case where a flip-flop including four sets of inverters and switches is used has been described above.
It is needless to say that other master-slave flip-flops including an OR circuit are also effective.

[0037]

As described above, the present invention can provide a flip-flop capable of inverting a master flip-flop and a slave flip-flop so as not to cause data through.

Further, according to the invention of claim 3,
This can be realized by changing the timing of the clock. Further, according to the invention according to claims 4 to 6, a clock signal having a required timing can be generated with a simple configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram of a flip-flop according to an embodiment of the present invention.

FIG. 2 is a block diagram of a clock buffer in the flip-flop.

FIG. 3 is a timing chart in the clock buffer.

FIG. 4 is a block diagram of a clock buffer in the flip-flop.

FIG. 5 is a timing chart in the clock buffer.

FIG. 6 is a block diagram of a clock buffer in the flip-flop.

FIG. 7 is a timing chart in the clock buffer.

FIG. 8 is a block diagram of a conventional flip-flop.

FIG. 9 is a block diagram of a shift register using a conventional flip-flop.

[Explanation of symbols]

 1-4 Inverter 5-8 Switch 9a, 9b Inverter 11-14 Inverter 15, 16 AND circuit 21, 22 Delay element 23 AND circuit 24 Inverter 31, 32 NOR element 33, 34 Delay element 35 Inverter 9 Clock buffer 91-94 Inverter 95 to 98 switch 99 inverter 100 flip-flop 101 delay element

Claims (6)

[Claims] 1. A flip-flop comprising a master flip-flop and a slave flip-flop, which perform a latch operation and a hold operation in response to a clock input, while generating an inverted output of the clock input and applying the clock input to the master flip-flop. In outputting the hold instruction signal and the latch instruction signal in the slave flip-flop, and outputting the inverted output as the latch instruction signal in the master flip-flop and the hold instruction signal in the slave flip-flop, the state of the hold instruction is changed to the latch instruction. And a latch hold instruction circuit for making the state longer than the state. 2. A flip-flop comprising a master flip-flop and a slave flip-flop which performs a latch operation and a hold operation in response to a clock input, while generating an inverted output of the clock input while applying the same clock input to the master flip-flop. In outputting the hold instruction signal and the latch instruction signal in the slave flip-flop, and outputting the inverted output as the latch instruction signal in the master flip-flop and the hold instruction signal in the slave flip-flop, the flip-flop circuit holds both flip-flops. A flip-flop comprising: a latch-hold instruction circuit for generating an instruction state. 3. The flip-flop according to claim 1, wherein the latch / hold instructing circuit generates two pairs of clock signals that are in an inverting relationship with each other, and these two pairs of clock signals are mutually connected. During one stabilization period, the other performs two inversions, and one pair issues a latch instruction and a hold instruction for the master flip-flop, and the other pair performs a latch instruction and a hold instruction for the slave flip-flop. And a flip-flop. 4. The flip-flop according to claim 3, wherein the latch and hold instruction circuit includes inverters connected in series in four stages, and performs AND output while using a first stage input and a last stage output as a set of inputs. And a hold instruction signal and a latch instruction signal of the master flip-flop that gives a long hold instruction as a NAND output, and an AND output and a NAND output are generated while using the output of the first stage and the output of the three stages as a set of inputs. A flip-flop comprising a latch instruction signal and a hold instruction signal for the slave flip-flop. 5. The flip-flop according to claim 3, wherein said latch and hold instruction circuit includes a delay element connected in series in two stages, and an AND output and a NAND output while receiving an input and an output of the series circuit as inputs. As the hold instruction signal and the latch instruction signal of the master flip-flop giving the hold instruction for a long time, the output of the first-stage delay element is inverted and output to output the latch instruction signal and the hold instruction signal of the slave flip-flop. A flip-flop characterized by: 6. The flip-flop according to claim 3, wherein the latch and hold instruction circuit cross-connects two NOR elements via a delay element or directly and connects one of the remaining NOR elements to one of the remaining inputs. Supplies a clock input and supplies the same clock input via an inverter to the other, and uses one of the outputs and the inverted output to use one of the sets to hold the master flip-flop with a long hold instruction signal in a hold state. And a latch instruction signal, and the other set is output to the slave flip-flop as a latch instruction signal and a hold instruction signal.