JPH11149279A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce distribution of defective sticking along a gate bus line so as to provide a liquid crystal display device having a uniform display characteristic by providing a plurality of drive circuits supplying voltage based on gradation reference voltage output by a control circuit to switching elements. SOLUTION: Timing signals of signal line drive circuits 9 and gradation display voltage of a liquid crystal panel 8 are supplied from a control circuit 11. Resistance RVref(a)-0, RVref(a)-1,...RVref(d)-3 are provided between the respective gradation reference voltage Vref output terminals of the control circuit 11 and the output terminals of the signal line drive circuits 9. The setting values of the resistance are decided so as to compensate the mean value of differential voltage at every block. Accordingly, the center value of display voltage can be changed at every signal line drive circuit, 9 and against a common electrode voltage value set to be fixed, distribution in plane of sticking generated by the reason of the variation portion due to capacity between gate and drain along a gate bus line can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display (hereinafter, referred to as LCD) using a thin film transistor (hereinafter, referred to as TFT).

[0002]

2. Description of the Related Art FIG. 4 is a diagram showing an equivalent circuit corresponding to one pixel of a conventional TFT-LCD. In FIG. 4, 1
Is a TFT, 2 is a display electrode connected to the drain electrode of the TFT 1, 3 is a common electrode, 4 is a capacitor formed between the display electrode 2 and the common electrode 3 facing each other via a liquid crystal (hereinafter referred to as a liquid crystal capacitance: CLC). Reference numeral 5 denotes a parasitic capacitance between the gate electrode and the drain electrode of the TFT 1 (hereinafter referred to as a gate-drain capacitance:
Cgd), 6 is a gate bus line as a scanning line connected to the gate electrode of TFT1, and 7 is a source bus line as a signal line connected to the source electrode of TFT1.
In the liquid crystal panel of the TFT-LCD, pixels shown in the equivalent circuit diagram of FIG. 4 are formed in a matrix, upper and lower pixels in the figure are connected to each other by source bus lines, and left and right pixels are gate bus lines. Are connected to each other.

FIG. 5 is a diagram showing driving waveforms of a conventional liquid crystal display device, showing a gate voltage Vg, a display voltage Vs, a display electrode voltage Vd, and a common electrode voltage Vcom for turning on or off a TFT. I have. FIG. 6 is a diagram showing a distribution of a variation ΔVgd due to gate-drain capacitance along a gate bus line of a conventional liquid crystal display device. FIG. 7 shows the center value Vs of the display voltage determined by the conventional method.
6 is a diagram showing o, a common electrode voltage Vcom.

Next, the operation of the conventional liquid crystal display device will be described. The TFT 1 is turned on only during the period when the gate voltage Vg input from the scanning line driving circuit via the gate bus line 6 is HI. On the other hand, a display voltage Vs of a desired magnitude is input to the source bus lines 7 from the signal line driving circuit for each source bus line 7. The display electrode voltage Vd reaches the display voltage Vs during the on-period of the TFT1, but at the moment when the TFT1 is turned off, is affected by the gate-drain capacitance Cgd5. Fluctuate. In Expression 1, ΔVg is a potential difference between HI and LOW of the gate voltage Vg. ΔVgd = (Cgd / (Cgd + CLC)) △ ΔVg (Equation 1) The direction of the fluctuation of ΔVgd is a direction of DC decrease regardless of the polarity of the display voltage Vs. This display electrode voltage V
The DC fluctuation of d causes a cracking defect. conventionally,
To compensate for this DC variation, the common electrode voltage Vcom
From the center value Vso of a certain display voltage Vs by ΔVg
It was set to a constant value lower by d.

[0005]

The effective value of the gate-drain capacitance Cgd5 that determines △ Vgd is affected by the difference in the gate voltage delay as the distance from the gate voltage input terminal to the terminal end increases. ΔVg
As shown schematically in FIG. 6, d decreases as the distance from the gate voltage input terminal increases, and has a distribution along the gate bus line 6. That is, in order to compensate for the DC fluctuation of the display electrode voltage Vd caused by ΔVgd, it is ideal to change the common electrode voltage Vcom along the gate bus line 6 as shown in FIG. on the other hand,
The common electrode voltage Vcom is set to be constant as in the prior art,
For example, as shown by the dotted line in FIG.
Is set so as to compensate for the DC fluctuation of the display electrode voltage Vd at the gate input end and the gate output end, so that a kicking failure occurs at the gate input end and the gate output end.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to reduce the distribution of cracking defects along a gate bus line and to obtain a liquid crystal display device having uniform display characteristics. I do.

[0007]

In a liquid crystal display device according to the present invention, a plurality of scanning lines and a plurality of signal lines are arranged in a matrix at intersections, and a first electrode is connected to a scanning electrode by a second electrode. A display unit having a switching element in which a third electrode is connected to the display electrode on the signal line, a first drive circuit connected to the scanning line and supplying a first voltage to the switching element, and a plurality of voltages. A control circuit that outputs a gray level reference voltage of a level, and a plurality of second drive circuits that are connected to the signal lines and supply a second voltage based on the gray scale reference voltage output by the control circuit to the switching element. The effect of the parasitic capacitance between the first electrode and the third electrode of the switching element on the voltage applied to the third electrode varies due to the delay of the first voltage in the wiring direction of the scanning line. Depending on the second drive And supplies a second voltage that is varied central value by a circuit to the switching element. The change in the center value of the second voltage is performed by adjusting the voltage level of the gradation reference voltage output from the control circuit and supplying the adjusted voltage to the second drive circuit.

The adjustment of the voltage level of the gradation reference voltage is performed for each second drive circuit. Further, the adjustment of the voltage level of the gradation reference voltage is performed by adjusting the value of the voltage level corresponding to the gradation reference voltage.

The adjustment of the voltage level of the gray scale reference voltage is performed so that the center value of the second voltage becomes lower as the delay of the scanning line in the wiring direction increases. The gray level reference voltage output from the control circuit is supplied to the second drive circuit via a resistor, so that the voltage level is adjusted.

[0010]

FIG. 1 is a block diagram showing a liquid crystal display according to an embodiment of the present invention. In the figure, only the part of the configuration of the liquid crystal display device that is directly related to the present invention is shown. In the figure, reference numeral 8 denotes a liquid crystal panel as a display unit, in which pixels shown in FIG. 4 are arranged in a matrix at intersections of source bus lines and gate bus lines.
Reference numeral 9 denotes a plurality of signal line driving circuits connected to the liquid crystal panel 8, which are distinguished from each other by (a) to (d). Reference numeral 10 denotes a scanning line driving circuit connected to the liquid crystal panel 8.
Reference numeral 11 denotes a control circuit for synchronizing each signal line drive circuit 9 with the scan line drive circuit 10 to supply a desired display signal to each signal line, and a gradation reference voltage Vr for outputting a gradation reference voltage.
It has an ef output terminal. RVref-0 to RVref are resistors provided between each gradation reference voltage Vref output terminal of the control circuit 11 and each gradation reference voltage Vref input terminal of each signal line drive circuit 9, and each of the individual signal line drive circuits 9 ( a) ~
RVref (a) -0 to RVref corresponding to (d)
(D) It is displayed like -3.

FIG. 2 is an input / output waveform diagram of the signal line driving circuit of the liquid crystal display device according to the embodiment of the present invention. FIG.
FIG. 5 is a diagram showing a center value Vso of a display voltage determined according to the embodiment of the present invention.

Next, the operation will be described. Control circuit 1
From 1, a timing signal necessary to operate the signal line driving circuit 9 and gradation reference voltage levels Vref 0 to Vref 3 for gradation display of the liquid crystal panel 8 are supplied to the signal line driving circuit 9. I have. Here, for the sake of simplicity, a binary display of white and black will be considered. FIG. 2 shows the magnitude relation between the gradation reference voltage levels. In the normally white mode, when displaying black, the signal line driving circuit 9 synchronizes with the timing signal POL shown in FIG.
0 and Vref3 are alternately selected and AC output is performed. In the case of white display, the gray scale reference voltage levels Vref1 and Vref2 are similarly output as an alternating current.

As described above, the center value Vs of the constant display voltage
Optimal common electrode voltage Vc for compensating ΔVgd for o
The om value has a distribution along the gate bus line as schematically shown in FIG. In order to compensate for this distribution, according to the present invention, as shown in FIG. 1, a resistor RVref (a) is provided between each gradation reference voltage Vref output terminal of the control circuit 11 and each gradation reference voltage Vref input terminal of the signal line driving circuit 9. )-
0, RVref (a) -1 ... RVref (d) -3
Is provided. The common electrode voltage Vcom is set to the average value of the optimum common electrode voltage Vcom of the block corresponding to each signal line drive circuit 9. The average value of ΔVgd of the block corresponding to each signal line drive circuit 9 is, as shown in FIG.
(A), Vgd (b), Vgd (c), and Vgd (d). Since the common electrode voltage Vcom is set so as to compensate for △ Vgd (a), it will deviate from the optimum value in other blocks.

Therefore, the resistance value inserted into the gradation reference voltage Vref0 line is represented by RVref (a) -0 <RVref (b) -0 <RVr
ef (c) -0 <RVref (d) -0 is set. Similarly, for the other resistors RVref, (a) <(b) <(c) <(d) is set for each signal line driving circuit 9 at each gradation reference voltage Vref. Since the set value of the resistor in this case can be determined so as to compensate for the average value of ΔVgd for each block, the center value Vso of the display voltage is changed for each signal line driving circuit 9 as shown in FIG. It is possible to reduce the in-plane distribution of the noise caused by the variation ΔVgd due to the gate-drain capacitance along the gate bus line with respect to the fixed common electrode voltage Vcom value.

[0015]

Since the present invention is configured as described above, it has the following effects. The effect of the parasitic capacitance between the first electrode connected to the scanning line of the switching element and the third electrode connected to the display electrode on the voltage applied to the third electrode is the first voltage. Since the second voltage whose center value is changed by the second drive circuit is supplied to the switching element in accordance with the fluctuation due to the delay of the scanning line in the wiring direction, the voltage applied to the third electrode is Variations in the effect of the parasitic capacitance can be compensated for, and the distribution of cracking defects in the scanning line wiring direction can be reduced. Also, the change in the center value of the second voltage is performed by adjusting the voltage level of the gradation reference voltage output by the control circuit and supplying the adjusted voltage to the second drive circuit. No adjustments are required.

Further, since the adjustment of the voltage level of the gradation reference voltage is performed for each of the second drive circuits, the distribution of the cracking defect can be reduced for each of the second drive circuits. Further, since the voltage level of the gray scale reference voltage is adjusted by adjusting the value of the corresponding voltage level of the gray scale reference voltage, the voltage level of the gray scale reference voltage can be adjusted with good balance.

The voltage level of the gradation reference voltage is adjusted so that the center value of the second voltage becomes lower in accordance with the increase in the delay of the scanning line in the wiring direction. Variations in the effect of the parasitic capacitance on the applied voltage can be compensated for, and the distribution of cracking defects in the scanning line wiring direction can be reduced. Further, since the gradation reference voltage output from the control circuit is adjusted by being supplied to the second drive circuit via the resistor, the compensation can be performed by determining the set value of the resistor. it can.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a gray scale reference voltage level input to a signal line driving circuit, a timing signal POL, and a display voltage output from the signal driving circuit of the liquid crystal display device according to the embodiment of the present invention.

FIG. 3 is a diagram showing a center value Vso of a display voltage determined in the embodiment of the present invention.

FIG. 4 is an equivalent circuit diagram corresponding to one pixel of a conventional liquid crystal display device.

FIG. 5 is a diagram showing driving waveforms of a conventional liquid crystal display device.

FIG. 6 is a diagram showing a distribution of a variation ΔVgd due to gate-drain capacitance along a gate bus line of a conventional liquid crystal display device.

FIG. 7 is a diagram showing a center value (Vso) of a display voltage and a common electrode voltage (Vcom) determined by a conventional method.

[Explanation of symbols]

1 TFT, 2 display electrode, 3 common electrode, 4
Liquid crystal capacity: CLC, 5 Gate-drain capacity: Cg
d, 6 gate bus lines, 7 source bus lines,
8 liquid crystal panel, 9 signal line drive circuit, 10 scan line drive circuit, 11 control circuit.

Claims (6)

[Claims] 1. A plurality of scanning lines and a plurality of signal lines are arranged in a matrix at intersections, with a first electrode serving as the scanning line, a second electrode serving as the signal line, and a third electrode serving as a display electrode. A display unit having a switching element connected thereto, a first driving circuit connected to the scanning line and supplying a first voltage to the switching element, a control circuit for outputting a gradation reference voltage having a plurality of voltage levels, A plurality of second drive circuits connected to the signal line and supplying a second voltage based on a grayscale reference voltage output by the control circuit to the switching element, and a first electrode of the switching element In response to the effect of the parasitic capacitance between the third electrode and the voltage applied to the third electrode fluctuating due to the delay of the first voltage in the wiring direction of the scanning line, the second driving circuit The center value was changed by A liquid crystal display device, wherein a second voltage is supplied to the switching element. 2. The method according to claim 1, wherein the change of the center value of the second voltage is performed by adjusting the voltage level of the gradation reference voltage output from the control circuit and supplying the adjusted voltage to the second drive circuit. The liquid crystal display device according to claim 1. 3. The method according to claim 2, wherein the adjustment of the voltage level of the gradation reference voltage is performed for each second drive circuit.
The liquid crystal display device as described in the above. 4. The liquid crystal display device according to claim 2, wherein the adjustment of the voltage level of the gray scale reference voltage is performed by adjusting the value of the corresponding voltage level of the gray scale reference voltage. . 5. The method according to claim 1, wherein the adjustment of the voltage level of the gray scale reference voltage is performed such that the center value of the second voltage becomes lower as the delay of the scanning line in the wiring direction increases. The liquid crystal display device according to claim 2. 6. The voltage level of the gray scale reference voltage output from the control circuit is adjusted by being supplied to a second drive circuit via a resistor.
The liquid crystal display device according to claim 1.