JPH11142885A - Array substrate for liquid crystal display device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure electric connection between a transparent pixel electrode and a source electrode by preventing the transparent pixel electrode from being discontinuous. SOLUTION: A Mo film 28A being a material of a source electrode S is formed at >=150 deg.. Thereby the average surface roughness Ra of the source electrode S becomes <=1.5 nm. Since the average surface roughness Ra is reduced, a normally tapered contact aperture 29h can be formed on a protection insulating film 29 formed on the electrode S. Consequently both the electrode S and a transparent pixel electrode 30 can be connected through the aperture 29h without being discontinuous.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array substrate for a liquid crystal display device and a method for manufacturing the same, and more particularly, to an active matrix type array substrate for a liquid crystal display device and a method for manufacturing the same.

[0002]

2. Description of the Related Art As a liquid crystal display device for displaying characters such as characters and figures, a gate electrode for a scanning line and a source / drain electrode for a signal line intersect, and a matrix type in which each of the intersections is a pixel. Things are used.
An active matrix type liquid crystal display device including a driving switching element corresponding to each pixel is often used. Typical examples of such a switching element include a thin film transistor (hereinafter abbreviated as TFT) and a non-linear resistance element (MIM). Among them, the TFT has excellent high-speed response and is suitable for full-color display.

For example, a description will be given of a light transmission type active matrix type liquid crystal display device in which a switch element is arranged for each display pixel. Such an active matrix liquid crystal display device includes an array substrate and a counter substrate. A liquid crystal layer is held between the array substrate and the counter substrate via an alignment film.

In an array substrate, a plurality of signal lines and scanning lines are arranged in a grid on a transparent insulating substrate such as glass, and amorphous silicon (hereinafter a-S) is provided at each intersection.
i: H) is connected. FIG. 6 shows a TFT on this array substrate.
It is a schematic sectional drawing of a part. As can be seen from FIG.
A scanning line 2 or a branch of the scanning line 2 serving as a gate electrode G is formed on an insulating substrate 1 made of glass. That is, the gate electrode G may be on the scanning line 2 or may be on a branched portion.
Further, the gate insulating films 3a and 3b, the semiconductor layer 4, the etching stopper layer 5, the contact layer 6, the pixel electrode 7,
A source electrode S, a drain electrode D, and a protective insulating film 8 are formed. As can be seen from these, the gate electrode G of the TFT constitutes the scanning line 2 and the drain electrode D is electrically connected to a signal line (not shown). Further, the source electrode S is electrically connected to the pixel electrode 7. The pixel electrode 7 is made of a transparent conductive material, for example, ITO.

In order to manufacture such an array substrate, 6 to 8 masks are required. Therefore, to reduce the number of masks, an array substrate having a structure as shown in FIG. 7 is used. That is, the semiconductor layer 25, the contact layer 27, the source S, and the drain D are collectively etched using one mask. Then, a protective insulating film 29 is deposited thereon, and a contact opening 29h is formed in the protective insulating film 29. This contact opening 29h allows the transparent pixel electrode 3
0 and the source electrode S are electrically connected.

On the other hand, a counter electrode made of ITO is disposed on a transparent insulating substrate such as glass on the counter substrate.
If a color display is to be realized, a color filter layer is arranged.

[0007]

In the conventional array substrate manufacturing process, although the number of masks can be reduced, there has been a problem that the contact opening 29h has an inversely tapered shape. FIG. 8 shows the shape of the contact opening 29h.
FIG. 3 is a diagram illustrating only a source electrode S, a protective insulating film 29, and a transparent pixel electrode 30 taken out therefrom. As can be seen from FIG. 8A, in a normal state, the contact opening 29h has a forward tapered shape. Thus, the contact opening 29h
Has a forward tapered shape, the source electrode S and the transparent pixel electrode 30 can contact with each other without any break. On the other hand, as can be seen from FIG. 8B, in a defective state, the contact opening 29h has an inversely tapered shape. When the contact opening 29h has an inversely tapered shape as described above, the transparent pixel electrode 30 is stepped, and there is a problem that a contact failure with the source electrode S occurs.

That is, in the manufacturing process of the array substrate, the protective insulating film 29 formed on the source electrode S for electrically connecting the source electrode S and the transparent pixel electrode 30 is formed.
To form a contact opening 29h. BHF (buffered HF) is used as an etchant for forming the contact opening 29h.
This is because the gate insulating film GI composed of the SiOx film 23 and the SiNx film 24 is also etched, and the opening of the electrode extraction pad portion at the end of the scanning line 22 is formed at the same time. Since the gate insulating film GI needs to be etched at the same time, the contact opening 27h for the source electrode S is likely to be over-etched. For this reason, the cross-sectional shape of the contact opening 27h becomes an inversely tapered shape. With such a shape, the transparent pixel electrode 30 connected to the source electrode S through the opening 27h is disconnected, that is, a step break occurs. That is, a poor electrical connection between the transparent pixel electrode 30 and the source electrode S occurs. This is a point defect in the liquid crystal display device, which is not preferable.

Here, an object of the present invention is to provide an array substrate for a liquid crystal display device in which the transparent pixel electrode 30 is not disconnected, and a method of manufacturing the same. In other words, the forward tapered contact opening 2 is formed in the protective insulating film 29.
An object of the present invention is to provide an array substrate for a liquid crystal display device capable of forming 9h and a method for manufacturing the same.

[0010]

In order to solve the above-mentioned problems, an array substrate for a liquid crystal display device according to the present invention comprises: a gate electrode formed from a part of a scanning line formed on a substrate; A gate insulating film, a semiconductor layer formed on the gate insulating film, connected to a part of the semiconductor layer, and formed to be connected to a signal line, a drain electrode, The semiconductor layer is formed so as to be connected to another part on the semiconductor layer, and has an average surface roughness of 1.5 nm.
The following, a source electrode, a protective insulating film formed on the drain electrode and the source electrode, and connected to the source electrode through a contact opening formed in the protective insulating film, And a transparent pixel electrode.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS According to the present invention, a Mo film forming a source electrode has an average surface roughness Ra of 1.5 nm or less, so that a protective insulating film formed on the source electrode has a forward tapered shape. A contact opening is formed to prevent a step from occurring in a transparent pixel electrode connected to a source electrode through the contact opening. This will be described in more detail below with reference to the drawings.

FIGS. 1 to 5 are cross-sectional views showing the steps of manufacturing an array substrate for a liquid crystal display device according to an embodiment of the present invention. These figures show, in particular, a schematic cross section of a protective film type inverted stagger type TFT portion.

First, as can be seen from FIG. 1, a MoW film 22A is deposited on a glass substrate 21 to a thickness of 300 nm by magnetron sputtering. The MoW film 22A is subjected to photolithography using a first mask to form a scanning line 22 which also functions as a gate electrode G.

Next, as can be seen from FIG. 2, Si is formed by a plasma chemical vapor deposition (CVD) method.
Ox film 23, SiNx film 24, a-Si: H film 25A,
Four layers of the SiNx film 26A are continuously deposited. Of these, the SiOx film 23 and the SiNx film 24 form the gate insulating film GI. Next, the etching stopper layer 26 is formed by patterning the uppermost SiNx film 26A at this time using the second mask. The SiOx film 23 may be a SiO ₂ film formed by a thermal CVD method or a silicon oxynitride film formed by a plasma CVD method.

Next, as can be seen from FIG. 3, a pretreatment is performed on the array substrate for the intermediate liquid crystal display device. Subsequently, an n + a-Si: H film 27A serving as a source / drain electrode contact is deposited by a plasma CVD method. further,
A Mo film 28A made of molybdenum to be a source / drain electrode and a signal line is deposited by magnetron sputtering. At this time, the deposition temperature of the Mo film 28A is 2
The temperature was set to 00 ° C. In order to reduce Ra of the Mo film 28A,
It is effective to increase the film forming temperature. That is, 1
By raising the temperature to 50 ° C. or higher, preferably 170 ° C. or higher, Ra of the Mo film 28A is set to 1.5 n over the entire surface of the substrate.
m or less. By reducing Ra in this way, it is possible to form a contact opening 29h having a favorable tapered cross section in the protective insulating film 29, as described later. As another method, the film formation temperature is set to 1
When the temperature is lower than 50 ° C., as a pretreatment for forming a protective insulating film 29 described later, which is an upper layer of the Mo film 28A, a process of oxidizing the surface with ozone and removing the oxide by washing with water is performed by the Mo film 28A. Is effective in reducing Ra of the above. Note that the Mo film 28A may be formed from molybdenum, or may be formed from an alloy mainly containing molybdenum. Molybdenum-based alloys include molybdenum, tungsten, tantalum, chromium, aluminum,
Alternatively, a metal to which copper or the like is added is conceivable. These molybdenum or molybdenum-based alloys are resistant to the HCl etchant, and can be easily processed while maintaining the selectivity with the contact layer 27 as the underlying film. Also, the specific resistance is sufficiently small. Next, Mo
The film 28A, the n + a-Si: H film 27A and the a-Si: H film 25A are simultaneously patterned using a third mask. Thereby, the source electrode S, the drain electrode D,
A contact layer 27, a semiconductor layer 25, and a signal line (not shown) are formed.

Next, as can be seen from FIG.
The protective insulating film 29 made of SiNx is
nm. This protective insulating film 29 made of SiNx
Forms two layers by changing the conditions of CVD. This is because when the protective insulating film 29 is etched, the contact opening 2
It is necessary to make 9h into a tapered shape. In the present embodiment, by changing the distance between the electrodes, which is one of the film forming conditions,
Two-layer films having different etching rates of BHF are formed.
That is, the shape of the contact opening 29h is controlled by making the etching rate of the lower protective insulating film 29b lower than that of the upper protective insulating film 29a. That is, the shape of the contact opening 29h is formed into a desired shape due to a difference in etching rate between the upper protective insulating film 29a and the lower protective insulating film 29b. In this embodiment, the upper protective insulating film 29a is formed to have a thickness of 50 nm, and the lower protective insulating film 29b is formed to have a thickness of 25 nm.
0 nm is formed.

Next, as can be seen from FIG. 5, the contact opening 2 is formed in the protective insulating film 29 using an etching solution BHF.
9h is formed. Although not clear from the figure, at this time, the gate insulating film GI is etched to form openings of the electrode extraction pad portion at the ends of the signal lines (not shown) and the scanning lines 22. That is,
In addition to the protective insulating film 29, the gate insulating film GI of SiO
The x film 23 and the SiNx film 24 are etched. Next, an ITO film 30A is formed, and this is patterned to form a transparent pixel electrode 30 serving as a display electrode. As an etchant for the ITO film 30A, hydrochloric acid (H
A mixed solution containing Cl) or hydrochloric acid is used. ITO film 30
The reason why these are used as the etching solution of A is to enhance the etching resistance of the source electrode S and the drain electrode D made of molybdenum when the etching solution penetrates through cracks or the like of the protective insulating film 29. That is, normally, a diluted aqua regia is used for etching the ITO film. If the diluted aqua regia infiltrates the protective insulating film 29, molybdenum is etched, and this is to be avoided. Thus, the array substrate is completed.

As described above, according to the array substrate according to the present embodiment, the contact opening 29h can be formed in a tapered shape, so that the transparent pixel electrode 30 can be brought into contact with the source electrode S without any step breakage. Can be. That is, since the average roughness Ra of the surface of the source electrode S is 1.5 nm or less, when the protective insulating film 29 is etched to form the contact opening 29h, the contact opening 2h is formed.
9h can be forward tapered. Table 1 shows the relationship between the surface roughness Ra of the source electrode S and the cross-sectional shape of the contact opening 29h.

[0019]

[Table 1]

As can be seen from Table 1, the source electrode S
Ra usually has a distribution in the substrate, and is 0.8 to 2.2.
It has a width of nm. Surface roughness Ra of the source electrode S
Is 1.5 nm or less, the contact opening 29h
Can have a forward tapered shape. On the other hand, Ra
Is 1.8 or more, it can be seen that the shape of the contact opening 29h has an inversely tapered shape. In the present embodiment, the source electrode S is formed by etching the Mo film 28A. Therefore, by setting the Ra on the surface of the Mo film 28A to 1.5 nm or less, the shape of the contact opening 29h can be made forward tapered.

To improve Ra of the material surface of the source electrode S,
For one, it is effective to raise the film forming temperature of the material of the source electrode S. That is, the Mo film 28A is heated to 150 ° C.
When formed at the above temperature, Ra of the Mo film 28A becomes:
It can be suppressed to 1.0 nm or less over the entire surface of the substrate. As another method, Ra can also be reduced by a method of removing the surface layer of the material of the source electrode S after oxidation as a pretreatment for forming the protective insulating film 29. That is, by removing the surface layer of the Mo film 28A before the formation of the protective insulating film 29, Ra can be reduced.

Further, two protective insulating films 29 are formed, and the etching rate of the lower protective insulating film 29b is made lower than the etching rate of the upper protective insulating film 29a in the protective insulating film 29. Therefore, contact opening 2
The forward taper shape of 9h can be controlled. That is, a contact hole 29h having a desired shape can be formed by using a difference in etching speed between the upper protective insulating film 29a and the lower protective insulating film 29b.

The present invention is not limited to the above embodiment, but can be variously modified. For example, the protective insulating film 29 does not necessarily have to have a two-layer structure, and may have a single layer.
Further, it may have a three-layer, four-layer structure.

[0024]

As described above, according to the present invention, by setting the average surface roughness of the source electrode material to 1.5 nm or less, the contact opening formed in the protective insulating film on the source electrode can be formed. It can have a forward tapered shape, and a poor electrical connection between the source electrode and the transparent pixel electrode can be avoided.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a part of a manufacturing process of an array substrate according to an embodiment of the present invention.

FIG. 2 is a sectional view showing a part of the manufacturing process of the array substrate according to one embodiment of the present invention.

FIG. 3 is a sectional view showing a part of the manufacturing process of the array substrate according to one embodiment of the present invention.

FIG. 4 is a sectional view showing a part of the manufacturing process of the array substrate according to one embodiment of the present invention.

FIG. 5 is a sectional view showing a part of the manufacturing process of the array substrate according to the embodiment of the present invention.

FIG. 6 is a cross-sectional view showing the structure of a conventional array substrate.

FIG. 7 is a sectional view showing the structure of another conventional array substrate.

FIG. 8 is a diagram showing a normal state and a defective state of a contact opening formed in a protective insulating film.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 21 Glass substrate 22 Scan line 23 SiOx film 24 SiNx film GI Gate insulating film 25 Semiconductor layer 26 Stopper layer 27 Contact layer 29 Protective insulating film 30 Transparent pixel electrode G Gate electrode S Source electrode D Drain electrode

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kiyotsugu Mizouchi 50, Amebe, Yobe-ku, Himeji-shi, Hyogo Prefecture Inside the Higashishiba Himeji Plant, Inc. Higashishiba Himeji Factory Co., Ltd.

Claims (10)

[Claims] A gate electrode formed from a part of a scanning line formed on a substrate; a gate insulating film formed on the gate electrode; a semiconductor layer formed on the gate insulating film; A drain electrode connected to a part on the semiconductor layer, and formed to connect to a signal line; and a drain electrode formed to connect to another part on the semiconductor layer,
And a source electrode having an average surface roughness of 1.5 nm or less, a protective insulating film formed on the drain electrode and the source electrode, and a contact opening formed in the protective insulating film. hand,
An array substrate for a liquid crystal display device, comprising: a transparent pixel electrode connected to the source electrode. 2. The array substrate according to claim 1, wherein the source electrode is made of a high melting point metal. 3. The array substrate for a liquid crystal display device according to claim 1, wherein said source electrode is made of molybdenum or an alloy mainly composed of molybdenum. 4. The transparent pixel electrode is formed by selectively etching an ITO film with hydrochloric acid or a mixed solution containing at least hydrochloric acid. Item 4. An array substrate for a liquid crystal display device according to any one of items 3. 5. The method according to claim 1, wherein the protective insulating film includes at least an upper protective insulating film and a lower protective insulating film, and the etching rate of the upper protective insulating film is equal to the etching rate of the lower protective insulating film. The array substrate for a liquid crystal display device according to claim 1, wherein the array substrate is configured to be faster than the speed. 6. A step of forming a scanning line on a substrate, using a part of the scanning line as a gate electrode, forming a gate insulating film on the gate electrode, and forming a semiconductor layer on the gate insulating film. Forming a conductive film having an average surface roughness of 1.5 nm or less on the semiconductor layer; and selectively etching the conductive film to connect the signal line to the signal line. Forming a drain electrode; forming a source electrode by selectively etching the conductive film; forming a protective insulating film on the drain electrode and the source electrode; Forming a contact opening in the protective insulating film; and forming a transparent pixel electrode connected to the source electrode through the contact opening on the protective insulating film. The liquid crystal display device for an array substrate manufacturing method that. 7. The array substrate according to claim 6, wherein the conductive film is formed of a high melting point metal. 8. The conductive film is made of molybdenum or an alloy mainly containing molybdenum.
A method for manufacturing an array substrate for a liquid crystal display device according to claim 7. 9. The step of forming the transparent pixel electrode includes: forming an ITO film on the protective insulating film; and selectively etching the ITO film with hydrochloric acid or a mixed solution containing at least hydrochloric acid. 9. The method for manufacturing an array substrate for a liquid crystal display device according to claim 6, further comprising the steps of: 10. The step of forming the protective insulating film includes: forming at least a lower protective insulating film on the drain electrode and the source electrode; and forming the lower insulating film on the lower protective insulating film. 10. The method according to claim 6, further comprising: forming an upper protective insulating film having a higher etching rate than the protective insulating film on the side. Production method.