JPH11126500A - Eeprom - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize an EEPROM which can shorten the inspection time in the case of confirming that the data of all addresses are in the erased state. SOLUTION: In the case of confirming that the data of all addresses are all in the erased state, a row decoder control signal 19 and column decoder control signal 22 at the time of inspection are brought to be at a low level. Thereby, the row decoder 23 selects all word lines 1, 2 simultaneously and a column decoder 24 selects all bit lines 11 simultaneously. Thus, all memory cells are selected. If there is even one memory transistor 7 whose data is not erased, the output of a current detection type sense amplifier (not shown) varies. Accordingly, only one readout operation can inspect whether the data of all addresses is erased or not.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an EEPROM (Electrically Erasable / Writable ROM).

[0002]

2. Description of the Related Art In recent years, the inspection time has increased due to the trend of increasing the capacity of memories. Since the inspection equipment of the EEPROM is expensive, shortening the inspection time is an essential issue. Hereinafter, a conventional EEPROM will be described. FIG.
FIG. 1 is a diagram showing a circuit example of a conventional EEPROM. In FIG. 3, 25 and 26 are word lines, 27 and 28 are column gate control signals, 29 is a high voltage N-channel MOS transistor for address selection, 30 is a high voltage N-channel MOS transistor for bit selection, 31 is a memory cell transistor, 32 is an N-channel MOS transistor for extracting the source line of the memory cell transistor 31 to the ground potential; 33 is a gate control signal of the N-channel MOS transistor 32 for extracting the source line of the memory cell transistor 31 to the ground potential; Line, 35 is a bit line, 36 is a memory portion (memory cell) for one address composed of a transistor group, and 37 is a high breakdown voltage N-channel MO.
A column gate composed of S transistors, 38 is a page line read bias control signal, 39 and 40 are bit line read bias control signals, 41 and 42 are row decoder control signals, 43 and 44 are column decoder control signals, 45
Is a row decoder, and 46 is a column decoder. In addition,
FIG. 3B shows a row decoder 45 connected to the word lines 25 and 26 in FIG. 3A and a column decoder 4 which outputs column gate control signals 27 and 28 to a column gate 37.
6 is shown.

In this conventional EEPROM, a row decoder 45 outputs signals obtained by inverting input row decoder control signals 41 and 42 to word lines 25 and 26, and a column decoder 46 outputs a column decoder control signal 4
Column gate control signal 2
7, 28 are output. Each of the bit lines 35 is connected to a current detection type sense amplifier (not shown) via a column gate 37. Also,
Each page line 34 is connected to a read page line bias circuit (not shown) via a column gate 37. In the memory section 36 for one address, the high voltage N-channel MOS transistor 30 for bit selection is used to select the memory cell transistor 31 for each bit. By using one transistor 31 each, it functions as a 1-bit memory.

FIG. 4 is a signal waveform diagram of each part at the time of a read operation of the EEPROM of FIG.
1, 42, column decoder control signals 43, 44, word line 25, 26 signal and column gate control signal 27,
28 is shown. The operation of this conventional EEPROM will be described below. First, at the time of a memory read operation, a memory cell for each address is selected by the row decoder 45 and the column decoder 46. Then, the voltage is applied to the memory cell transistor 31 by the current detection type sense amplifier connected to the bit line 35 through the column gate 37.
And the value of the drain current of the memory cell transistor 31 changes according to the write data of each bit. As a result, the output voltage of the current detection type sense amplifier changes, and as a result, data is determined as “0” or “1”.

[0005]

However, in the above-described conventional configuration, an inspection for confirming that the drain current of all the memory cell transistors 31 does not flow at the time of the read operation, that is, that all the data of all the addresses are in the erased state, is performed. When performing this operation, the data read operation must be sequentially performed for all the addresses, and there has been a problem that the inspection time becomes longer.

The present invention solves the above-mentioned conventional problems, and can reduce the inspection time when confirming that all data at all addresses are in an erased state.
It aims to provide OM.

[0007]

In order to achieve this object, an EEPROM of the present invention comprises a plurality of bit lines and a plurality of word lines provided at intersections of a plurality of bit lines and a plurality of word lines selected by each word line. A memory cell, a current detection type sense amplifier connected to each bit line via each column gate for reading data of the memory cell, a column decoder for selecting a bit line by controlling the column gate, and a word line. An EEPROM having a row decoder to be selected, wherein a column decoder is capable of simultaneously selecting all bit lines, and a row decoder is capable of simultaneously selecting all word lines.

With this configuration, at the time of inspection for confirming that all data at all addresses are in the erased state, the column decoder simultaneously selects all bit lines and the row decoder simultaneously selects all word lines. Thus, all the memory cells are selected, and if there is at least one memory cell from which data has not been erased, the output of the current detection type sense amplifier changes. Therefore, it is possible to check whether or not all the data of all the addresses have been erased by one read operation.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration of an EEPROM according to an embodiment of the present invention. In FIG. 1, 1 and 2 are word lines, 3 and 4 are column gate control signals, 5 is a high voltage N-channel MOS transistor for address selection, 6 is a high voltage N-channel MOS transistor for bit selection, 7 is a memory cell transistor, 8 is an N-channel MOS transistor for extracting the source line of the memory cell transistor 7 to the ground potential;
Is a gate control signal of the N-channel MOS transistor 8 for pulling out the source line of the memory cell transistor 7 to the ground potential, 10 is a page line, 11 is a bit line, and 12 is a memory unit for one address composed of a transistor group (memory cell). ), 13 are column gates composed of high voltage N-channel MOS transistors, 14 is a page line read bias control signal, 15 and 16 are bit line read bias control signals, 17 and 18 are normal row decoder control signals, 19 Is a row decoder control signal at the time of inspection for simultaneously selecting all word lines 1 and 2, 20 and 21 are column decoder control signals at normal time, and 22 is all bit lines 11
And a column decoder control signal at the time of inspection for simultaneously selecting the page line 10, 23 is a row decoder, and 24 is a column decoder. FIG. 1 (b) is the same as FIG.
Row decoder 23 connected to the word lines 1 and 2, and a column decoder 24 that outputs column gate control signals 3 and 4 to the column gate 13.

The EEPROM of this embodiment has a row decoder 23 and a column decoder 24 which are different from the conventional EEPROM shown in FIG. 3 in other configurations. Each of the row decoder 23 and the column decoder 24 includes a plurality of NAND (NAND) circuits, and the NAND circuits include, for example, a plurality of N-channel MOS transistors. The row decoder control signals 17 and 18 in the normal state are input to one input of each NAND circuit constituting the row decoder 23, and the row decoder control signal 19 in the common test is input to the other input of each NAND circuit. The output of each NAND circuit is supplied to the word lines 1 and 2. Also, column decoder control signals 20 and 21 are input to one input of each NAND circuit constituting the column decoder 24, respectively, and the other input of each NAND circuit is connected to the column decoder control signal 2 at the time of common inspection.
2 is input, and the output of each NAND circuit is supplied to the column gate 13 as column gate control signals 3 and 4.

FIG. 2 is a signal waveform diagram of each part at the time of a read operation at the time of inspection for confirming that all data at all addresses of the EEPROM of FIG. 1 are in an erased state. 18, column decoder control signals 20 and 21 during normal operation, row decoder control signal 19 during inspection, column decoder control signal 22 during inspection, signals of word lines 1 and 2, and column gate control signals 3 and 4. The control signals 17, 18, 20, 21 during the inspection
Becomes constant at a high level.

Regarding the EEPROM of this embodiment,
The operation will be described below. At the time of inspection for confirming that all data at all addresses are in the erased state, the row decoder control signal 19 and the column decoder control signal 22 at the time of inspection are set to low level, and the row decoder 23 is set.
And all the outputs of the column decoder 24, that is, the signals of the word lines 1 and 2, and the column gate control signals 3 and 4 become high level, and all the memory cells are simultaneously selected. At the same time, at the time of the read operation, the N for pulling the source line of the memory cell transistor 7 to the ground potential is set.
Channel MOS transistor 8 is rendered conductive. When data is erased, the memory cell transistor 7 is in a non-conductive state even when a voltage is applied between the drain and the source and between the gate and the source by a read operation, and has a characteristic that a drain current does not flow. Column gate 1
Even if a voltage is applied to the drain of the memory cell transistor 7 by the current detection type sense amplifier (not shown) connected to the bit line 11 via the bit line 3, the drain current of the memory cell transistor 7 does not flow. If there is a bit that cannot be erased even in one bit of all addresses,
Since the drain current flows through the memory cell transistor 7, the output value of the current detection type sense amplifier changes. For this reason, it is possible to check whether or not all the data at all addresses has been erased, based on the output value of the current detection type sense amplifier.

During a normal read operation, the row decoder control signal 19 and the column decoder control signal 22 at the time of inspection hold a high level, and the row decoder control signals 17 and 18 and the column decoder control signal 2 at the normal time.
By setting a signal corresponding to a memory cell selected from 0 and 21 to low level, data can be read.

As described above, according to the present embodiment, at the time of inspection for confirming that all data at all addresses are in the erased state, the column decoder 24 selects all the bit lines 11 at the same time and the row decoder 23 is all word lines 1,
By selecting 2 at the same time, all the memory cells are selected, and if there is at least one memory cell transistor 7 from which data has not been erased, the output of the current detection type sense amplifier changes. Therefore, it is possible to inspect whether or not all the data of all the addresses are erased by one read operation, so that an excellent E that can reduce the inspection time can be achieved.
An EPROM can be realized.

[0015]

As described above, according to the present invention, the column decoder can select all bit lines at the same time, and the row decoder can select all word lines at the same time. At the time of inspection for confirming the erased state, all memory cells are selected by the column decoder selecting all bit lines at the same time and the row decoder selecting all word lines at the same time,
If there is at least one memory cell from which data has not been erased, the output of the current detection type sense amplifier changes. Therefore, it is possible to inspect whether or not all the data of all addresses has been erased by one read operation, so that the excellent EEPR that the inspection time can be reduced.
OM can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an EEPROM according to an embodiment of the present invention.

FIG. 2 is a signal waveform diagram of each part at the time of a read operation at the time of inspection for confirming that all data at all addresses of an EEPROM are in an erased state in the embodiment of the present invention.

FIG. 3 is a circuit diagram of a conventional EEPROM.

FIG. 4 is a signal waveform diagram of each section during a read operation of a conventional EEPROM.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Word line 2 Word line 3 Column gate control signal 4 Column gate control signal 5 High voltage N channel MOS transistor for address selection 6 High voltage N channel MOS transistor for bit selection 7 Memory cell transistor 8 Ground potential of source line of memory cell transistor N-channel MOS transistor for pulling out to gate 9 Gate control signal of N-channel MOS transistor for pulling out source line of memory cell transistor to ground potential 10 Page line 11 Bit line 12 Memory unit (memory cell) for one address 13 Column gate 14 Page line read bias control signal 15 Bit line read bias control signal 16 Bit line read bias control signal 17 Normal row decoder control signal 18 Normal row decoder control signal 1 During inspection of the row decoder control signal 20 normal column decoder control signal 21 normal column decoder control signal 22 column decoder control signal 23 row decoder 24 column decoder during a test

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 29/788 29/792

Claims (1)

[Claims] A plurality of memory cells provided at intersections of a plurality of bit lines and a plurality of word lines and selected by the respective bit lines and the respective word lines; and a plurality of memory cells connected to the respective bit lines via respective column gates. An E including a current detection type sense amplifier for reading data from a memory cell, a column decoder for selecting a bit line by controlling the column gate, and a row decoder for selecting a word line.
An EPROM, wherein the column decoder enables simultaneous selection of all bit lines, and the row decoder enables simultaneous selection of all word lines.