JPH11126053A - Matrix display device - Google Patents

Abstract

(57) [Summary] [Problem] Monochrome multi gradation by analog data input
To realize a liquid crystal display of multi-color display and to provide an analog input LCM. An LCM on which a liquid crystal display panel is mounted is connected to the outside by an analog interface, and an analog-to-digital conversion circuit that converts input analog data having a plurality of signal levels into digital data, A voltage generation circuit for generating voltages of a plurality of levels is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matrix display device such as a liquid crystal display device, and more particularly to a method for realizing multi-gradation and multi-color display by analog display data input.

[0002]

2. Description of the Related Art A conventional liquid crystal display device is disclosed in
As described in Japanese Patent No. 5628, the liquid crystal cell is turned on and off in accordance with a digital value indicating input display data of "1" or "0" to perform monochrome display or eight-color display. No consideration was given to multi-color display analog input. The problems of the prior art will be described below with reference to FIGS.

FIG. 2 is a block diagram of a conventional liquid crystal display device. Reference numeral 1 denotes a liquid crystal display device (or a liquid crystal display module, also referred to as an LCM) having a matrix liquid crystal panel 17 selected by an X signal line and a Y signal line. Abbreviated), 18 is display data, display ON (white) is “1”, display OFF
(Black) is represented by “0”. Reference numeral 3 denotes a latch clock which is a clock synchronized with the display data 18, 4 denotes a horizontal clock indicating a display data amount transmission period for one horizontal display, and 5 denotes a head line signal. 19 is voltage generating means, 20 is display ON
Voltage, 21 is a display OFF voltage, 13 is a selection voltage, 14 is a non-selection voltage, and each voltage is generated by the voltage generation means 19. Reference numeral 22 denotes an X driving means for driving the X signal line, which is reset at the falling edge of the horizontal clock 4 and outputs the latch clock 3
, The display data 18 is fetched for one horizontal line.
When the data is 0, the data is converted to the display OFF voltage 21 and output at the falling edge of the next horizontal clock 4. X1 to X6
Numeral 40 denotes panel data, which is an output voltage of the X driving means 22. Reference numeral 16 denotes Y driving means for driving the Y signal line, and Y1 to Y2.
Reference numeral 00 denotes a scanning signal. The Y driving means 16 captures the leading line signal 5 at the falling edge of the horizontal clock 4, sets the scanning signal Y1 to the selection voltage 13, and sets the horizontal signal 4
The selection voltage 13 is sequentially applied to the scanning signals Y2 and Y at the falling edge of
3. Shifts to Y200. Note that each scanning signal has a non-selection voltage 14 other than the selection voltage 13. Reference numeral 17 denotes a liquid crystal panel, which is panel data X1 to X64 which are X signal line driving voltages output from the X driving means 22.
The scanning signal Y having the level of the selection voltage 13 according to 0
The data is displayed on the line on i.

FIG. 3 is a timing chart for explaining the operation of LCM1.

In FIG. 2, the X driving means 22 sequentially fetches the display data 18 for one line in synchronization with the latch clock 3, and is selected by the next horizontal clock 4 by "1" or "0" of each data. Display ON voltage 20,
The display OFF voltage is output as panel data X1 to X640. Therefore, as shown in FIG.
2 outputs the voltage selected by the data of the 200th line which is the last line when the data of the first line is fetched, and outputs the voltage selected by the data of the first line when the data of the second line is fetched. Outputs the selected voltage. That is, the operation is performed with the capture and the output shifted by one line. At this time, the Y driving means 16 is
The leading line signal 5 is taken in at the timing of the horizontal clock 4 so that the scanning signal Y1 is at the level of the selection voltage 13 so that the scanning signal of the line output by the selection voltage 13 is the selection voltage 13, and then the selection voltage 13 is shifted according to the horizontal clock 4. Go. The liquid crystal panel 17 performs “white” when the display ON voltage is 20 and “black” when the display OFF voltage is 21 according to the voltages of the panel data X1 to X640 on the line of the scanning signal having the selection voltage 13.

At the time of color display, red, green, and blue color filters are arranged in the line direction or the dot direction, and three dots make visible information one dot, and display ON or display OFF, respectively.
8 colors are displayed by additive color mixing.

[0007]

Recently, demands for color display and multi-gradation display have been increasing. However, as the number of colors increases, an interface between a liquid crystal panel and an information processing device such as a personal computer becomes a problem. . That is, for example, in the case of displaying 4096 colors, signal lines representing each of R, G, and B are required for 4 bits, and 12 signal lines are required. When 32768 colors are displayed by increasing the number of colors, R,
G and B signal lines of 5 bits each are required (15 lines in total). As the number of signal lines increases, the connection between the display panel and a personal computer or the like becomes complicated and causes unnecessary spatter. To prevent this, the input signal line may be an analog input.

However, the above-mentioned prior art is a display with display ON or display OFF, and does not consider analog data input for performing monochrome multi-tone and color multi-color display.

An object of the present invention is to realize a liquid crystal display of multi-gradation and multi-color display by analog data input, and further to provide an analog input LCM.

[0010]

According to the liquid crystal display device of the present invention, an LCM on which a liquid crystal display panel is mounted and an external device are connected by an analog interface, and the input analog data having a plurality of signal levels is converted into digital data. And a voltage generating circuit for generating a plurality of levels of voltages according to the gradation.

Further, the liquid crystal display device of the present invention comprises a serial / parallel conversion circuit for converting an input serial signal into parallel, and a latch means for simultaneously latching a parallel output.

Since the outside and the LCM are connected by an analog interface, the number of input signal lines does not increase even if the number of gradations increases. The input analog data is converted into digital data by an analog / digital conversion circuit, and a signal having a voltage level corresponding to the digital data is selected from the voltage generation circuit and applied to the liquid crystal panel.
This enables multi-gradation expression.

Further, the serial data is converted into parallel data by a serial / parallel conversion circuit, and the subsequent circuits are operated in parallel, whereby the circuit operation can be slowed down.

[0014]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
This will be described with reference to FIG. In the present embodiment, a monochrome 4-gradation display will be described as an example.

FIG. 1 is a block diagram of an embodiment of the present invention. Reference numeral 2 denotes analog display data having quaternary voltage levels;
Reference numeral 6 denotes analog-to-digital conversion means, and reference numeral 7 denotes digital display data. The analog-to-digital conversion means 6 converts the input analog display data 2 into 2-bit digital display data 7 according to the voltage value (4 of the analog display data 2).
(00), (0,
1), (1, 0), and (1, 1)). Reference numeral 8 denotes a multi-voltage level output generation circuit which generates a plurality of levels of voltages according to the gradation. For example, in this embodiment, since four gradations are displayed, four levels of voltages are generated. A signal of a voltage level corresponding to gradation 0 is output to signal line 9 and signal line 1 is output.
Signals of voltage levels corresponding to gradations 1, 2, and 3 are output to 0, 11, and 12, respectively. Numeral 15 denotes X driving means, which sequentially fetches 2-bit digital display data 7 for one line by the latch clock 3, and outputs four gradations output to the signal lines 9, 10, 11, 12 according to the decode value of the data of each dot. Select one of the voltages and select the panel data X1
~ X640. Others are the same as FIG.

FIG. 4 is a block diagram of one embodiment of the X driving means. Reference numeral 23 denotes a latch selector, S1 to S640 denote select signals, and the latch selector 23 is cleared by a horizontal clock 3 and thereafter by a latch clock 3. The selection signals S1 and S2 are sequentially set to “high”. A latch circuit 24 latches the digital display data 7 in blocks (latch 1 to latch 640) in which the select signal is "high". Reference numerals 25 to 28 denote 2-bit latch data 1 to 640, which are outputs of each block of the latch circuit 24.
Reference numeral 29 denotes a horizontal latch circuit which latches latch data 1 to 640 in synchronization with a horizontal clock 4 by horizontal latches 1 to 640, respectively. Reference numerals 30 to 33 denote outputs of the respective blocks of the horizontal latch circuit 29, which are 2-bit horizontal data 1 to 640, respectively. Reference numeral 34 denotes a decoder which decodes each of the horizontal data 1 to 640 by the decoder (decoder 1 to 640) of each block ((0, 0) is 1, (0, 1) is 1 (1, 0) and 2 is 2).
(1, 1) = 3). Reference numerals 35 to 38 denote output values of the decoders of the respective blocks, which are decoded values 1 to 640. 39 is a voltage selector, which is a value (0, 0) of decode values 1 to 640,
According to (0,1), (1,0), (1,1), one of the gradation voltages is selected.

In FIG. 1, the analog display data 2 is converted into 2-bit digital display data by the analog-to-digital conversion means 6 and input to the X drive means 15. X
The drive means 15 receives the select signal which is “high” at that time in synchronization with the input digital display data 7 in synchronization with the latch clock 3. It is taken into one block of the latch circuit 24. Since the latch selector 23 shifts the “high” state of the select signal every time the latch clock 3 is input, the latch circuit 24 sequentially captures the digital display data 7 sequentially transmitted to the latches 1 and 2. be able to. Thus, the latch circuit 2
4 takes in the digital display data 7 for one line, that is, up to the latch 640, the horizontal clock 4 is given,
The latch selector 23 is cleared, and the data fetched into the latch circuit 24 is transferred to the horizontal latch circuit 29 and latched in preparation for fetching the next line data. The horizontal data 1 to 640 output from the horizontal latch circuit 29 are input to the decoder 34, and are respectively decoded by the decoders 1 to 640 of the block of the decoder 34, and the decoded values 1 to 640 are provided.
Is output from the decoder 34. Voltage selector 39
Then, the decode values 1 to 640, which are the outputs of the decoder 34,
, The grayscale 0 voltage 9 when the decode value is “0”, the grayscale 1 voltage 10 when the decode value is “1”, and the grayscale 2 when the decode value is “2” in the voltage selectors 1 to 640 of each block. When the voltage is “3”, the gray scale 3 voltage is selected, output from each block, and supplied to the liquid crystal panel 17 as panel data X1 to X640. Therefore, in the LCM 1 of FIG.
The four-level voltage output from the X driving means 15 is applied to the one-line liquid crystal panel at the voltage level of the selection voltage 13 of the scanning signal, which is the output of the above, and four-gradation display is realized.

In the above-described embodiment, the description has been made of the 4-gradation display. However, the input analog display data is 2N (N is 1).
When expressing the above (integer) level, analog-to-digital conversion means converts the data into N-bit digital display data, and
The same can be realized by setting the data width of the internal circuit of the driving means to N bits and the input voltage to 2N types.

In the case of a color display, red, green and blue color filters are arranged on the liquid crystal panel 17 in the dot direction, and as shown in FIG.
1 and B42 are provided with analog-to-digital conversion means, respectively, and R, G, and B analog-to-digital conversion means 43, 44, and 45 are provided.
Is provided to the color X driving means 46. At this time, the color X drive means 46 has three blocks of FIG. 4 and each panel data is RX1 to RX64.
0, GX1 to GX640 and BX1 to BX640.

Next, as a second embodiment, a case where the X drive means is a parallel (M dot) input will be described. In the present embodiment, description will be made on the assumption that M = 2 dots.

FIG. 6 is a block diagram of an embodiment when the X driving means is parallel input. 47 is serial-parallel conversion means, 48 is 1-dot digital data, 49 is 2-dot digital data. The output 2-bit serial digital display data 7 is converted into 2-bit parallel data of first-bit digital data 48 and second-dot digital data 49. 50
Is a timing correction means, 51 is a parallel clock, 52
Is a corrected horizontal clock signal, 53 is a corrected leading line signal, and the timing correction means 50 is a latch clock 3 which outputs a parallel first dot digital data 48, a parallel clock 50 synchronized with the second dot digital data, and display data. In order to correct the phase shift caused by the parallel conversion, the horizontal clock 4 and the leading line signal 5 are corrected by the latch clock 3 to obtain a corrected horizontal clock 52 and a corrected leading line signal 53. Numeral 54 denotes parallel X drive means, which sequentially captures parallel 2-bit display data with the parallel clock 51. FIG. 7 is a timing chart showing the operation of the serial / parallel conversion means. FIG. 8 is a block diagram of the input section of the parallel X drive means 54. And select signals S1 and S
2. S320 is set to "high". Reference numeral 52 denotes a parallel latch circuit, which is a “high” block of the select signals S1 to S320 and is a first dot digital 47;
The second-dot digital data 48 is simultaneously latched at the timing of the parallel clock 51. Other reference numerals are the same as those in FIG.

In FIG. 6, analog display data 2 having a quaternary voltage level is converted into 2-bit digital display data 7 by analog-to-digital conversion means 6, and this digital display data 7 is converted to serial-parallel conversion means 4.
7, the data is converted into 2-dot parallel data as shown in FIG. 7, and becomes first-dot digital data 48 and second-dot digital data synchronized with the parallel lock 5. At this time, the data output from the serial / parallel conversion means 47 is delayed by two clocks as compared with the input phase, as shown in FIG. In order to correct the delay, the horizontal clock 4 and the leading line signal 5 are similarly delayed by two clocks by the timing correcting means 50, and the X driving means 54 and the Y driving signal 54 are used as the corrected horizontal clock 52 and the corrected leading timing signal 53. It is provided to the driving means 16. As shown in FIG. 8, the X driving means 54 parallelizes the first-dot digital data 48 and the second-dot digital data 49 to one block of the parallel latch circuit 55 in which the output of the parallel select 54 is "high". The data is taken in synchronization with the clock 51.

The parallel latch select 51 is cleared by the correction horizontal clock 52, and thereafter the parallel clock 5
1, the latch signals are sequentially latched in the order of the latches 1, 2, 3,..., And the data of one line is also latched. Will do. The output of each block of the parallel latch circuit 55 is latched by the horizontal latch circuit 29 with the corrected horizontal clock 52, and thereafter, the same operation as in FIG.
1 to X640. As described above, the X driving means is provided by providing the serial / parallel conversion means 47, latching the input portion of the X driving means by two dots simultaneously, and further providing the timing correction means for correcting the phase delay caused by the parallel conversion. Can be input as two dots. Thus, the analog / digital conversion means 6
The operation speed of the subsequent circuit can be reduced.

In this embodiment, the input of the X driving means is described as 2 bits and 2 dots. However, N (N is an integer of 1 or more) bits and M (M is an integer of 2 or more) dots can be similarly implemented. .

As shown in FIG. 9, also in the case of color display, an R serial / parallel converter 56, a G serial / parallel converter 57 and a B serial / parallel converter 58 are provided in FIG. 59 can be realized by adopting a configuration having three lines of input units of the X drive means in FIG.

In the above description, a liquid crystal display device has been described as an embodiment, but a matrix display device such as a plasma display or EL may be used.

[0027]

According to the present invention, a multi-tone, multi-color display LCM can be realized by analog data input, and the number of input lines of the LCM can be reduced. Also, by reducing the number of data bits and converting to analog data, there is an effect that generated noise can be reduced.

The X drive means can be driven in parallel.
This has the effect of reducing the operating speed.

Further, since the output of the X driving means is of a voltage selection method using an N-bit decode value, it is possible to use each gradation voltage with little variation.

[Brief description of the drawings]

FIG. 1 is a block diagram of an LCM according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a conventional LCM.

FIG. 3 is a timing chart showing an operation of the LCM of FIG. 2;

FIG. 4 is a block diagram of one embodiment of an X driving means.

FIG. 5 is a block diagram of a first embodiment for color display.

FIG. 6 is a block diagram of a data system of an LCM according to a second embodiment of the present invention.

FIG. 7 is a timing chart showing the operation of the serial-parallel conversion means.

FIG. 8 is a block diagram of an input unit of a parallel X driving unit 54;

FIG. 9 is a block diagram of a data system according to a second embodiment for color display.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... LCM, 2 ... Analog display data, 3 ... Latch clock, 4 ... Horizontal clock, 5 ... Head line signal, 6 ... Analog digital conversion means, 7 ... Digital display data, 8
... Multiple output voltage generating means, 9... Gray scale 0 voltage, 10.
Voltage, 11: grayscale 2 voltage, 12: grayscale 3 voltage, 15: X
Driving means, X1 to X640: panel data, 17: liquid crystal panel, 23: latch selector, 24: latch circuit,
29: horizontal latch circuit, 34: decoder, 39: voltage selector, 43: R analog-to-digital conversion means, 44:
G analog-to-digital conversion means, 45 ... B analog-to-digital conversion means, 46 ... color X driving means, 47 ... serial / parallel conversion means, 48 ... first dot digital data,
49: 2nd dot digital data, 50: timing correction means, 51: parallel clock, 52: correction horizontal clock, 53: correction head line signal, 54: parallel X drive means, 54: parallel latch select, 55: parallel latch circuit , 56 ... R serial / parallel conversion means, 5
7: G serial / parallel conversion means, 58: B serial / parallel conversion means, 59: color parallel X driving means

Continued on the front page (72) Inventor Toshio Futami 3300 Hayano, Mobara-shi, Chiba Pref.Hitachi Seisakusho Mobara Plant (72) Inventor Kiyoge Kinukawa 3300 Hayano, Mobara-shi Chiba Pref.

Claims (2)

[Claims] A matrix display panel having an X signal line; an analog-to-digital conversion circuit for converting analog display data into serial digital display data; and an adjoining serial digital display data on the matrix display panel. A serial-to-parallel conversion circuit for converting display data indicating display of an X signal line into parallel digital display data, and a parallel digital display indicating display of the continuous X signal line converted by the serial-parallel conversion circuit A latch circuit for latching data; and X for supplying a voltage signal according to the parallel digital display data latched by the latch circuit to the X signal line.
A matrix display device, comprising: a driving circuit. 2. The matrix display device according to claim 1, wherein a horizontal clock signal indicating a display data amount transmission period for one horizontal display corrected according to a latch clock, and a head line of display data corrected according to the latch clock. A timing correction circuit for correcting a phase error generated between the serial digital display data and the parallel digital display data obtained by converting the serial digital display data by the serial / parallel conversion circuit, based on a leading line signal; A matrix display device characterized by the above-mentioned.