JPH11123845A - Image forming apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To move to an image forming operation immediately after an emission quantity of a semiconductor laser is adjusted to be an adequate value without increasing a burden of a software. SOLUTION: An LDSET signal is turned on in order to start an initial optical quantity adjusting mode. At that time, an LD is continuously lightened and a polygon mirror 3 is continuously rotated, then a mask (MASK) signal of a BD signal is validated. Next, a setting time required for initializing stored in a program ROM is read. A counter is incremented until the setting time has elapsed. When the setting time has elapsed, it is judged whether the optical quantity of the LD is an adequate level based on a monitor voltage. When it becomes the adequate level, the mask (MASK) signal is released.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image forming apparatus for writing an image using a semiconductor laser (laser diode: LD).

[0002]

2. Description of the Related Art In general, the drive current-emission light amount characteristic of an LD is such that the light emission amount is weak when the drive current does not exceed a threshold value (LED light emission region), and the drive current exceeds the threshold value (laser light emission region). In (2), the amount of emitted light increases in proportion to the drive current. However, the threshold value varies depending on the temperature. For this reason, even if the drive current is the same, the light emission amount is different when the temperature is different. Therefore, a photodiode for monitoring the light emission amount of the LD is provided in the LD unit, Generally, the drive current is controlled based on the amount of received light so that the amount of light emitted from the LD becomes an appropriate amount of light.

Conventionally, this type of image forming apparatus includes a normal mode in which writing is performed line by line in an image area, as described in Japanese Patent Application Laid-Open No. Hei 9-11531, and a normal mode in which writing is performed in a non-image area before the image area. During the sampling period for each line, the LD is turned on, the amount of emitted light is monitored, the LD drive current is adjusted so that the monitored amount of light becomes an appropriate value, and a voltage corresponding to the appropriate value is charged to the holding capacitor. A device having a light amount adjustment mode for shifting to a normal mode has been proposed.

In the light amount adjustment mode, a voltage corresponding to an appropriate light amount is held by a holding capacitor. When a synchronization detection signal is detected in a non-image area immediately before an image area, the mode shifts from the light amount adjustment mode to a normal mode. In the mode, the LD is driven with an appropriate drive current based on the charging voltage of the capacitor.

[0005]

However, in the above-described conventional image forming apparatus, the initial adjustment is performed not only for each line, but also immediately before writing is started in the image area when the OFF time of the LD is long. It is necessary to charge the holding capacitor for a certain period of time in order to perform the following steps.Therefore, it is necessary to promptly shift to the image forming step after the initial adjustment is completed, thereby increasing the software load. is there. Also, in the sampling period, if there is not enough time for the lighting time of the LD, there is a problem that an excessive current flows during the lighting of the LD and the LD may be broken.

In view of the above-mentioned conventional problems, the present invention can immediately shift to the image forming operation after adjusting the light emission amount of the semiconductor laser to an appropriate value without increasing the load on software. It is an object to provide an image forming apparatus.

[0007]

In order to achieve the above object, a first means is to scan an output light of a semiconductor laser on a photosensitive member by a polygon mirror in a normal operation mode to form an image by an electrostatic image forming process. In an image forming apparatus for forming, a monitor means for monitoring an output light amount of the semiconductor laser, and an output light of the semiconductor laser scanned by the polygon mirror is received outside an end of the photoconductor to generate a synchronization detection signal. Means for detecting, and masking the synchronization detection signal at the time of power setting, continuously lighting the semiconductor laser and continuously rotating the polygon mirror, during which the monitoring of the semiconductor laser monitored by the monitoring means is performed. Output light is sampled and controlled so that the proper light quantity is reached, and when the proper light quantity is reached, the synchronization detection signal mask is released. Characterized in that a light amount control means shifts to the normal operation mode Te.

The second means is the first means, wherein the light quantity control means samples the time during which the semiconductor laser is turned on during a power set period and the output light of the semiconductor laser monitored by the monitor means. The time can be changed.

A third means is that, in the second means, the light quantity control means measures and stores a light quantity adjustment time from the start of one light quantity adjustment period to a proper light quantity, and adjusts the light quantity adjustment time. If the time ends within a predetermined time, the next light amount adjustment time is shortened.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a laser printer system to which an embodiment of the image forming apparatus according to the present invention is applied, FIG. 2 is a configuration diagram showing an optical scanning system of the optical writing unit of FIG. 1, and FIG. FIG. 4 is a block diagram showing an initial power set block of the laser printer system of FIG. 1, FIG. 5 is a timing chart showing main signals by the circuit of FIG. 4, and FIG. 6 is a light amount. FIG. 7 is a flowchart for explaining processing in the adjustment mode, and FIG. 7 is a block diagram functionally showing the image forming apparatus according to the present invention.

FIG. 1 shows a control block of a laser printer system to which the image forming apparatus of the present invention is applied.
The control block includes a printer engine 45 that scans the output light of the semiconductor laser on the photoconductor by a polygon mirror to form an image by an electrostatic image forming process in a normal operation mode, an engine driver 40 that controls the printer engine 45, A printer controller 3 that receives image data from the host machine 38, develops the image, and outputs the image data to the engine driver 40
0.

The printer controller 30 and the engine driver 40 include CPUs (MPU) 31, 41, program ROMs 32, 42, RAMs 33, 43, and I / O
The printer controller 30 transfers the developed image data line by line in accordance with a timing signal from the engine driver 40 via an interface (I / F) 36. Here, the timing circuit constituted by logic is often integrated as an ASIC. The printer engine 45 includes the optical writing unit 26, the sequence device group 46, and the sensors 4
The optical writing unit 26 has an optical scanning system as shown in detail in FIG. 2 and an LD control plate 10 as shown in FIG.

In FIG. 2, the LD unit 1 comprises a laser diode (LD) and a photodiode (PD) for monitoring the light emission amount P of the LD, and the light of the LD is transmitted from an LD control plate 10 shown in FIG. On / off modulation is performed according to the image data at the time of image formation by the drive current Id, and the light is continuously turned on at the time of light quantity adjustment. The light of this LD is collimated by the cylindrical lens 2 and then rotated by the polygon mirror 3 in the direction of the arrow A.
Is deflected at a constant angular velocity in the direction of the arrow B, and is then deflected at a constant velocity by the fθ lens 4 in the direction of the arrow C to irradiate the photosensitive member 5.

A synchronization detecting sensor 6 is disposed outside the end of the photosensitive member 5 (non-image area immediately before the image area), and when one line of LD light is deflected in the arrow direction C,
First, scanning is performed in the non-image area, and then, in the non-image area immediately before the image area, light is received by the synchronization detection sensor 6 to detect the main scanning synchronization signal BD.
The electrostatic latent image is formed in the image area. This electrostatic latent image is developed by a known electrostatic image forming process and recorded on a sheet.

As shown in FIG. 3, the LD control board 10 includes a control driving circuit 11, a voltage holding circuit 12 constituted by a parallel circuit of a capacitor Ch and a resistor Rh, and a variable resistor VR.
And fixed load resistors Rb, Rs, Ro, a pull-up resistor Rp, and a diode D. The control drive circuit 11 includes a reference voltage power supply 13, a bias current power supply 14, a switching (SW) current power supply 15, a SW circuit 16, a differential amplifier 17, and a sample and hold (S / H) circuit 18. .

The anode of the LD and the cathode of the PD constituting the LD unit 1 are both connected to a + power supply. LD
The drive current Id on the cathode side of the bias current Ib
The current Isw is divided into a bias current Ib and a SW current Isw.
6 is applied. Light intensity monitor current I on the anode side of PD
m is applied to the differential amplifier 17.

The reference voltage power supply 13 outputs a reference voltage Vr as a constant voltage power supply to the bias current power supply 14 and the S / H circuit 18, and the bias current power supply 14 outputs a constant current Ib as a constant current power supply. The SW current power supply 15 controls the value of the drive current Id, and the SW circuit 16 controls the current Is according to the input data.
w is turned on and off. The differential amplifier 17 forms a feedback system of the light amount monitor current Im monitored by the PD, and converts the light amount monitor current Im into a voltage signal Vm. The S / H circuit 18 samples the light amount monitor voltage signal Vm output from the differential amplifier 17 during the sampling period, and holds this during the holding period.

From the engine driver 40, a signal obtained by logically ORing the image data developed and synchronized with the image clock and the timing light emission signal for sampling and synchronization detection is output as an LD lighting (LDON) signal. This LDON signal is applied to the SW circuit 16 via the diode D. The SW circuit 16 closes when the LDON signal is high and emits light from the LD, and closes when the LDON signal is low and emits no light.

The engine driver 40 outputs an enable (ENB) signal and a sample and hold (S / H) signal. This ENB signal is a bias current power supply 1
4, applied to the SW current power supply 15 and the S / H circuit 18,
These circuits 14, 15, 18 are enabled when the ENB signal is low, while they are disabled when the ENB signal is high. The S / H signal is S / H
Applied to circuit 18, S / H circuit 18 is in a sampling mode when the S / H signal is high, while it is in a holding mode when the S / H signal is low.

The load resistor Rb is connected between the ground and the bias current power supply 14, thereby providing the bias current power
4 keeps the bias current Ib constant regardless of whether the LD is on or off, and keeps the LD in the LED light emitting region under any environmental conditions.

The load resistance Rs is equal to the ground and the SW current power supply 1.
5 so that the SW current power supply 15
The SW current Isw output when the circuit 16 is closed is maintained at a standard value. The sum of the SW current Isw and the bias current Id is L
D drive current Id, and the SW circuit 16
When the switch is opened and closed according to the signal, the SW current Isw is turned on and off. In this case, the ON-time SW current Isw changes so that the light emission amount of the LD becomes an appropriate light amount near the standard value determined by the resistance Rs.

The resistance Ro is a laser power supply load resistance connected between the SW circuit 16 and the power supply Vcc. The variable resistor VR is connected to the differential amplifier 17, and this value is set in advance when the differential amplifier 17 converts the light amount monitor current Im to the monitor voltage Vm when the LD light emission amount is an appropriate light amount.
m is adjusted so as to be equal to the reference voltage Vr. Here, when the ENB signal is low, that is, when the LD control plate 10 is active and all other signals are not active, only the bias current Id flows as the LD drive current Id, and the LD is in the LED light emitting region. The light quantity is weak, and the light quantity monitor current Im is almost “0”.

Next, the operation of the LD control plate 10 will be described. First, the engine driver 40 performs S / H in the non-image area.
When the signal and the LDON signal are made high, the S / H circuit 18 enters the sampling mode when the S / H signal is high,
Further, the SW circuit 16 is closed and the SW current Isw flows.
Therefore, since the LD drive current Id is the sum of the SW current Isw and the bias current Id, the LD shifts from the LED light emission region to the laser light emission region, and the light emission amount P sharply increases. Then, the monitor current Im of the PD according to the light emission amount P is converted into a monitor voltage Vm by the differential amplifier 17, and the monitor voltage Vm is applied to the S / H circuit 18.

In the sampling mode, the S / H circuit 18 compares the monitor voltage Vm with the reference voltage Vr, and determines that Vm <
When Vr, that is, when the amount of emitted light P is less than the appropriate amount of light, the capacitor Ch is charged. On the other hand, when Vm> Vr, that is, when the amount of emitted light P exceeds the appropriate amount of light, the capacitor Ch is discharged with a constant current.

When the holding voltage Vh of the capacitor Ch is higher than an appropriate value, the SW current power supply 15 increases the SW current Isw to increase the amount of emitted light P, while the holding voltage Vh
Is lower than the appropriate value, the SW current Isw is decreased to lower the light emission amount P.

By such feedback control, L
When the D drive current Id reaches an appropriate value and the amount of emitted light P becomes an appropriate amount of light, and the PD monitor voltage Vm becomes equal to the reference voltage Vr, the S / H circuit 18 does not charge or discharge the capacitor Ch, and holds the capacitor Ch. The voltage Vh becomes equal to the appropriate value.

Next, when the engine driver 40 makes the S / H signal and the LDON signal low in the non-image area,
The SW circuit 16 is opened, the SW current Isw is cut off, and the LD
Stops emitting light. Further, the S / H circuit 18 shifts from the sampling mode to the holding mode, the internal impedance of the terminal to which the capacitor Ch is connected becomes infinite, and the proper holding voltage Vh held by the capacitor Ch is held.

Here, when sampling starts and ends, L
When D does not emit light, it is determined that the LD has not emitted light at the set light amount, and charging of the capacitor Ch is started.
When the potential is increased and the LD is turned on, the LD may be destroyed by an excessive current. Therefore, it is necessary to allow time for the LD emission timing before and after the sampling period.

Next, when the engine driver 40 sets the LDON signal high during the detection period of the main scanning synchronization detection signal in the non-image area immediately before the image area, the LD emits light with the light amount P corresponding to the holding voltage Vh of the capacitor Ch. Then, during the light emission, the engine driver 40 shifts to the preparation for outputting the LDON signal corresponding to the image data by the clock phase-synchronized with the main scanning synchronization detection signal BD detected by the synchronization detection sensor 6.

Next, when the detection period of the main scanning synchronization detection signal BD elapses, the engine driver 40 returns the LDON signal to low to stop the light emission of the LD, and then one line of the image from the start of writing of the image area. The output of the LDON signal is started. At this time, the SW circuit 16 turns on and off the SW current Isw according to the appropriate holding voltage Vh according to the LDON signal. Therefore, the LD outputs an appropriate amount of laser light when the LDON signal is on. 5
An electrostatic latent image for one line is formed thereon.

Next, the initial power set block of the engine control board will be described with reference to FIG. L
The DSET signal is a signal for setting an initial power set mode, and is an output of an LDSET register (not shown). The CLK signal is an operation clock of the engine control board. The BD (beam detect) signal is a signal detected by the synchronization detection sensor 6. BDD signal is B
The D signal is a signal delayed by a clock.
The LDSET register (not shown) is cleared at a low level. The RST signal is a system reset signal.

The PLD signal is an LD light emission timing signal in an initial power set mode, and a logical sum signal of a synchronization detection timing light emission signal for each line and image data is used as an LDON signal in a subsequent circuit.
The PLD signal is cleared at the falling edge of the BDD signal.
The PSH signal is a sampling signal in the initial power set mode.
An OR signal with the H signal is output to the LD control board 10.
The PSH signal is cleared at the fall of the BD signal.

At the time of initial setup, as shown in FIG. 5, the LDON signal becomes active when the LDSET register is set. The S / H signal is LD
After the SET register is set, 1
Becomes active after clock delay. The MASK signal is a signal for masking the BD signal, and during this set period, the LDON signal is not cleared even if the BD signal is input. Therefore, the time required for initial light quantity adjustment, M
By setting the ASK signal, the light amount can be continuously adjusted.

Next, the processing in the light amount adjustment mode will be described with reference to FIG. First, the LDSET signal is turned on to start the initial light amount adjustment mode (step S
1).

At this time, the LD is continuously turned on, the polygon mirror 3 is continuously rotated, and the BD signal mask (MASK signal) is valid. Next, the set time required for the initial set in the program ROM 42 is read, and the counter is incremented until the set time elapses (step S2 →
S3). When the set time has elapsed, it is determined whether or not the LD light quantity is at an appropriate level based on the monitor voltage (steps S4 → S5). If the LD light quantity is at the appropriate level, the MASK signal is released (step S6). If the level is not the level, an error process is executed (step S7).

In FIG. 4, when the BD signal is unmasked and the BD signal is input, the S / H signal is cleared, the LDON signal is cleared by the BDD signal, and the LDS signal is cleared.
Clear the ET register. In addition, in step S5 shown in FIG. 6, when the LD light amount has not reached the appropriate level even after the set time has elapsed, the operation is stopped and L
The DSET signal is turned off, and power set error processing of the LD is performed (step S7). Therefore, the above processing makes it possible to shift from the light amount adjustment period to the normal image forming period in only one step of releasing the mask of the BD signal.

Next, FIG. 7 functionally shows an image forming apparatus according to the present invention, in which a sampling light emission control means 70, a light emission timing setting means 71, and a synchronization detection light emission control means 72 are provided.
And a light quantity control means 73 having a setting storage means 74 and a current value control means 75, and a semiconductor laser 76. The sampling light emission control means 70 outputs a sampling signal to the setting storage means 74 and the current value control means 75 during the sampling period set in the light emission timing setting means 71, and the current value control means 75 turns on the semiconductor laser 76. The monitor light quantity signal is fed back to the light quantity control means 74, and the appropriate light quantity is stored in the setting storage means 74. Further, the synchronization detection light emission control means 7
2 masks the synchronization detection signal BD during the sampling period set in the light emission timing setting means 71.

Next, a second embodiment will be described with reference to FIGS. FIG. 8 shows a main circuit of a control block of the second embodiment, and FIG. 9 shows main signals of the circuit of FIG. In FIGS. 8 and 9, when the BD signal is input asynchronously with respect to the clock of this control block, DF
F latches the clock of the control circuit and generates a BDS signal synchronized with the clock of the control circuit. This BD
As an example, the S signal is applied to a data input terminal D of a 4-bit shift register, and four signals BDD1 to BDD1 delayed by one clock by the 4-bit shift register.
DD4 is generated. Next, the signals BDD1 to BDD
4 is switched by a multiplexer by selection signals SEL0 and SEL1 according to the source clock, and is input as a BDD signal in the circuit shown in FIG. Therefore, the clear timing delay of the LDON signal with respect to the BD signal can be set in clock units in accordance with the timing specification of the light amount adjustment. Here, the clear signal sets the light amount for each line.

Next, a third embodiment will be described with reference to FIGS. FIG. 10 shows a process of adjusting the light amount in the initial state. As the first light amount adjustment, the adjustment time is set as initially set (step S11). Next, an adjustment time counter is started (step S12),
Next, an adjustment time counting process is performed in parallel while checking whether or not the light amount level has become appropriate (Step S).
13 to S16). Then, when the light amount level becomes appropriate within the adjustment set time, the required time at that time is stored in the non-volatile memory (step S14 → S17), and then the MASK signal is released to end the light amount adjustment mode, The operation shifts to a normal image forming operation (step S18).

FIG. 11 shows a process for adjusting the light amount after acquiring the adjustment time sample in FIG. 10. First, an adjustment time counter is started (step S21), and then the light amount adjustment stored in the above-mentioned nonvolatile memory is performed. If the time has a considerable margin with respect to the initial setting time, the light amount adjustment time is reduced. A time obtained by giving a margin to the stored time is set as an adjustment time, and a time difference from the initial setting is set as an adjustment start delay (steps S22 to S2).
3) After the delay time has elapsed, the adjustment mode is started (step S24). Then, similarly, the light amount is adjusted until the set time (steps S25 to S30).

[0041]

As described above, according to the first aspect of the present invention, the synchronous detection signal is masked at the time of power setting, the semiconductor laser is continuously turned on, and the polygon mirror is continuously rotated. Since the output light of the semiconductor laser monitored at the time is sampled and controlled so as to have an appropriate amount of light, when the amount of light reaches the appropriate amount, the mask of the synchronization detection signal is released and the mode shifts to the normal operation mode. The mode can be shifted to the normal operation mode only by canceling the signal mask.Therefore, the light emission amount of the semiconductor laser is adjusted to an appropriate value without increasing the software load, and then the image forming operation is immediately started. Can be migrated.

According to the second aspect of the invention, even when the source clock is different, the time for turning on the semiconductor laser and the time for sampling the output light of the monitored semiconductor laser can be made the same.

According to the third aspect of the present invention, the light amount adjustment time from the start of one light amount adjustment period to the appropriate light amount is measured and stored, and the light amount adjustment time ends within a predetermined time. In this case, since the next light amount adjustment time is shortened, unnecessary lighting of the semiconductor laser after the light amount adjustment is completed can be prevented, and the life can be extended.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a laser printer system to which an embodiment of an image forming apparatus according to the present invention is applied.

FIG. 2 is a configuration diagram showing an optical scanning system of the optical writing unit of FIG.

FIG. 3 is a block diagram illustrating an LD control plate of the optical writing unit of FIG. 1;

FIG. 4 is a block diagram showing an initial power set block of the laser printer system of FIG. 1;

FIG. 5 is a timing chart showing main signals by the circuit of FIG. 4;

FIG. 6 is a flowchart for describing processing in a light amount adjustment mode.

FIG. 7 is a block diagram functionally showing the image forming apparatus according to the present invention.

FIG. 8 is a block diagram illustrating a main circuit of a control block according to a second embodiment.

FIG. 9 is a timing chart showing main signals of the circuit of FIG. 8;

FIG. 10 is a flowchart illustrating a process of adjusting a light amount in an initial state according to the third embodiment.

FIG. 11 is a flowchart showing a process of adjusting the light amount after acquiring an adjustment time sample in FIG.

[Explanation of symbols]

 LD laser diode PD photodiode 10 LD control board 20 engine driver

Claims (3)

[Claims] 1. An image forming apparatus for forming an image by an electrostatic image forming process by scanning an output light of a semiconductor laser on a photosensitive member by a polygon mirror in a normal operation mode, wherein the monitor monitors an output light amount of the semiconductor laser. Means for receiving the output light of the semiconductor laser scanned by the polygon mirror outside the end of the photoreceptor to detect a synchronization detection signal, and masking the synchronization detection signal during power setting, The semiconductor laser is continuously turned on and the polygon mirror is continuously rotated. During this time, the output light of the semiconductor laser monitored by the monitor is sampled and controlled so as to have a proper light quantity. Light amount control means for canceling the mask of the synchronization detection signal and shifting to the normal operation mode when An image forming apparatus, comprising: 2. The method according to claim 1, wherein the light amount control means is capable of changing a time for turning on the semiconductor laser during a power set period and a time for sampling output light of the semiconductor laser monitored by the monitor means. The image forming apparatus according to claim 1. 3. The light quantity control means measures and stores a light quantity adjustment time from the start of one light quantity adjustment period to an appropriate light quantity, and when the light quantity adjustment time ends within a predetermined time. 3. The image forming apparatus according to claim 2, wherein the time for adjusting the next light amount is reduced.