JPH11121566A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] To inspect a plurality of integrated circuit devices at a wafer level, disperse a current at the start of operation,
Further, the state of one of the plurality of integrated circuit devices can be monitored during the inspection. SOLUTION: Each chip ID of a chip ID holding circuit 10
Each of the recording units 11, 12, and 13 has a transistor whose gate receives the ID selection signal 1 output from the external device, whose power supply voltage is applied to its drain, and whose source is grounded via a fuse. The output data of each transistor is output to the clock signal control circuit 20.
The clock signal control circuit 20 includes an ID selection signal 1, an external clock signal 2, and first to third chip ID recording units 11 to 1.
3 and a counter 21 for outputting a carry signal B and a latch circuit 2 for latching the carry signal B.
And a generation circuit 2 that generates and outputs an internal clock signal 3 from the output of the latch circuit 22 and the external clock signal 2.
And 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for simultaneously inspecting a plurality of integrated circuits of a chip formed on a semiconductor wafer in a wafer state while performing delays in the operations of the plurality of integrated circuits. Further, the present invention relates to a semiconductor integrated circuit device capable of inspecting a specific integrated circuit among a plurality of integrated circuits.

[0002]

2. Description of the Related Art In recent years, there has been remarkable progress in miniaturization and price reduction of electronic equipment equipped with a semiconductor integrated circuit device, and accordingly, demands for miniaturization and price reduction of the semiconductor integrated circuit device have increased. ing.

Normally, in a semiconductor integrated circuit device, after a semiconductor chip and a lead frame are electrically connected by bonding wires, the semiconductor chip is supplied in a state of being sealed with resin or ceramics, and is mounted on a printed circuit board. You. However, due to a demand for miniaturization of electronic equipment, a method of directly mounting a semiconductor integrated circuit device in a state of being cut out from a semiconductor (hereinafter, the semiconductor integrated circuit device in this state is referred to as a bare chip or simply a chip) on a circuit board. It has been desired to supply bare chips with guaranteed quality at a low price.

In order to guarantee the quality of bare chips, it is necessary to burn in the semiconductor integrated circuit device in a wafer state.

[0005] However, burn-in performed collectively in a semiconductor wafer state (hereinafter, referred to as wafer burn-in) is very complicated in handling semiconductor wafers, and cannot meet the demand for cost reduction. In addition, since it takes a lot of time to burn-in by dividing a plurality of bare chips formed on one semiconductor wafer one by one or several times many times, it is not possible in terms of time and cost. Therefore, it is required that all bare chips be simultaneously burned in a wafer state at the same time.

Here, a burn-in device capable of performing a wafer burn-in disclosed in Japanese Patent Application Laid-Open No. Hei 8-5666 will be described.

FIG. 7 shows an overview of a conventional wafer burn-in apparatus. As shown in FIG. 7, a wafer burn-in apparatus 100 includes a rack 110 capable of storing a plurality of wafer cassettes 103 in which a wafer tray 101 and a probe card 102 are decompressed and pressed against each other, and a vacuum for maintaining a decompressed state of the wafer cassette 103. It comprises a pump 111 and a drive circuit 112 for electrically driving a plurality of semiconductor integrated circuit devices formed on semiconductor wafers held in the wafer cassette 103, respectively.

[0008]

However, in the conventional wafer burn-in apparatus, a plurality of semiconductor integrated circuit devices formed in a matrix on a semiconductor wafer are collectively or row-wise (column-wise). Since the test is performed on the lined semiconductor integrated circuit devices, the current flowing through a plurality of semiconductor integrated circuit devices selected from external devices transiently increases during about several tens of nanoseconds at the start of operation. There is a problem that the burn-in device, the probe card, and each selected semiconductor integrated circuit device on the inspection side become electrically unstable.

Further, since a plurality of semiconductor integrated circuit devices formed on one semiconductor wafer are collectively inspected, there is a problem that individual states of the semiconductor integrated circuit devices cannot be grasped during the inspection. ing.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problem and disperses a current at the start of operation of a selected semiconductor integrated circuit device when testing a plurality of semiconductor integrated circuit devices at a wafer level. It is a second object of the present invention to monitor the state of one of the plurality of semiconductor integrated circuit devices during inspection.

[0011]

In order to achieve the first object, a first semiconductor integrated circuit device according to the present invention comprises:
A semiconductor integrated circuit device that operates based on a clock signal, and holds a chip ID for identifying one of the plurality of semiconductor integrated circuit devices and selects one of the semiconductor integrated circuit devices. Receiving the ID selection signal, the chip ID, and the external clock signal, and starts outputting the internal clock signal based on the value of the chip ID. Clock signal control means, and the clock signal control means has a counter for integrating the number of pulses of the external clock signal so as to have a cycle whose upper limit is the maximum value of the chip ID.

According to the first semiconductor integrated circuit device, the chip ID holding means for holding a chip ID for identifying one semiconductor integrated circuit device among the plurality of semiconductor integrated circuit devices is provided in the semiconductor integrated circuit device. When an ID selection signal to be selected (activated) is input, the chip ID is output, and a clock signal control unit that receives the chip ID, the ID selection signal, and the external clock signal outputs a signal based on the value of the chip ID. In order to start outputting the internal clock signal, if a unique ID is given to each of the plurality of semiconductor integrated circuit devices, the output start timing of the internal clock signal is shifted for each unique ID.

In the first semiconductor integrated circuit device, the clock signal control means includes a counter for integrating the number of pulses of the external clock signal so as to have a cycle whose upper limit is the maximum value of the chip IDs, and a predetermined counter of the counter. It is preferable to have a clock generation unit that generates an internal clock signal using the value and the external clock signal.

In order to achieve the second object, a second semiconductor integrated circuit device according to the present invention includes a chip ID for identifying one of a plurality of semiconductor integrated circuit devices. Chip ID holding means for holding and outputting a chip selection signal indicating that one semiconductor integrated circuit device has been selected by inputting ID data having the same value as the chip ID; And a specific data output means for outputting an electric signal indicating electric characteristics specific to one semiconductor integrated circuit device.

According to the second semiconductor integrated circuit device, the chip ID holding means for holding the chip ID for identifying one semiconductor integrated circuit device among the plurality of semiconductor integrated circuit devices is provided by the semiconductor integrated circuit device. When ID data coincident with the chip ID is input, a chip selection signal indicating that the chip ID has been selected is output, the chip selection signal is received, and an electric signal indicating electric characteristics unique to the semiconductor integrated circuit device is output. Because it has a unique data output means, for example,
An internal voltage or the like, which is an electric signal unique to the chip, can be output to the outside.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An object of the present invention is to provide an individual semiconductor integrated circuit device capable of performing a stable inspection collectively on a plurality of semiconductor integrated circuit devices formed on one semiconductor wafer. . However, in the following embodiments, only the constituent elements of the invention incorporated in each semiconductor integrated circuit device are described for convenience of explanation.

(First Embodiment) A first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a circuit configuration of an internal clock signal generation circuit of a semiconductor integrated circuit device according to a first embodiment of the present invention. In the present embodiment, a logic circuit,
It is assumed that a semiconductor integrated circuit device that operates with a plurality of clock signals, such as a microcomputer or a synchronous DRAM, is used.

As shown in FIG. 1, the internal clock signal generation circuit 30 includes a chip ID holding circuit 10 and a clock signal control circuit 20.

The chip ID holding circuit 10 includes a first chip ID recording unit 11 for recording a first chip ID (ID0).
And a second chip ID recording unit 12 for recording a second chip ID (ID1) and a third chip ID recording unit 13 for recording a third chip ID (ID2). Each of the units 11, 12, and 13 receives, for example, an ID selection signal 1 output from a burn-in device at a gate, a power supply voltage is applied to a drain, and a source is connected to an output terminal side and connected to a source. It has transistors that are grounded via fuses, and the output data of each transistor is output to the clock signal control circuit 20. Here, each chip ID recording unit 11,
The presence or absence of the fuses 12 and 13 determines the chip ID. In this case, since three chip ID recording sections are provided, eight IDs from 2 to 3 powers, that is, 0 to 7 are assigned. be able to.

The clock signal control circuit 20 includes: an ID selection signal 1; an external clock signal 2;
D outputs from the D recording units 11 to 13 and carry signals B
Is output. And AND
A latch circuit 22 comprising an OR circuit, an inverter circuit, and a shift register, for latching the carry signal B, and a clock generator for generating and outputting an internal clock signal 3 from an output of the latch circuit 22 and an external clock signal 2 As the generation circuit 23.

The chip ID holding circuit 10 has three chip ID recording sections, and as shown in FIG.
Since the fuses of the D recording unit 11 and the third chip ID recording unit 13 have been cut in advance, when the gate is turned on, the first and third chip ID recording units 11,
13 outputs high data, and the second chip ID recording unit 12 outputs low data as a ground potential via a fuse. Therefore, the first chip ID
If the (ID0) side is the MSB, it indicates 101B (B represents a binary number; the same applies hereinafter) as 3-bit data. That is, the chip ID of this integrated circuit device is 5 in decimal, and this 5 of the chip ID is the initial value of the counter 21.

On the other hand, the counter 21 of the clock signal control circuit 20 has counter values of 0, 1,.
It is constituted by, for example, an accumulator (register), which forms one cycle with the maximum value of the 3-bit data such as 0, 1,... And outputs the carry signal B at the timing of returning from 7 to 0.

Hereinafter, the operation of the internal clock signal generation circuit 30 configured as described above will be described with reference to the drawings.

FIG. 2A shows the timing at which the internal clock signal 3 is generated when the chip ID is 5, and FIG. 2B shows the timing at which the internal clock signal 3 is generated when the chip ID is 3. Timing. FIG.
As shown in (a), first, when the ID selection signal 1 is input, the chip ID holding circuit 10 outputs the chip ID 5 to the counter 21. Here, since a load timing is provided until the chip ID, which is the initial value of the counter, is completely input from the chip ID holding circuit 10 to the counter 21, the ID selection signal 1 is the load signal A having a predetermined delay. Is input to the counter 21.

Next, the external clock signal 2 is supplied to the counter 21.
Each time is input, the integrated value of the counter 21 is integrated one by one from the initial value of 5. When the integrated value returns to 0, a carry signal B is generated and output to the latch circuit 22. When the next external clock signal 2 is input, the generation circuit 2
At 3, the internal clock signal 3 is output from the external clock signal 2 and the latch signal C.

Similarly, in FIG. 2B, the chip I
Since D is 3, the timing at which the carry signal B is output from the counter 21 is shifted as compared with the case where the chip ID is 5.

As described above, according to the present embodiment, when the electrical characteristics of a plurality of semiconductor integrated circuit devices formed on one semiconductor wafer are collectively tested, each of the plurality of semiconductor integrated circuit devices is Since different chip IDs are recorded and the initial value of the counter having one cycle is determined according to the chip IDs, the timings at which the counters are cleared to 0 are different from each other. Will be generated. This allows
Even if the ID selection signal 1 is simultaneously turned on (high) from an external device and a plurality of semiconductor integrated circuit devices are selected,
Since the timings at which the currents start to flow in the respective semiconductor integrated circuit devices are shifted from each other to cause a delay, the operations of the inspection device and the respective semiconductor integrated circuit devices are not unstable.

The fuses of the chip ID recording units 11 to 13 in the chip ID holding circuit 10 can be easily blown by trimming using a laser beam.

In addition, not only the fuse but also a storage element such as an antifuse or an EPROM can electrically set an ID.

The chip ID does not necessarily have to be different for each semiconductor integrated circuit device, but may be unique for each block selected.

Further, when the number of semiconductor integrated circuit devices formed on one semiconductor wafer is very large and the internal clock signal generating circuit 30 is to be simplified, the range in which the amount of current can be suppressed is suppressed. Thus, the same chip ID may be assigned to an appropriate number of semiconductor integrated circuit devices.

(Second Embodiment) Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 3 shows a circuit configuration of an internal voltage monitor of a semiconductor integrated circuit device according to a second embodiment of the present invention. As shown in FIG. 3, the internal voltage monitor 31 includes a chip ID holding circuit 40 and an internal voltage output circuit 50 as unique data output means.

The chip ID holding circuit 40 has four chips I
D recording units 41 to 44 indicate that the chip ID can be held as 4-bit data. Each of the chip ID recording units 41 to 44 has one end to which a power supply voltage is applied, the other end connected to an output terminal, and a chip I.
A fuse for determining D is connected between the output terminal and the ground. As shown in FIG.
Since the fuses of the chip ID recording units 41 and 42 are blown and the fuses of the chip ID recording units 43 and 44 are connected, if the chip ID recording unit 44 is set to the MSB, the chip ID becomes 0011B. , Representing 3 in decimal.

The chip ID holding circuit 40 receives the ID data from the external inspection device and the clock signal CLK, and outputs the ID data.
An XNOR circuit, which receives and compares the ID data output from the shift register 45 and each ID signal output from each of the chip ID recording units 41 to 44, and outputs high data if the comparison result is true. And a second comparator 47 that determines the comparison result output from each of the first comparators 46 and outputs a chip selection signal D indicating that the selection has been made if the determined result is true. Have.

The internal voltage output circuit 50 includes a transistor having a gate receiving the chip select signal D, an internal voltage Vcc applied to the drain, and a source connected to the internal pad 60.

The internal pad 60 is connected to a probe terminal of an inspection probe card, and is connected from the probe terminal as a monitor signal line to the inspection device.

Hereinafter, the operation of the internal voltage monitor 31 configured as described above will be described with reference to the drawings.

FIG. 4 shows the timing at which the chip select signal D is generated. In the present embodiment, since the ID data D0 to D3 are input as serial signals,
The chip ID recording units 41, 42, 43, and 44 are shifted by one cycle of the clock signal CLK, respectively, and when ID data is finally input in the order of D0, D1, D2, and D3, externally. If the input ID data is 3, a chip selection signal D is output from the second comparator 47 in the chip ID holding circuit 40. As a result, the internal voltage output circuit in the selected semiconductor integrated circuit device is output. From 50, the internal voltage Vcc is read.

As a matter of course, the externally input I
When the D data has a value other than 3, the internal voltage output circuit 50 does not output an internal voltage value.

The fuses of the chip ID recording sections 41 to 44 in the chip ID holding circuit 40 can be easily blown by trimming using a laser beam.

The ID can be set electrically by using a storage element such as an antifuse or an EPROM without being limited to the fuse.

As described above, according to the present embodiment, when the electrical characteristics of a plurality of semiconductor integrated circuit devices formed on one semiconductor wafer are inspected collectively, each of the plurality of semiconductor integrated circuit devices is If different chip IDs are recorded and a desired chip ID is input from an external inspection device, the internal voltage Vcc of the semiconductor integrated circuit device corresponding to the input chip ID can be read. Therefore, it is possible to read the unique data of one of the plurality of semiconductor integrated circuit devices, so that it is possible to specify whether or not an electrical abnormality has occurred.

Further, since the output data line for monitoring can be shared, the wiring of the probe card and the like can be simplified.

In this embodiment, the internal voltage V
Although cc is a monitoring target, the present invention is not limited to this, and unique data such as a substrate potential may be used.

(Modification of Second Embodiment) Hereinafter, a modification of the second embodiment of the present invention will be described with reference to the drawings.

FIG. 5 shows a circuit configuration of an internal voltage monitor of a semiconductor integrated circuit device according to a modification of the second embodiment of the present invention. 5, the same components as those shown in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted. As shown in FIG. 5, the internal voltage monitor 31 includes a chip ID holding circuit 40A and an internal voltage output circuit 50 as unique data output means.

This modification is different from the second embodiment in that it has a configuration capable of coping with a case where ID data D3 to D0 input from an external device are input in parallel.

That is, each of the first comparators 46 in the chip ID holding circuit 40A is connected to each of the chip ID recording sections 41 to 4
4 as well as ID data input from an external device in parallel from the first comparator 46 on the chip ID recording unit 44 side as D3, D2, D1 and D0.

The output of the second comparator 47 is connected to a shift register 45 which is activated by the ID selection signal 1. The output signal of the shift register 45 becomes a chip selection signal D and an internal voltage output circuit. Output to 50.

Hereinafter, the operation of the internal voltage monitor 31 configured as described above will be described with reference to the drawings.

FIG. 6 shows the timing at which the chip select signal D is generated. In this modification, since the ID data D3 to D0 are input as parallel signals,
When the D data D3 to D0 are input and the ID selection signal 1 is input, if the input ID data D3 to D0 is 3, the chip selection from the shift register 45 in the chip ID holding circuit 40A is performed. The signal D is output, and as a result, the internal voltage Vcc is read from the internal voltage output circuit 50 in the selected semiconductor integrated circuit device.

Further, by using a DQ signal line or an address signal line as an input means of the ID data D3 to D0, it is possible to suppress an increase in the number of wires in a probe card or the like.

As described above, according to the present embodiment, when the electrical characteristics of a plurality of semiconductor integrated circuit devices formed on one semiconductor wafer are collectively inspected, each of the plurality of semiconductor integrated circuit devices has: If different chip IDs are recorded and a desired chip ID is input from an external inspection device, the internal voltage Vcc of the semiconductor integrated circuit device corresponding to the input chip ID can be read. Therefore, it is possible to read the unique data of one of the plurality of semiconductor integrated circuit devices, so that it is possible to specify whether or not an electrical abnormality has occurred.

Further, since the output data line for monitoring can be shared, wiring of the probe card and the like is simplified.

In this embodiment, the internal power supply V
Although cc is a monitoring target, the present invention is not limited to this, and unique data such as a substrate potential may be used.

[0058]

According to the first semiconductor integrated circuit device of the present invention, when a plurality of semiconductor integrated circuit devices are collectively inspected in a state where a plurality of semiconductor integrated circuit devices are formed on one semiconductor wafer. When an ID selection signal indicating that the semiconductor integrated circuit device is selected is input to the chip ID holding unit, the chip ID is output.
The clock signal control means that receives the D selection signal and the external clock signal starts outputting the internal clock signal based on the value of the chip ID. Therefore, if the plurality of semiconductor integrated circuit devices have a unique ID, , The output start time of the internal clock signal is shifted for each unique ID.
As a result, even if an ID selection signal is input from an external device and a plurality of semiconductor integrated circuit devices are selected, each semiconductor integrated circuit device receives a current by an internal clock that starts operating separately based on different chip IDs. , The large current generated in a very short time immediately after the selection is dispersed. Therefore, in each of the semiconductor integrated circuit devices, the timing at which the current starts to flow is shifted, so that the operation of the inspection device and each of the semiconductor integrated circuit devices does not become unstable.

In the first semiconductor integrated circuit device, a counter for integrating the number of pulses of the external clock signal so as to have a cycle whose upper limit is the maximum value of the chip ID, a predetermined value of the counter and the external clock signal And a clock generation unit that generates an internal clock signal using
Since the initial value of the counter is given from the chip ID holding means, the counter having a cycle whose upper limit is the maximum value of the chip IDs starts from the added initial value of the pulse of the external clock signal. Therefore, if the clock generation unit starts outputting the internal clock signal based on the external clock signal, for example, triggered by the counter exceeding the maximum value and returning to the reset state, the internal clock signal starts for each chip ID. The timing can be reliably shifted.

According to the second semiconductor integrated circuit device of the present invention, when a plurality of semiconductor integrated circuit devices are collectively inspected in a state where a plurality of semiconductor integrated circuit devices are formed on one semiconductor wafer, Chip I of a semiconductor integrated circuit device
When the ID data corresponding to D is input, a chip select signal indicating that the semiconductor integrated circuit device has been selected is output, the chip select signal is received, and the electric characteristics unique to the semiconductor integrated circuit device are set. Since the unique data output means for outputting the indicated electric signal is provided, for example, an internal voltage or the like which is an electric signal unique to the chip can be output to the outside. Therefore, it is possible to read the unique data of one of the plurality of semiconductor integrated circuit devices, so that it is possible to specify whether or not an electrical abnormality has occurred.

Further, since the output data line for monitoring can be shared, the wiring of the probe card and the like can be simplified.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an internal clock signal generation circuit of a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2A is a timing chart illustrating an operation of an internal clock signal generation circuit of the semiconductor integrated circuit device according to the first embodiment of the present invention. FIG. 2B is a timing chart illustrating the operation of the internal clock signal generation circuit of the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing an internal voltage monitor of a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 4 is a timing chart illustrating an operation of an internal voltage monitor of a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing an internal voltage monitor of a semiconductor integrated circuit device according to a modification of the second embodiment of the present invention.

FIG. 6 is a timing chart showing an operation of an internal voltage monitor of a semiconductor integrated circuit device according to a modification of the second embodiment of the present invention.

FIG. 7 is a schematic view showing a conventional wafer burn-in apparatus.

[Explanation of symbols]

 Reference Signs List 1 ID selection signal 2 External clock signal 3 Internal clock signal A Load signal B Carry signal C Latch signal D Chip selection signal 10 Chip ID holding circuit 11 First chip ID recording unit 12 Second chip ID recording unit 13 Third Chip ID recording unit 20 Clock signal control circuit 21 Counter 22 Latch circuit 23 Generation circuit (clock generation unit) 30 Internal clock signal generation circuit 31 Internal voltage monitor 41 Chip ID recording unit 42 Chip ID recording unit 43 Chip ID recording unit 44 Chip ID Recorder 45 Shift register 46 First comparator 47 Second comparator 50 Internal voltage output circuit (unique data output means) 60 Internal pad

Claims (3)

[Claims] 1. A semiconductor integrated circuit device that operates based on a clock signal, comprising: a chip ID for identifying one of the plurality of semiconductor integrated circuit devices; Chip ID holding means for outputting the chip ID by receiving an ID selection signal for selecting the semiconductor integrated circuit device, receiving the ID selection signal, the chip ID, and an external clock signal; Clock signal control means for starting output of an internal clock signal based on a value. 2. A counter for integrating the number of pulses of the external clock signal so as to have a cycle whose upper limit is the maximum value of the chip IDs; 2. The semiconductor integrated circuit device according to claim 1, further comprising: a clock generation unit that generates the internal clock signal using a clock signal. 3. When a chip ID for identifying one of the plurality of semiconductor integrated circuit devices is held, and ID data having the same value as the chip ID is input, A chip ID holding unit that outputs a chip selection signal indicating that the one semiconductor integrated circuit device has been selected; and an electric signal that receives the chip selection signal and indicates electric characteristics unique to the one semiconductor integrated circuit device. And a unique data output means for outputting the data.