JPH11110995A - Semiconductor storage device - Google Patents

Abstract

(57) [Summary] To improve the redundancy repair ratio and the flexibility of the redundancy repair in a semiconductor memory device that is redundant in block units. A first storage means of a redundant circuit stores a normal address for selecting a defective cell as a redundant address. The second storage means 5 stores a difference between a normal address AD for selecting a defective cell on a word line WL or a bit line BL different from the defective cell and the redundant address stored in the first storage means 4. . The determination unit 6 determines whether the input regular address AD matches the redundant address stored in the first storage unit 4 or the input regular address A
If the difference between D and the redundant address stored in the first storage means 4 matches the difference stored in the second storage means 5,
A redundant signal JG is generated, and a redundant selection signal Rsel is generated based on the input normal address AD.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a redundant circuit for switching between a defective cell and a redundant cell in a normal cell array.

2. Description of the Related Art In recent years, a semiconductor memory device has achieved high integration and large capacity by miniaturizing its memory cell.
Therefore, the probability of occurrence of a defect in the memory cell increases, and the size of the defect increases not only on one word line or bit line but also on a plurality of adjacent word lines or bit lines. . Therefore, it has become necessary to improve not only the remedy rate of defective cells but also the flexibility of the redundancy rescue.

[0003]

2. Description of the Related Art A DRAM in which a large number of storage cells are formed in a memory cell array includes a normal cell array in which a large number of normal storage cells are formed and a redundant cell array in which a plurality of redundant cells are formed. D configured in this way
In the RAM, when a defective cell is found in a normal cell array by an operation test, a normal address corresponding to the defective cell is stored as a redundant address in a redundant circuit by an operation such as cutting a fuse.

Here, there is a method of performing redundancy repair in a DRAM having a large storage capacity in units of blocks. That is,
One redundant circuit is connected to, for example, two redundant word lines and a redundant cell array as a set of redundant cells. By doing so, the number of redundant circuits can be reduced with respect to the redundant cell array, and an increase in the layout area of the DRAM can be suppressed.

[0005] The redundant circuit is provided with a redundant address determination circuit.
A match / mismatch with the stored redundant address is determined.

In this case, the redundant circuit conventionally switches the word driver for driving the normal cell array to an inactive state when the address information other than the least significant bit of the address matches in the redundant address determination circuit, and switches the redundant cell array to the inactive state. The redundant word driver to be driven is switched to the activated state. That is, two normal cell columns in which only the least significant bit is selected by different consecutive addresses are replaced by two redundant cell columns.

The redundant circuit generates a redundant word line selection signal at the least significant bit of the address so that the redundant driver selects one of the two redundant word lines.

A redundant word driver selects one redundant word line based on a redundant word line selection signal from the redundant circuit, and is selected based on the selected redundant word line and a column selection signal. With the bit line, a redundant cell is selected instead of the defective cell to rescue the defective cell.

[0009]

By the way, in a DRAM memory cell, an address inputted to an address terminal of the DRAM does not always correspond to a physical cell arrangement on a chip. That is, as shown in FIG. 6, the address information of the row address corresponding to four physically continuous normal cell columns C1 to C4 in the memory cell array 6 is X.
AD (i), XAD (i + 2), XAD (i + 1), X
AD (i + 3) may be assigned discontinuously.
This is often due to layout reasons mainly due to chip size restrictions.

For this reason, due to the large storage capacity, failures often occur simultaneously in the physically adjacent normal cell rows C1 and C2. However, in the above-described redundancy repair, two normal cell columns selected by consecutive addresses having different least significant bits are replaced with redundant cell columns. Therefore, addresses are continuous even if they are physically adjacent. Because of this, it cannot be relieved by one block. Therefore, there is a problem that the above-described redundancy relief does not have the flexibility of the redundancy relief and cannot improve the relief rate.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to improve the redundancy repair ratio and the flexibility of the redundancy repair in a semiconductor memory device that is redundant in block units. is there.

[0012]

FIG. 1 is a diagram for explaining the principle of claim 1. That is, the semiconductor memory device includes the selection circuit 1
, A redundancy selection circuit 2 and a redundancy circuit 3, and perform a redundancy operation in units of a redundancy circuit that controls a selection operation of a plurality of redundant word lines RWL or redundant bit lines RBL. Selection circuit 1
Is a plurality of word lines WL normally provided in a cell array.
Alternatively, one of the bit lines BL is selected, and is inactivated based on the input of the redundant signal JG. The redundancy selection circuit 2 is activated based on the input of the redundancy signal JG, and any one of a plurality of redundancy word lines RWL or redundancy bit lines RBL provided in the redundancy cell array based on the input of the redundancy selection signal Rsel. One is selected. When a normal address AD for selecting a defective cell in the normal cell array is input, the redundant circuit 3
A redundancy signal JG is output to the selection circuit 1 and the redundancy selection circuit 2, and a redundancy selection signal Rs is supplied to the redundancy selection circuit 2.
Output el. The redundancy circuit 3 includes a first storage unit 4
And a second storage unit 5 and a determination unit 6. First
Storage means 4 stores a normal address AD for selecting the defective cell as a redundant address. Second storage means 5
Is a word line WL or a bit line B different from the defective cell.
L and the first address AD for selecting a defective cell on L.
The difference between the redundant addresses stored in the storage means 4 is stored. The determination means 6 determines whether the input regular address AD matches the redundant address stored in the first storage means 4 or the inputted regular address AD and the first regular address AD.
The difference between the redundant addresses stored in the storage means 4 is the second
When the difference matches the difference stored in the storage means 5, the redundant signal JG is generated, and the redundant selection signal Rsel is generated based on the input normal address AD.

According to a second aspect of the present invention, in the normal cell array, addresses for selecting a plurality of redundant word lines or redundant bit lines formed physically adjacent to each other are discontinuously assigned.

According to a third aspect of the present invention, the determining means includes a subtractor for calculating a difference between the input normal address and the redundant address stored in the first storage means, The redundant signal is generated when the result of the operation becomes zero or when the result of the operation of the subtractor matches the difference stored in the second storage means.

(Operation) According to the first and second aspects of the present invention, the determining means determines whether the input normal address matches the redundant address stored in the first storage means or the input normal address. If the difference between the address and the redundant address stored in the first storage means matches the difference stored in the second storage means, it is determined that a normal address for selecting a defective cell has been input and the redundant operation is started. Switch. Therefore,
Non-contiguous address or continuous address and 2
Even if two bits have different addresses,
Redundancy can be made simultaneously by one redundant circuit. As a result, since one redundant circuit and one redundant cell array, that is, one block can perform redundancy, the flexibility of the redundancy repair can be improved, and the repair rate can be improved.

According to the third aspect of the present invention, the judgment of the coincidence / mismatch of the addresses by the judging means is performed by the subtracter. Therefore, it is possible to easily perform the address comparison judgment by the judgment means.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention embodied in a DRAM will be described below with reference to FIGS.

FIG. 2 shows an outline of the DRAM. An externally input row address signal XAD is input to a row decoder 2 via a row address buffer 1. A column address signal YAD input from the outside is input to the column decoder 4 via the column address buffer 3.

The row decoder 2 receives the row address signal XA
D, generates a word line selection signal sel and outputs it to a word driver (WD) 5. The word driver 5 selects one of the normal cell arrays 6a in the memory cell array 6 based on the word line selection signal sel. The word line WL is raised to the H level. In the present embodiment,
As shown in FIG. 6, for four physically continuous normal cell columns C1 to C4 in the memory cell array 6, the address information of the row address is XAD (i) and XAD (i), respectively.
(I + 2), XAD (i + 1), and XAD (i + 3) are discontinuously allocated.

The column decoder 4 outputs a column selection signal to the sense amplifier 7 based on the column address signal YAD. Then, one of the storage cells in the normal cell array 6a is selected by the bit line BL selected based on the column selection signal and the word line WL selected by the word driver 5.

The sense amplifier 7 is connected to an I / O buffer 8, and an input / output terminal DQ is connected to the I / O buffer 8. At the time of the cell information write operation, the write data externally input to the input / output terminal DQ is I / O
The data is written to the selected memory cell via the O buffer 8 and the sense amplifier 7.

At the time of reading the cell information, the cell information read from the selected storage cell is input to the sense amplifier 7 and the I / O buffer 8, and from the I / O buffer 8 to the input / output terminal DQ. Read data is output.

The row address signal XAD is input to the redundancy circuit 9 via the row address buffer 1. In the redundant circuit 9, a normal address corresponding to a defective cell in the normal cell array 6a found by the operation test is stored as a redundant address. This redundant circuit 9 has a plurality (see FIG. 2).
Only one is shown).

When the input row address signal XAD determines that the normal address corresponding to the defective cell coincides with the redundant address, the redundant circuit 9 outputs, for example, an H-level redundant signal JG and outputs a redundant word driver (G). RWD)
10 is activated and the word driver 5 is deactivated.

The redundant word drivers 10 are provided in the same number as the redundant circuits 9, and each redundant word driver 10 is connected to two redundant word lines RWL0, RWL1 and a redundant cell array 6b which is a set of redundant cells. . That is,
The redundant circuit 9 and the redundant word driver 10 simultaneously connect the two word lines WL of the normal memory cell 6a to the redundant word line R.
Replace with WL0 and RWL1.

In addition, the redundant circuit 9 generates a redundant word line selection signal Rsel0, Rsel0, so that the redundant word driver 10 selects one of the two redundant word lines RWL0, RWL1 based on the stored redundant address. Rsel1
Is switched to, for example, the H level.

The redundant word driver 10 selects one redundant word line RWL0 (RWL1) based on one of the redundant word line selection signals Rsel0 and Rsel1 input from the redundant circuit 9, and selects the selected redundant word line RWL0 (RWL1). By the redundant word line RWL0 (RWL1) and the bit line BL selected based on the column selection signal, a memory cell in the redundant cell array 6b is selected instead of the defective cell.

FIG. 3 shows the redundant circuit 9. The redundancy circuit 9 includes a redundancy address determination circuit 11 and first and second R
OM12 and OM13. The row address signal XAD is input to the redundant address determination circuit 11 via the row address buffer 1.

In the first ROM 12, a normal address corresponding to a defective cell in the normal cell array 6a found by an operation test is stored as a redundant address. That is, the first ROM 12 stores the address information RO of the redundant address.
M (i) is stored, and information for outputting a redundancy permission signal ROMj (for example, H level) indicating the use state of the redundancy circuit 9 is stored.

The second ROM 13 stores a difference between a normal address corresponding to a defective cell on a different word line WL and an address corresponding to the defective cell. Here, in the memory cell array 6 of the present embodiment, since the difference between the addresses of four physically continuous normal cell columns C1 to C4 is "2" at the maximum, the second ROM
Reference numeral 13 is configured to be able to store 2-bit information. Therefore, the second ROM 13 can store the difference between “1” and “3”.

In this embodiment, when a defective cell is simultaneously generated in a physically continuous normal cell row, the smaller address is used as a redundant address in the first ROM 1.
2 and the second ROM 13 stores the difference from the smaller address.

Therefore, for example, the normal cell row C shown in FIG.
1 and C2, the first ROM
12 stores the address information XAD (i) of the row address, and the second ROM 13 stores the difference "2" between the addresses of the normal cell columns C1 and C2. Also, the normal cell row C
2 and C3, the first ROM
12 stores the address information XAD (i + 1) of the row address, and the second ROM 13 stores the normal cell columns C2 and C3.
Is stored as the address difference "1". Further, when defective cells occur simultaneously in the normal cell columns C3 and C4, the first R
The OM 12 has address information XAD (i +
1) is stored in the second ROM 13 and the normal cell row C
The difference "2" between the addresses 3 and C4 is stored.

The redundant address judging circuit 11 outputs the first RO
An address information ROM (i) of the redundancy permission signal ROMj and the redundancy address stored in the M12;
And outputs the redundant signal JG to the word driver 5 and the redundant word driver 10 and the redundant word line selection signal Rse.
10 and Rsel1 are output.

FIG. 4 shows a specific configuration of the redundant circuit 9. The redundant address determination circuit 11 of the redundant circuit 9 includes the same number of full adders FA0 to FAi as the number of bits of the row address signal XAD (XAD0 to XADi).

The input terminals X of the full adders FA0 to FAi are connected to each bit XAD0 of the row address signal XAD from the full adder FA0 corresponding to the least significant bit to the full adder FAi corresponding to the most significant bit. To XADi are input in order from the lower bit.

The input terminals Y of the full adders FA0 to FAi are connected to the respective bits ROM0 to ROMi of the redundant address stored in the first ROM from the full adder FA0 to the full adder FAi in the same manner as described above. Are inverted by the inverter circuit 14 in order from the lower bit and input.

An H level signal is always input to the input terminal Z of the full adder FA0 corresponding to the least significant bit. Output signals C0 to Ci-1 output from carry terminals C of full adders FA0 to FAi-1 are input to input terminals Z of full adders FA1 to FAi corresponding to the upper bits, respectively. The carry terminal C of the full adder FAi corresponding to the most significant bit is an open terminal.

The full adders FA0 to FA configured as described above
i is each bit XAD0 to XA of the row address signal XAD.
Di and each bit ROM0 of the inverted redundant address.
ROMi is added. That is, full adders FA0 to FAi
And an inverter circuit 14, which constitutes a subtractor. From each bit XAD0 to XADi of the row address signal XAD,
The bits ROM0 to ROMi of the redundant address are subtracted.

Accordingly, when each bit XAD0 to XADi of the row address signal XAD matches each bit ROM0 to ROMi of the redundant address stored in the first ROM 12, that is, when the result of the subtraction is zero, the full adders FA0 to XADi FAi outputs L-level output signals S0 to Si from output terminal S.

Each bit X of row address signal XAD
When AD0 to XADi is greater than each bit ROM0 to ROMi of the redundant address stored in the first ROM 12 by "1", that is, when the subtraction result is "1", only the full adder FA0 outputs the H level output signal S0. Output.

Each bit X of the row address signal XAD is
When AD0 to XADi is larger than each bit ROM0 to ROMi of the redundant address stored in the first ROM 12 by "2", that is, when the subtraction result is "2", only the full adder FA1 outputs the H level output signal S1. Output.

Further, when each bit XAD0 to XADi of the row address signal XAD is larger than each bit ROM0 to ROMi of the redundant address stored in the first ROM 12 by "3", that is, when the result of the subtraction is "3", Adder FA
0 and FA1 both output H-level output signals S0 and S1.

The bits XAD0 to XADi of the row address signal XAD are "1" to "0" from the bits ROM0 to ROMi of the redundant address stored in the first ROM 12.
If there is a mismatch except when it is greater than "3", at least one of the full adders FA2 to FAi of lower three bits or more outputs the output signals S2 to Si at the H level.

Output terminals S of the full adders FA0 to FAi
Are input to the NOR circuit 15a. Also, the lower 2 bits full adders FA0, FA1
The output signals S2 to Si output from the output terminals S of the full adders FA2 to FAi except for the above are input to the NOR circuit 15b. Output signals S0 and S1 output from the output terminals S of the lower two-bit full adders FA0 and FA1 are supplied to the NOR circuit 15 via EOR circuits 16a and 16b, respectively.
b.

The second ROM 13 has fuses f0 and f1 corresponding to two bits. The input terminal of the EOR circuit 16a is connected to a power supply VCC via a latch circuit 17a composed of two inverter circuits and a resistor R.
, And to the ground GND via the latch circuit 17a and the fuse f0.

The other input terminal of the EOR circuit 16b is connected to the power supply VCC through a latch circuit 17b composed of two inverter circuits and a resistor R, and is connected to the ground GN through the latch circuit 17b and fuse f1.
D is connected.

Incidentally, the second ROM 13 of the present embodiment
When only the fuse f1 is cut, the fact that the difference with respect to the redundant address is "1" is stored, and
When only 0 is disconnected, the difference with respect to the redundant address is “2”.
Is stored, and when the fuses f0 and f1 are both blown, it is stored that the difference with respect to the redundant address is "3".

The output signals of the NOR circuits 15a and 15b are output to input terminals of an OR circuit 18, respectively. O
The output signal of the R circuit 18 is input to the NAND circuit 19. The other input terminal of the NAND circuit 19 is connected to the first input terminal.
Enable signal RO based on the information stored in the ROM
Mj is input. The NAND circuit 19 outputs NO
The redundancy signal JG is generated by the output signal of the R circuit 15 and the redundancy permission signal ROMj. The redundant circuit 9
Is unused, the L-level redundancy permission signal ROMj is input, so that the NAND circuit 19 outputs an L-level redundancy signal JG.

The output signals of the NOR circuits 15a and 15b are output to the redundant word driver 10 as redundant word line selection signals Rsel0 and Rsel1, respectively.

FIG. 5 shows the redundant word driver (RW
D) A specific configuration of 10 is shown. Redundant word driver 10
Is composed of two AND circuits 20 and 21. AND
The output signal of the NOR circuit 15a, that is, the redundant word line selection signal Rsel0 is input to one input terminal of the circuit 20, and the redundant signal JG is input to the other input terminal. The output terminal of the AND circuit 20 is connected to one redundant word line RWL0.

The output signal of the NOR circuit 15b, that is, the redundant word line selection signal Rsel1 is input to one input terminal of the AND circuit 21, and the redundant signal JG is input to the other input terminal. The output terminal of the AND circuit 21 is connected to the other redundant word line RWL1.

When the redundant circuit 9 is not used, the redundant signal JG is fixed at L level.
0 and 21 hold the redundant word lines RWL0 and RWL1 in an inactive state (L level).

In the redundant circuit 9 configured as described above, as shown in FIG.
1 and C2, the first R
OM12 has address information XAD of normal cell column C1.
(I) is stored as the address information ROM (i) of the redundant address. The second ROM 13 stores the difference “2”.
Is stored.

That is, the second second ROM 13 shown in FIG.
In the above, only the fuse f0 is blown to store the difference “2” with respect to the redundant address. Then, an L-level signal is input from the latch circuit 17a to the EOR circuit 16a, and the latch circuit 1 is input to the EOR circuit 16b.
An H-level signal is input from 7b.

(In the case where the address of the normal cell column C1 is input) In this case, the currently input row address signal XA
D are stored in the first ROM 12
Bits ROM0 to ROM of the redundant address stored in the ROM
matches i. Therefore, the redundant address determination circuit 11
Since the subtraction result is zero, the full adders FA0 to FA0
FAi both output L-level output signals S0 to Si. Then, the NOR circuit 15a outputs an H-level output signal, that is, an H-level redundant word line selection signal Rsel0.

At this time, since an H level signal is input to the EOR circuit 16b from the latch circuit 17b, the output signal of the EOR circuit 16b becomes H level.
Then, the NOR circuit 15b outputs an L-level output signal, that is, an L-level redundant word line selection signal Rsel1.

Accordingly, the OR circuit 18 outputs an H-level output signal to the AND circuit 19. This AND circuit 19
Is supplied with the H-level redundancy permission signal ROMj, the AND circuit 19 outputs the H-level redundancy signal JG.
Is output.

That is, in FIG. 5, the AND circuits 20 and 21 of the redundant word driver 10 apply the H-level redundant signal J.
G is input. Then, based on the H level redundant word line selection signal Rsel0, the AND circuit 20 rises to the H level to select the redundant word line RWL0. Further, the AND circuit 21 generates a redundant word line RW based on the redundant word line selection signal Rsel1 at L level.
L1 is held at the L level so as to be in the non-selected state.

(In the case where the address of the normal cell column C2 is input) In this case, the currently input row address signal XA
D are stored in the first ROM 12
Bits ROM0 to ROM of the redundant address stored in the ROM
"2" larger than i. Therefore, in the redundant address determination circuit 11, since the subtraction result is “2”, only the full adder FA1 outputs the output signal S1 at the H level.
Then, the NOR circuit 15a outputs an L-level output signal, that is, an L-level redundant word line selection signal Rsel0.

At this time, since the H level signal is input from the latch circuit 17b to the EOR circuit 16b, the output signal of the EOR circuit 16b becomes L level.
The fact that the output signal of the EOR circuit 16b becomes L level means that the subtraction result of the redundant address determination circuit 11 is:
This means that the difference stored in the second ROM 13 matches. Then, the NOR circuit 15b outputs an H-level output signal, that is, an H-level redundant word line selection signal Rse.
11 is output.

Accordingly, the OR circuit 18 outputs an H level output signal to the AND circuit 19. This AND circuit 19
Is supplied with the H-level redundancy permission signal ROMj, the AND circuit 19 outputs the H-level redundancy signal JG.
Is output.

That is, in FIG. 5, the H-level redundant signal J is supplied to the AND circuits 20 and 21 of the redundant word driver 10.
G is input. Then, the AND circuit 20 holds the redundant word line RWL0 at the L level so as to be in a non-selected state based on the redundant word line selection signal Rsel0 at the L level. Further, the AND circuit 21 rises to H level to select the redundant word line RWL1 based on the L level of the redundant word line selection signal Rsel1.

(In the case where an address other than the normal cell columns C1 and C2 is input) In this case, the bits XAD0 to XADi of the currently input row address signal XAD correspond to the redundant address stored in the first ROM 12. Each bit ROM
The difference from 0 to ROMi is other than “2”. Therefore, in the redundant address determination circuit 11, at least one of the full adders FA0 or the full adders FA2 to FAi outputs the output signals S0, S2 to Si at the H level. Then, NOR
Circuits 15a and 15b both output L-level output signals to O
Output to the R circuit 18.

Therefore, the OR circuit 18 outputs an L-level output signal to the AND circuit 19. This AND circuit 19
Outputs an L-level redundancy signal JG regardless of the redundancy permission signal ROMj.

That is, in FIG. 5, the L level redundant signal J is applied to the AND circuits 20 and 21 of the redundant word driver 10.
Since G is input, the AND circuits 20 and 21 hold the redundant word lines RWL0 and RWL1 at the L level in order to make both of them unselected.

As described above, the redundant circuit 9 is configured as shown in FIG.
As shown in FIG. 3, physically adjacent normal cell columns C1, C2
, And even if the address information XAD (i) and XAD (i + 2) of the row address signal XAD corresponding to the normal cell columns C1 and C2 are discontinuous, one redundant circuit 9 enables redundancy.

The redundancy circuit 9 of the present embodiment cuts the fuses f0 and f1 in combination according to the difference between the row address signals XAD even when the difference between the row address signals XAD is "1" or "3". In the same manner as in the case where the difference is “2”, redundancy can be performed by one redundant circuit 9. That is, in the present embodiment, even if the continuous normal cell row is a continuous address and the two bits are different addresses, the difference is “1”. Can be redundant. Therefore, the row address signal XAD
Is a discontinuous address or a continuous address and two bits have different addresses, but if the difference is between "1" and "3", one redundant circuit and one redundant The cell array, that is, one block can be made redundant.

As described above, this embodiment has the following operation and effects. (1) In the redundant circuit 9 of the present embodiment, even if a defective cell is simultaneously generated in the physically adjacent normal cell columns C1 and C2 and the address difference between the cell columns C1 and C2 is "2", At the same time, redundancy can be achieved by one redundant circuit 9 and one redundant word driver 10. Therefore, since redundancy can be performed without using unnecessary redundant circuits and redundant word drivers, etc.,
The redundancy rescue rate can be improved.

(2) In addition, by combining and cutting the fuses f0 and f1 of the second ROM 13, it is possible to freely set and store the difference between "1" and "3". . Therefore, the flexibility of the redundancy relief can be improved.

(3) The redundant address determination circuit 11 includes a subtractor composed of full adders FA0 to FAi. Therefore, comparison of addresses in the redundant address determination circuit 11 can be easily performed.

The present invention may be embodied in the following modes in addition to the above embodiment. In the above embodiment, two redundant word lines RWL are added to the redundant word driver 10 controlled by one redundant circuit 9.
Although 0 and RWL1 are connected, three or more redundant word lines may be connected. in this case,
If there are three redundant word lines, the first ROM 1
It is necessary to store two differences from the redundant address stored in the NOR circuits 15a and 15b in parallel with the NOR circuits 15a and 15b.
It is necessary to provide a circuit and newly provide an EOR circuit, a latch circuit, a fuse, and the like. That is, it is necessary to appropriately change the portion surrounded by the alternate long and short dash line shown in FIG.

In the above embodiment, the EOR circuit 16 is connected to each output terminal S of the full adders FA0 and FA1 of lower 2 bits.
a and 16b are connected to each other, and the difference from the redundant address is stored from "1" to "3" depending on whether or not the fuses f0 and f1 are cut. However, the EOR circuits 16a and 16b store all of the bits. The difference from the redundant address may be changed by connecting to any one of the output terminals S of the adders FA0 to FAi.
In addition, the number of EOR circuits, fuses, and the like may be increased as appropriate, and a change may be made to store a difference from a redundant address of 3 bits or more.

In the above embodiment, the second ROM 13
Is composed of the latch circuit 17, the fuses f0 and f1, and the resistor R, but the configuration is not limited to this as long as the operation can be performed in the same manner as above.

In the above embodiment, the first ROM 12
Stores the minimum address as a redundant address in the second
Although the difference from the smallest address is stored in the ROM 13 of the first embodiment, the present invention is not limited to this.
Stores the maximum address as a redundant address,
ROM 13 may store the difference from the maximum address.

In the above embodiment, the full adders FA0 to FA0
Although the subtractor is configured by the FAi and the inverter circuit 14, the circuit configuration is not limited to this, as long as the difference between the addresses can be detected.

In the above embodiment, the redundancy is implemented on the word line WL side, but may be implemented on the bit line BL side.

[0077]

As described in detail above, according to the present invention,
In a semiconductor memory device that is redundant in block units, the redundancy repair ratio and the flexibility of the redundancy repair can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram showing an outline of a DRAM of the embodiment.

FIG. 3 is a block diagram showing a redundant circuit;

FIG. 4 is a circuit diagram showing a specific configuration of a redundant circuit.

FIG. 5 is a circuit diagram showing a specific configuration of a redundant word driver.

FIG. 6 is an explanatory diagram showing a relationship between a normal cell column and a row address of a memory cell array.

[Explanation of symbols]

 1 selection circuit 2 redundancy selection circuit 3 redundancy circuit 4 first storage means 5 second storage means 6 determination means AD normal address WL word line BL bit line RWL redundant word line RBL redundant bit line JG redundant signal Rsel redundant word line selection signal

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Mutsuya Nakaya 2-1844-2 Kozoji-cho, Kasugai-shi, Aichi Prefecture Inside Fujitsu VSI Co., Ltd. (72) Yasuo Fukasawa 2-1844-1 Kozoji-cho, Kasugai-shi, Aichi 2 Inside Fujitsu VSI Ltd. (72) Inventor Shuichi Saito 2-1844-2 Kozoji-cho, Kasugai-shi, Aichi Prefecture Inside Fujitsu VSI

Claims (3)

[Claims] A selector circuit for selecting one of a plurality of word lines or bit lines provided in a normal cell array and inactivating based on a redundant signal input; A redundant selection circuit that is activated based on the input of the redundant cell array and selects one of a plurality of redundant word lines or redundant bit lines provided in the redundant cell array based on a redundant selection signal input; When a normal address for selecting a defective cell in the cell array is input, the redundant circuit outputs a redundant signal to the selecting circuit and the redundant selecting circuit, and outputs a redundant selecting signal to the redundant selecting circuit. A semiconductor memory device performing a redundancy operation in units of a redundancy circuit for controlling a selection operation of a redundancy word line or a redundancy bit line, wherein the redundancy circuit selects the defective cell. Storage means for storing a normal address to be used as a redundant address, a normal address for selecting a defective cell on a word line or a bit line different from the defective cell, and a redundant address stored in the first storage means. And a second storage unit for storing the difference between the normal address and the redundant address stored in the first storage unit, or storing the input normal address and the normal address in the first storage unit. When the difference between the input redundant addresses matches the difference stored in the second storage means, the redundant signal is generated, and the redundant selection signal is generated based on the input normal address. A semiconductor storage device comprising: 2. The semiconductor memory according to claim 1, wherein the normal cell array has a configuration in which addresses for selecting a plurality of redundant word lines or redundant bit lines formed physically adjacent to each other are discontinuously assigned. apparatus. 3. The determining means includes a subtractor for calculating a difference between an input normal address and a redundant address stored in the first storage means, and the result of the subtractor becomes zero. 3. The semiconductor memory device according to claim 1, wherein the redundant signal is generated when the operation result of the subtractor matches a difference stored in the second storage unit. 4.