JPH11110344A - Bus arbitration equipment - Google Patents

Abstract

(57) [Problem] To provide a bus arbitration device which can flexibly cope with a change in system configuration, does not generate redundant arithmetic processing, and has a small circuit scale. SOLUTION: A bus controller 105 detects a plurality of devices 104 that can be bus masters, and notifies circuit circuit setting means 103 and signal connection means 106 of the information. The circuit data setting means 103 selects optimum circuit data from the circuit data storage means 102 according to the information and sets the optimum circuit data in the rewritable arbitration circuit 101. The arbitration circuit 101 arbitrates a bus request signal from the device 104 input via the signal connection means 106 by a circuit determined by the set circuit data, and provides a bus grant to the device 104 which permits use of the bus. Output a signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus arbitration device, and more particularly, to a bus arbitration device that arbitrates for a right to use a bus when receiving a bus request signal requesting bus use for one bus from a plurality of devices. Related to the device.

[0002]

2. Description of the Related Art In a system in which a plurality of devices are connected to one common bus, each device can use the bus by time sharing. The bus arbitration device arbitrates bus request signals from a plurality of devices to give one device a right to use the bus. This arbitration method includes round robin (round robin).
n) There are a method and a priority method. A device that has obtained the right to use the bus is called a bus master.

In the round robin method, each device is given a right to use a bus fairly. In this case, even when a bus request signal is output from a plurality of devices, the devices are sequentially and cyclically polled to release the bus at fixed time intervals, and the bus request signal is output to the device for which the bus request signal is output. And outputs a bus grant signal for granting the right to use the bus. The device that has received the bus grant signal can perform processing such as data transfer using the bus within a given fixed time. On the other hand, in the priority system, when a bus request signal is output from a plurality of devices, the bus is preferentially released to a device having a more urgent degree and a bus grant signal is output.

[0004]

However, in a conventional bus arbitration apparatus, for example, in a round robin system, the number of devices that can be a bus master is set, and the arbitration system is determined according to the system configuration of the fixed set number. Therefore, when the number of devices to be actually connected is smaller than the set number, there is a problem that the bus is invalidated and the bus is invalidated by polling the devices not connected. On the other hand, in the case of a system configuration in which the number of devices that can become a bus master is larger than the set number, an arbitration method has to be constructed again. In addition, since each device needs to perform processing such as data transfer within a certain period of time, the number of connected devices is limited according to its maximum transfer capability. Furthermore, during the operation of the system, it is not possible to cope with a change in the number of devices that can become bus masters.

[0005] For this reason, a bus arbitration device has been proposed which has flexibility in changing the system configuration. For example, in the bus arbitration apparatus disclosed in Japanese Patent Laid-Open No. Hei 7-244635, a plurality of priority determining means for device selection are provided in advance, and processing is performed for each priority determining means. The arbitration is multiplexed by selecting one or more priority order determining means by means and control means, thereby providing flexibility in changing the system configuration. However, in such a priority method using the bus arbitration device, the arithmetic processing for determining the priority is performed by a plurality of priority determining means at the same time, so that the arithmetic processing of the non-selected priority determining means is redundant and wasteful. . Further, the circuit scale becomes large, which has caused an increase in cost.

[0006] The present invention has been made in view of the above, and can flexibly cope with changes in the system configuration.
An object of the present invention is to provide a bus arbitration device that does not generate redundant arithmetic processing and has a small circuit size.

[0007]

According to a first aspect of the present invention, there is provided a bus arbitration apparatus which arbitrates a bus request signal from a plurality of devices which are connected to a single bus and can be a bus master. A bus arbitration device that stores a plurality of types of circuit data as circuit configuration information, and determines a connection state of an internal circuit according to the set circuit data, and determines a plurality of connection states according to the determined circuit. Arbitrates bus request signals from other devices,
Rewritable arbitration circuit means for outputting a bus grant signal to the device according to the arbitration result; and circuit data setting means for selecting at least one type of circuit data from the circuit data storage means and setting the selected data in the arbitration circuit means. It is provided.

That is, according to the bus arbitration apparatus of the first aspect, the arbitration circuit means in which circuit data can be rewritten,
Optimal circuit data selected from a plurality of types of circuit data is set, the connection state of the internal circuit is determined, and bus request signals from a plurality of devices are arbitrated by the determined circuit.

[0009] In the bus arbitration device according to claim 2,
In claim 1, the circuit data setting means selects circuit data according to a connection status of a device that can be a bus master to one bus.

That is, according to the bus arbitration apparatus of the second aspect, when selecting circuit data, it detects whether or not a device is connected to the bus and selects it.

In the bus arbitration device according to claim 3,
3. The arbitration circuit means according to claim 1, wherein a bus request signal output from a plurality of devices and an input port of the plurality of bus request signals of the arbitration circuit means are arbitrarily associated with each other and connected based on the bus master information. There is provided signal connection means for connecting the output ports of the plurality of bus grant signals and the bus grant signals input to the plurality of devices in any correspondence.

That is, according to the bus arbitration apparatus of the third aspect, the correspondence between the bus request signal from the device and the bus grant signal to the device and the signal processed in the arbitration circuit means can be freely changed.

According to a fourth aspect of the present invention, in the bus arbitration apparatus according to the third aspect, the signal connection means determines the connection of the priority system based on the bus master priority information.

In other words, according to the bus arbitration device of the present invention, the bus arbitration device outputs a bus request signal from the device, a bus grant signal to the device, and a signal processed in the arbitration circuit based on the bus master priority information. Change the correspondence freely.

According to a fifth aspect of the present invention, in the bus arbitration device according to any one of the first to fourth aspects, the circuit data setting means operates the device arbitrated by a circuit determined by arbitrary circuit data. Also, the circuit data of the arbitration circuit is changed to another circuit data and set.

That is, according to the bus arbitration device of the present invention, during system operation, the circuit data of the arbitration circuit is freely changed to other circuit data.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a bus arbitration device of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of the system configuration of the bus arbitration device according to the embodiment. Arbitration circuit 101
Is arbitration circuit means (corresponding to the arbitration circuit means of the present invention) constituted by a rewritable programmable device that determines a connection state of an internal circuit according to circuit data. The programmable device in this embodiment is an SRAM-based FPGA (Field Programmable G
ate Array). SRAM-based FP
In the GA, the circuit data is stored in the SRAM in the FPGA chip.
Since it is set above, other circuit data can be set even when the power is turned on or the system is operating.

The circuit data storage section 102 (corresponding to the circuit data storage means of the present invention) stores a plurality of types of circuit data set in the arbitration circuit 101. The circuit data storage unit 102 may be composed of a ROM, for example, and may be a plurality of ROMs for each circuit data, or may store circuit data in each of a plurality of areas of a single ROM. The circuit data setting unit 103 (corresponding to a circuit data setting unit of the present invention) selects and reads at least one type of circuit data stored in the circuit data storage unit 102 and sets the circuit data in the arbitration circuit 101.

The plurality of devices 104 are connected to a system bus (hereinafter, referred to as “bus”). Devices include those whose connection status changes depending on the user, such as an external storage device. Each device 104 outputs a bus request signal to the arbitration circuit 101 to request a right to use the bus. The bus controller 105 performs control other than bus arbitration on each device 104.

The signal connection unit 106 (corresponding to the signal connection means of the present invention) converts a bus request signal from each device 104 into a bus request signal that can be processed in the arbitration circuit 101, and converts the bus request signal from the arbitration circuit 101. The grant signal is converted into a bus grant signal that can be processed by each device 104. The signal connection unit 106 does not directly depend on the bus arbitration system, and thus is independent of the arbitration circuit 101. The description of the connection of the signal connection unit 106 will be further described later.

Next, the operation of the bus arbitration apparatus configured as described above will be described.

When the system shown in FIG. 1 is started, the bus controller 105 detects the device connection status of the bus and detects whether or not each device 104 can become a bus master. Then, the information of the detection result is notified to the circuit data setting unit 103. The circuit data setting unit 103 selects and reads out optimal circuit data from the circuit data stored in the circuit data storage unit 102 in accordance with information from the bus controller 105, and sets the selected circuit data in the SRAM of the arbitration circuit 101. Then, the initialization of the bus use ends.

Thereafter, the device 104 outputs a bus request signal to the arbitration circuit 101, and the arbitration circuit 101
Performs arbitration when a bus request signal is output from a plurality of devices 104, and outputs a bus grant signal to the device 104 that permits use of the bus. The device 104 that has received the bus grant signal activates the bus busy signal to use the bus. After the use of the bus is completed, the bus busy signal is made inactive, and the completion of the use of the bus is notified to the arbitration circuit 101 and the bus controller 105. Then, the arbitration circuit 101 enters the next bus arbitration.

Next, an example of an optimal bus arbitration method for different system configurations will be described. For example, in the case of the round robin method in which the number of devices that can become bus masters is six, the circuit data setting unit 103 has a circuit configuration that fairly grants the right to use the bus to the six devices 104. The arbitration circuit 10 selects circuit data and reads the circuit data from the circuit data storage unit 102.
1 SRAM. Then, the arbitration circuit 101
As shown in the state transition diagram of FIG. 2, the state is changed for the devices # 1 to # 6, and the bus request signal output from each device 104 is sequentially and cyclically polled to determine whether or not it is active. To detect. Then, a bus grant signal is output so as to give the right to use the bus for a predetermined time to each device 104 that has output the active bus request signal. Thereafter, the state transition is stopped until the bus use by the device 104 ends.

In the case of the round robin method in which the number of devices that can be a bus master is two, the circuit data setting unit 103 has a circuit configuration that imparts the right to use the bus fairly to the two devices 104. Is selected, the circuit data is read from the circuit data storage unit 102, and is set in the SRAM of the arbitration circuit 101. Then, the arbitration circuit 101 alternately transitions the state between the two devices # 1 and # 2 as shown in the state transition diagram in FIG. 3, and determines whether the bus request signal output from each device 104 is active. Are alternately polled and detected. Then, a bus grant signal is output so as to give the right to use the bus for a predetermined time to each device 104 that has output the active bus request signal. Thereafter, the state transition is stopped until the bus use by one device 104 ends.

Next, a description will be given of an example of a priority system in which the priority of a specific device 104 is increased rather than imparting a bus use right fairly to each device 104 in the round robin system. In the case where the number of devices that can become bus masters is device # 1 to device # 6,
To increase the priority for one device # 1, circuit data corresponding to the bus arbitration is read from the circuit data storage unit 102 and set in the SRAM of the arbitration circuit 101. Then, as shown in the state transition diagram of FIG. 4, by increasing the number of polling states for the device # 1, the frequency of detecting the bus request signal from the device # 1 increases, and the priority improves.

As described above, by configuring the arbitration circuit 101 with a rewritable programmable device that determines the connection state of the internal circuit according to the circuit data, the system configuration changes regardless of the number of devices that can become the bus master. Can respond flexibly. Also, one arbitration circuit 1
Since 01 is set in a plurality of circuit configurations and only the arithmetic processing required for the system configuration is performed, a bus arbitration device with a small circuit size without redundant arithmetic processing can be realized.

Next, the signal connection unit 1 in the priority order system
The operation of 06 will be described with reference to FIG.

In the system according to this embodiment, eight devices can be connected to the bus as in a general system. Now, among the eight devices # 1 to # 8, devices # 3, # 5, and # 8 are devices that can be bus masters. The 8-bit bus master information is notified from the bus controller 105 to the circuit data setting unit 103 and the signal connection unit 106. Further, the bus master priority information is notified to the circuit data setting unit 103 and the signal connection unit 106. In this case, device # 5, device # 3,
It is assumed that the priorities are set in the order of device # 8. In the arbitration circuit 101, bus request signals and bus grant signals to be used are allocated in advance in ascending order from the lower number. Therefore, in the case of the priority system, the lower the number, the higher the priority.

The circuit data setting section 103 selects and reads the optimum circuit data from the circuit data storage section 102 in accordance with the bus master information and the bus master priority information, and sets the selected circuit data in the SRAM of the arbitration circuit 101. On the other hand, the signal connection unit 106 obtains the number of devices that can become the bus master according to the bus master information, that is, three devices in this case, and transfers three bus request signals connected to the arbitration circuit 101 to the bus master. Get device # 3, #
5. Connect to # 8 bus request signal. In this case, as shown in FIG. 5, the bus request signals BR1a, BR2a, BR3 of lower numbers of the arbitration circuit 101.
a is connected to the bus request signals BR5, BR3 and BR8 of the devices # 5, # 3 and # 8 based on the bus master priority information (3 bits in this case). Similarly, the lower number bus grant signal of the arbitration circuit 101 is
Based on the bus master priority information, devices # 5, # 5
3, # 8 bus grant signals BG5, BG3, B
Connect to G8.

FIG. 6 shows an example of a state transition diagram in this case.
That is, the polling state of the device # 5 having the highest priority is the highest, and the polling state of the device # 3 having the second highest priority is the next highest.

As described above, based on the bus master information, the signal connection unit 106 connects the bus request signals output from the plurality of devices 104 that can become bus masters and the input ports of the plurality of bus request signals of the arbitration circuit 101 to each other. The plurality of bus grant signal output ports of the arbitration circuit 101 are arbitrarily connected to the plurality of bus grant signals input to the plurality of devices 104. Therefore, flexibility can be given to the connection position of the device.

Further, the signal connection unit 106 determines the connection of the priority system based on the bus master priority information. Therefore, the bus arbitration of the priority system can be performed using the signal connection unit 106.

As described above, the SRAM-based FPG
In A, since the circuit data is set on the SRAM in the FPGA chip, other circuit data can be set even when the power is turned on or the system is operating. For this reason, the circuit data setting unit 103 can change and set another circuit data even when the device arbitrated by the circuit determined by the arbitrary circuit data is operating (that is, during system operation). For example, during system operation, when one of the devices connected to the bus is turned off, or when a malfunction occurs, the bus controller 105 sets this device to the bus non-use, and
The circuit data setting unit 103 is instructed to set new circuit data to the arbitration circuit 101. At the same time, it outputs bus master information to the signal connection unit 106 to change the connection. Therefore, it is possible to flexibly cope with not only the system configuration before the system startup but also the change of the system configuration after the system startup, and to perform optimal bus arbitration.

[0036]

The bus arbitration apparatus according to the present invention (Claim 1)
According to the method, the optimal circuit data selected from a plurality of types of circuit data is set in the arbitration circuit means in which the circuit data can be rewritten, the connection state of the internal circuit is determined, and a plurality of Arbitrates the bus request signal from the device. Therefore, regardless of the number of devices that can become bus masters, it is possible to flexibly cope with changes in the system configuration. In addition, since one arbitration circuit is set to a plurality of circuit configurations and performs only the arithmetic processing necessary for the system configuration, a redundant arithmetic processing does not occur and a small-scale bus arbitration device is realized. it can.

Further, according to the bus arbitration apparatus according to the present invention, in selecting the circuit data in the first aspect, it is detected whether or not the device is connected to the bus. . Therefore, an optimal operation can be performed according to the system configuration.

According to the bus arbitration apparatus of the present invention (claim 3), in claim 1 or 2, the bus request signal from the device and the bus grant signal to the device are processed in the arbitration circuit means. Freely change the correspondence with the signal. Therefore, flexibility can be given to the connection position of the device.

According to the bus arbitration apparatus of the present invention, a bus request signal from a device and a bus grant signal to the device are arbitrated based on the bus master priority information. The correspondence with the signal to be processed in the circuit means is freely changed. Therefore, priority can be given to the bus arbitration.

According to the bus arbitration device of the present invention, the circuit data of the arbitration circuit can be freely changed to other circuit data during the operation of the system. Therefore, it is possible to flexibly respond not only to the system configuration before system startup but also to the change of system configuration after system startup,
Optimal bus arbitration can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a system of a bus arbitration device according to an embodiment of the present invention.

FIG. 2 is a state transition diagram of a round robin system of six devices in the embodiment.

FIG. 3 is a state transition diagram of a round robin system of two devices in the embodiment.

FIG. 4 is a state transition diagram of a priority system of six devices in the embodiment.

FIG. 5 is an explanatory diagram showing a connection state of a signal connection unit in FIG. 1;

FIG. 6 is a state transition diagram of a priority order method of three devices corresponding to FIG. 5;

[Explanation of symbols]

 Reference Signs List 101 Arbitration circuit 102 Circuit data storage unit 103 Circuit data setting unit 104 Device 105 Bus controller 106 Signal connection unit

Claims (5)

[Claims] 1. A bus arbitration device that is connected to one bus and arbitrates bus request signals from a plurality of devices that can be a bus master, and that stores a plurality of types of circuit data as circuit configuration information. Means for determining a connection state of an internal circuit according to the set circuit data, arbitrating bus request signals from the plurality of devices by the determined circuit, and granting a bus grant to the device according to the arbitration result. Rewritable arbitration circuit means for outputting a signal; and circuit data setting means for selecting at least one type of circuit data from the circuit data storage means and setting the selected arbitration circuit means in the arbitration circuit means. Bus arbitration device. 2. The circuit data setting means according to claim 1, wherein said circuit data setting means selects circuit data in accordance with a connection status of a device which can be a bus master to said one bus.
The bus arbitration device according to item 1. 3. An arbitration circuit means for arbitrarily connecting a plurality of bus request signal input ports of the arbitration circuit means with bus request signals output from the plurality of devices, based on bus master information. 3. A bus arbiter according to claim 1, further comprising signal connection means for arbitrarily connecting the output ports of the plurality of bus grant signals and the bus grant signals input to the plurality of devices. apparatus. 4. The bus arbitrating device according to claim 3, wherein said signal connection means determines connection of a priority system based on bus master priority information. 5. The circuit data setting means changes and sets circuit data of the arbitration circuit means to other circuit data even during operation of the device arbitrated by a circuit determined by arbitrary circuit data. The bus arbitration device according to any one of claims 1 to 4, wherein