JPH11103070A - Thin film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To ensure reliability for a long time by improving an insulating layer included in a thin film transistor. SOLUTION: A thin film transistor has a laminated structure including a semiconductor film 5, a gate oxide film 3 formed on the bottom surface of the semiconductor film 5, an etching stopper film 6 formed on the top surface of the semiconductor film 5, and a gate electrode 1 just under the semiconductor film 5 via the gate oxide film 3, and is formed on an insulating substrate 0 at a process temperature under 60 deg.C. The semiconductor film 5 includes an active layer comprising non-single crystalline silicon. The gate oxide film 3 constituting a lower insulating layer comprises SiO2 generated by the dissolution of inorganic silane compounds and is made dense by laser annealing. The etching stopper film 6 constituting an upper insulating layer comprises SiO2 generated by the dissolution of organic saline compounds and has a dense composition. It is possible to make the gate oxide film 3 and the etching stopper film 6 dense at the same time by employing a rapid heating method when impurities implanted into the semiconductor thin film are activated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor having a semiconductor thin film such as polycrystalline silicon formed on an insulating substrate as an active layer. More specifically, the present invention relates to a thin film transistor formed by a low-temperature process (for example, a process maximum temperature is 600 ° C. or lower). More specifically, the present invention relates to a technique for modifying an insulating layer included in a thin film transistor.

[0002]

2. Description of the Related Art Thin film transistors are widely used as switching elements in active matrix type liquid crystal displays. In particular, polycrystalline silicon has been conventionally used as a semiconductor thin film serving as an active layer of a thin film transistor. The polycrystalline silicon thin film transistor can be used not only as a switching element but also as a circuit element, and a peripheral driving circuit can be built on the same substrate together with the switching element. Further, since the polycrystalline silicon thin film transistor can be miniaturized, the occupied area of the switching element in the pixel structure can be reduced, and a high aperture ratio of the pixel can be achieved. By the way, conventionally, a polycrystalline silicon thin film transistor has a process maximum temperature of about 1000 ° C. in a manufacturing process, and quartz glass or the like having excellent heat resistance has been used as an insulating substrate. It has been difficult to use a low melting point glass substrate in a high temperature process. However, in order to reduce the cost of the liquid crystal display, it is essential to use a low melting point glass plate material. Therefore, in recent years, the development of a so-called low-temperature process in which the maximum process temperature is 600 ° C. or lower has been promoted. In particular, the low-temperature process is extremely advantageous in terms of cost when manufacturing a large liquid crystal display.

[0003]

In order to process a thin film transistor at a low temperature, it is generally adopted to form a gate oxide film by a plasma CVD method or a low pressure CVD method instead of the conventional thermal oxidation method. . As the source gas, for example, SiH ₄ which is an inorganic silane compound is used. However, in these conventional methods, 600 ° C.
High quality Si comparable to thermal oxide film by the following low temperature process
It is difficult to form an O ₂ film. For example, the threshold voltage (Vth) of a thin film transistor due to a defect level in the film
And it was difficult to maintain long-term reliability. In addition, SiO 2 formed by a conventional plasma CVD method
_{In the two} films, for example, when an n-channel thin film transistor is in an ON state, hot electrons jump into a gate oxide film in contact with the vicinity of the drain end of the channel or another oxide film facing the gate oxide film via the semiconductor thin film. As a result, negative charges are induced in these oxide films. As a result, the channel region near the drain end is weakly inverted, and the channel resistance is increased. This accumulation of hot electrons causes a serious problem that the on-current of the thin film transistor is reduced and long-term reliability cannot be ensured. As a countermeasure, a method has been adopted in which, for example, a low-concentration impurity region (LDD region) is provided at the drain end to reduce the electric field concentration at the drain end and to suppress the influence of hot carriers such as hot electrons. However, with this measure, since the resistance of the LDD region is high, the problem of reducing the on-current of the thin film transistor cannot be fundamentally solved. In order to ensure long-term reliability of a thin film transistor by a low-temperature process, reforming of a gate oxide film is urgently required. Although the gate oxide film is in contact with the interface on the gate electrode side of the semiconductor thin film forming the thin film transistor, the oxide film is also generally in contact with the interface on the opposite side (back gate side). Since hot carrier accumulation occurs not only in the gate oxide film but also in the oxide film on the back gate side, its modification is necessary.

In recent years, as a means for forming a high-quality SiO ₂ film at a low temperature, a method of decomposing an organic silane compound by high-frequency plasma instead of an inorganic silane compound has attracted attention. However, in this method, impurities of a carbon-based compound which is a decomposition by-product of the organic silane compound adhere to the surface of the formed SiO ₂ . This impurity cannot be completely removed in the cleaning step. Although a dense and high-quality SiO ₂ film can be formed by plasma CVD using an organic silane compound, there is a problem of impurities as described above. When a semiconductor thin film such as silicon is laminated on an SiO ₂ film covered with impurities and then laser annealing is performed, the impurities diffuse into the semiconductor thin film, causing a problem that a large change in characteristics of the thin film transistor occurs. Note that laser annealing is a crystallization technique employed in a low-temperature process, and converts amorphous silicon into polycrystalline silicon by irradiating a semiconductor thin film with laser light.

[0005]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems of the prior art, the present invention eliminates the influence of decomposition by-products of an organic silane compound and secures a highly reliable thin film transistor structure. A first object is to provide a manufacturing method. The following measures were taken to achieve this purpose. That is, the thin film transistor according to the present invention basically includes
A semiconductor thin film including an active layer made of non-single-crystal silicon;
A lower insulating layer formed in contact with the lower surface side of the active layer, an upper insulating film formed in contact with the upper surface side of the active layer, and the semiconductor thin film over the lower insulating layer or the upper insulating layer. And a gate electrode formed on the insulating substrate at a process temperature of 600 ° C. or lower. As a characteristic feature, the lower insulating layer is made of SiO ₂ generated by decomposition of an inorganic silane compound, and the upper insulating layer is made of SiO ₂ generated by decomposition of an organic silane compound.

[0006] Optionally, the lower insulating layer, the lower layer made of SiO ₂ produced by the decomposition of the inorganic silane compound comprises a layer of SiO ₂ produced by the decomposition of the organic silane compound. Preferably, the upper insulating layer is formed by plasma decomposition of an organic silane compound.
It is made of SiO ₂ formed at a temperature of not more than ℃. Further, the semiconductor thin film is crystallized by laser annealing using laser light irradiation, and the lower insulating layer located below the semiconductor thin film is automatically improved in film quality under the influence of laser annealing. In one embodiment, the lower insulating layer is a base oxide film interposed between the insulating substrate and the semiconductor thin film, and the gate electrode is located above the semiconductor thin film via a gate oxide film including an upper insulating layer. It is a top gate structure located. In another embodiment, the upper insulating layer is an etching stopper film located on the semiconductor thin film, and the gate electrode is located below the semiconductor thin film via a gate oxide film made of a lower insulating layer. Structure.

The present invention includes a method for manufacturing a thin film transistor. The thin film transistor has a semiconductor thin film including an active layer made of non-single-crystal silicon, a lower insulating layer formed in contact with the lower surface of the active layer, and an upper insulating layer formed in contact with the upper surface of the active layer. It has a laminated structure including a gate electrode superposed on the semiconductor thin film via the lower insulating layer or the upper insulating layer, and is formed on an insulating substrate at a process temperature of 600 ° C. or lower according to the following steps. First, an inorganic silane compound is decomposed to deposit SiO ₂ on the insulating substrate to form the lower insulating layer. Next, the semiconductor thin film is formed on the lower insulating layer. Subsequently, the semiconductor thin film is crystallized by irradiating a laser beam, and at the same time, the lower insulating layer is modified. Thereafter, the organic silane compound is decomposed to form S
iO ₂ is deposited on the semiconductor thin film to form the upper insulating layer.

According to the present invention, the lower insulating layer uses SiO ₂ generated by decomposition of an inorganic silane compound,
A semiconductor thin film is formed thereon. Since the inorganic silane compound has no by-products other than SiO ₂ by decomposition, the surface of the lower insulating layer is kept clean. Therefore, the interface between the lower insulating layer and the semiconductor thin film is in a good state, and there is no possibility that the reliability is adversely affected. In addition, when the semiconductor thin film is crystallized by laser annealing, the lower insulating layer is also automatically heat-treated, and the quality of the film becomes dense, so that the number of defect levels that can trap hot electrons is greatly reduced. on the other hand,
For the upper insulating layer, SiO ₂ generated by decomposition of an organic silane compound is used. This SiO ₂ inherently has a dense composition, and the interface with the lower semiconductor thin film is in a good state. Decomposition of the organic silane compound generates by-products, which adhere to the surface of the upper insulating layer and do not adversely affect the semiconductor thin film below. As described above, according to the present invention, since the semiconductor thin film is held from above and below by the insulating layer made of SiO ₂ having good film quality, a thin film transistor having stable operation characteristics and reliability can be obtained.

A second object of the present invention is to provide a rapid heating method (RT).
The purpose of A) is to densify the insulating layer and improve the reliability of the thin film transistor. The following measures were taken to achieve this purpose. That is, the invention according to the second object is directed to a method for manufacturing a thin film transistor. The thin film transistor includes a semiconductor thin film including an active layer made of non-single-crystal silicon, a lower insulating layer formed in contact with the lower surface of the active layer, and an upper insulating layer formed in contact with the upper surface of the active layer. And a gate electrode superposed on the semiconductor thin film via the lower insulating layer or the upper insulating layer, and is formed on an insulating substrate at a process temperature of 600 ° C. or less. Such a thin film transistor is manufactured by the following steps according to the present invention. First, a lower deposition step of depositing SiO ₂ on the insulating substrate and forming the lower insulating layer is performed.
Next, a film forming step of forming the semiconductor thin film on the lower insulating layer is performed. Subsequently, an implantation step of selectively implanting impurities into the semiconductor thin film to form a source region and a drain region of the thin film transistor is performed. Furthermore, SiO
₂ is deposited on the semiconductor thin film to form an upper insulating layer. Finally, a rapid heating step of activating the implanted impurities by a rapid heating method and simultaneously densifying the lower insulating layer and the upper insulating layer is performed.

Preferably, the lower deposition step is performed by decomposing an inorganic silane compound, by sputtering or vapor deposition.
The O ₂ is deposited. Also preferably, in the upper deposition step, SiO ₂ is deposited by an inorganic silane compound decomposition method, a sputtering method, or a vapor deposition method. More preferably, the upper deposition step decomposes the organic silane compound to deposit SiO ₂ . The rapid heating step has a process temperature of 500 ° C.
The above is performed.

In the method of manufacturing a thin film transistor,
A rapid heating method is used to activate the impurities implanted in the semiconductor thin film. The rapid heating method is a method of irradiating a semiconductor thin film such as polycrystalline silicon with light having a wavelength in an ultraviolet region for a short time to activate impurities previously implanted in the semiconductor thin film. Since the rapid heating method has excellent heating temperature uniformity, the resistance variation of the active layer can be suppressed,
The productivity is also superior to the conventional activation annealing using laser light. The rapid heating method has the above advantages,
Since the above process temperature is possible, the insulating layer made of SiO ₂ can be densified, which has a great advantage that the hot carrier breakdown voltage can be improved. If the rapid heating method is used in the activation treatment, the insulating layers sandwiching the semiconductor thin film from above and below can be densified at the same time. In order to improve the hot carrier breakdown voltage, SiO ₂ sandwiching the semiconductor thin film from above and below
It is indispensable to densify both.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a schematic sectional view showing a first embodiment of a thin film transistor according to the present invention. As shown in the drawing, the present thin film transistor has a bottom gate type laminated structure and is formed on an insulating substrate 0 made of glass or the like at a process temperature of 600 ° C. or less. On the insulating substrate 0, a gate electrode 1, a gate nitride film 2, a gate oxide film 3, a semiconductor thin film 5, and an etching stopper film 6 are sequentially stacked from below. That is, the present thin film transistor has a lower insulating layer (gate oxide film 3) formed in contact with the semiconductor thin film 5 and its lower surface, and an upper insulating layer (etching stopper film 6) formed in contact with the upper surface of the semiconductor thin film 5. And a gate electrode 1 superposed on the semiconductor thin film 5 via the lower insulating layer. In addition,
In the case of the top gate type, the gate electrode is overlaid on the semiconductor thin film via the upper insulating layer. The semiconductor thin film 5 is divided into a channel region Ch (active layer) located immediately below the etching stopper film 6 and a drain region D and a source region S located on both sides thereof. Further, a low concentration impurity region (L) is provided between the channel region Ch and the drain region D.
DD region) is interposed. Similarly, the channel region Ch
An LDD region is interposed between the semiconductor device and the source region S.
The thin film transistor having such a configuration is sequentially covered with an interlayer insulating film 7 and a passivation film 8. A wiring electrode 9 is formed on the passivation film 8 by patterning, and is connected to the source region S via a contact hole. A flattening layer 10 is coated on the uppermost layer,
The pixel electrode 11 is formed thereon by patterning.
The pixel electrode 11 is connected to the drain region D via a contact hole. As described above, in the present embodiment, the thin film transistor is used for switching driving of the pixel electrode 11. In this connection, it is necessary to suppress the leak current, and a so-called LDD structure is employed. However, the present invention does not necessarily include the LDD region as an essential component, and it is possible to remove the LDD region when forming a thin film transistor in a driver circuit or the like. The upper insulating substrate 20 is joined to the lower insulating substrate 0 via a predetermined gap. The upper insulating substrate 20 is made of glass or the like, and has at least a counter electrode 21 formed on the inner surface thereof. An electro-optical material 22 made of a liquid crystal or the like is held in a gap between the two insulating substrates 0 and 20.

As a feature of the present invention, the gate oxide film 3 serving as the lower insulating layer is made of SiO ₂ generated by decomposition of an inorganic silane compound. On the other hand, the etching stopper film 6 serving as the upper insulating layer is made of SiO ₂ generated by the decomposition of the organic silane compound. As is clear from the figure, the etching stopper film 6 and the gate oxide film 3 are in direct contact with the channel region Ch (active layer) of the semiconductor thin film 5 from above and below. The semiconductor thin film 5 is crystallized by laser annealing using laser light irradiation.
The gate oxide film 3 located below the gate oxide film is affected by the laser annealing, and the film quality is improved. Thereby, the absolute value of the flat band voltage of the gate oxide film 3 can be controlled to 2 V or less. The absolute value of the flat band voltage is SiO ₂
The smaller the absolute value, the denser the film quality and the lower the defect level density.
Originally, laser annealing is a process of irradiating the semiconductor thin film 5 with laser light to crystallize the semiconductor thin film 5. This laser annealing also instantaneously heats the gate oxide film 3 directly in contact with the semiconductor thin film 5 to a temperature of 1000 ° C. or higher. Due to this effect, the surface of the gate oxide film 3 becomes dense, and the absolute value of the flat band voltage becomes 2 V or less. When the oxide film is not densified, the oxide film obtained by decomposition of the inorganic silane compound has an absolute value of the flat band voltage of about 20 V. On the other hand, the etching stopper film 6 serving as an upper insulating layer
Is obtained, for example, by plasma decomposition of an organic silane compound.
The film is formed at a temperature of 50 ° C. or less. According to this method, a dense SiO ₂ film can be originally formed, and the absolute value of the flat band voltage is 2 V or less. That is, the film quality of the etching stopper film 6 is close to that of a conventional thermal oxide film, is high quality and is dense, and can suppress a decrease in long-term reliability due to accumulation of hot carriers.

Next, a method of manufacturing the thin film transistor shown in FIG. 1 will be described in detail with reference to FIG. In this example, a method for manufacturing an n-channel thin film transistor is shown for convenience, but the same applies to a p-channel thin film transistor only by changing the impurity species (dopant species). First, as shown in (a),
Al, Mo, T on insulating substrate 0 made of glass etc.
a, such as a, Ti, Cr, W, or a layered structure of highly doped polycrystalline silicon and said metal, or a layered structure or alloy of said metals, and is patterned into a predetermined shape to form a gate electrode 1; Process.

Next, a gate insulating film is formed on the gate electrode 1 as shown in FIG. In the present embodiment, the gate insulating film is a gate nitride film 2 (SiN _x ) / gate oxide film 3
A (SiO ₂ ) two-layer structure was used. The gate nitride film 2 is made of S
A film was formed by a plasma CVD method (PCVD method) using a mixture of iH ₄ gas and NH ₃ gas as a source gas. The radio frequency (RF) for inducing plasma is 13.56 MHz
, A power of 0.06 W / cm ² , a substrate temperature of 300 to 350 ° C., and a film thickness of 50 to 150 nm. Then, the gate oxide film 3
Was formed by using SiH ₄ , which is an inorganic silane compound, as a source gas, mixing O ₂ , and continuously depositing SiO ₂ on the gate nitride film 2 by a plasma CVD method. As the inorganic silane compound, disilane Si ₂ H ₆ can be used in addition to SiH ₄ , and O ₂ may be mixed with this to form a film. In this embodiment, RF =
The gate oxide film 3 is formed to a thickness of 50 to 100 nm under the conditions of 13.56 MHz, power 0.06 W / cm ² , and substrate temperature of 300 to 350 ° C. At this stage, the gate oxide film 3
The absolute value of the flat band voltage is 2 V or more.

Next, a semiconductor thin film 4 made of amorphous silicon is formed on the gate oxide film 3 to a thickness of 30 to 50 nm. The two-layered gate nitride film 2 and gate oxide film 3 and the amorphous semiconductor thin film 4 can be continuously formed without breaking the vacuum system of the film formation chamber. After forming the amorphous semiconductor thin film 4, 4
Dehydrogenation annealing is performed at 00 ° C. for about 2 hours. here,
The amorphous semiconductor thin film 4 is converted into a polycrystalline semiconductor thin film 5 by irradiating a laser beam. For example, 300 to 440 mJ / c
An excimer laser beam having an energy density of m ² is irradiated. The wavelength of the laser beam at this time is, for example, 308
and the pulse frequency of the excimer laser beam is 2
00 Hz and a pulse duration of 25 ns. As a result of this laser annealing, the gate oxide film 3 in contact with the lower portion of the amorphous semiconductor thin film 4 also instantaneously becomes 1 in the order of tens of ns.
Heated above 000 ° C. Due to this effect, the surface of the gate oxide film 3 becomes dense, and the flat band voltage becomes substantially equal to that of the thermal oxide film. That is, a high quality gate oxide film 3 in which the absolute value of the flat band voltage is controlled to 2 V or less can be obtained. Moreover, at this stage, the gate oxide film 3 in contact with the semiconductor thin film 4 is formed by decomposing the inorganic silane compound, and is not affected by the carbon by-product.

Next, as shown in FIG. 1C, S is deposited on the semiconductor thin film 5 converted into polycrystalline silicon by plasma CVD.
iO ₂ is deposited to a thickness of about 100 nm. TEOS (Si (C ₂ H ₅ ) ₄ , an organic silane compound, is used as a source gas.
O ₄ ), the RF was set to 10 to 30 MHz, the power was set to 0.5 W / cm ² or more, the substrate temperature was set to 300 to 450 ° C., and a film was formed with a thickness of, for example, 100 nm. When forming an oxide film using TEOS, the RF frequency is 13.56 MHz or less, and the RF power is 0.2 W / cm ^2.
It is not preferable to perform the heat treatment at less than less because the withstand voltage of the obtained oxide film is low and the number of defect levels in the film increases. Therefore, RF
The frequency needs to exceed 13.56 MHz, and the RF power needs to be 0.2 W / cm ² or more. Preferably, the frequency is about 27.12 MHz and the power is 0.5 W / cm ^2.
Good degree. TEOS is an organic silane compound.
_May be used instead of TRIES (Si (C ₂ H ₅ ) O ₃ H). Thus, a high-quality upper insulating layer in which the absolute value of the flat band voltage is controlled to 2 V or less can be obtained.
The flat band voltage is an important index indicating the reliability of a device with respect to hot carriers, and the lower the absolute value, the better. When SiO ₂ is formed by decomposition of an organic silane compound, impurities of a carbon-based compound which is a decomposition by-product adhere to the surface. However, this impurity only adheres to the surface and is not included in the interface between the semiconductor thin film and the upper insulating layer. Now, SiO ₂ constituting the upper insulating layer is patterned into a predetermined shape and processed into an etching stopper film 6. In this case, the etching stopper film 6 is patterned so as to be aligned with the gate electrode 1 using a backside exposure technique. This etching stopper film 6 serves to protect the channel region (active layer) immediately below when etching the polycrystalline semiconductor thin film 5 in a later step. The etching stopper film 6 is also affected by the hot carriers, and in the conventional SiO ₂ film, fixed charges are induced in the stopper film 6 during the operation of the thin film transistor. Therefore, in order to improve the reliability, it is necessary to form the etching stopper film 6 using TEOS.

Finally, as shown in FIG. 1D, an impurity (eg, P) is implanted into the semiconductor thin film 5 by ion doping using the etching stopper film 6 as a mask to form an LDD region. Further, after a photoresist is formed by patterning so as to cover the stopper film 6 and the LDD regions on both sides thereof, impurities (for example, P) are ion-doped at a high concentration using the photoresist as a mask to form a source region S and a drain region D.
To form Thereafter, the impurities injected into the semiconductor thin film 5 by laser annealing or thermal annealing are activated. At this stage, the semiconductor thin film 5 is patterned into a predetermined shape by etching. Subsequently, about 200 to 600 n of SiO ₂
m to form an interlayer insulating film 7. The interlayer insulating film 7 may be formed by a plasma CVD method, a normal pressure CVD method,
Either a low pressure CVD method or a sputtering method may be used. However, preferably, the interlayer insulating film 7 is formed by a plasma CVD method using TEOS as a source gas. Because T
This is because EOS-SiO ₂ has excellent step coverage, prevents cracks and the like caused by steps between layers, and reduces interlayer leakage. After the formation of the interlayer insulating film 7, SiN _x is formed to a thickness of about 100 to 400 nm by a plasma CVD method to form a passivation film (cap film) 8. At this stage, heat treatment at 300 to 400 ° C. is performed for 1 to 2 hours in a nitrogen gas, a forming gas, or a vacuum atmosphere to diffuse hydrogen atoms contained in the interlayer insulating film 7 into the semiconductor thin film 5.
Note that the passivation film (cap film) 8 is not always necessary, and annealing may be performed only in the state of the interlayer insulating film 7. Thereafter, a contact hole is opened, and Mo,
After sputtering Al or the like, the wiring pattern 9 is processed by patterning into a predetermined shape. Further, a contact hole is opened after the flattening layer 10 made of an acrylic resin or the like is applied. After a transparent conductive film made of ITO or the like is sputtered on the flattening layer 10, it is patterned into a predetermined shape and processed into the pixel electrode 11.

FIG. 3 is a process chart showing a method of manufacturing a thin film transistor according to a second embodiment of the present invention. Unlike the first embodiment, the present embodiment has a top gate structure. First, as shown in (a), two layers of base films 6a and 6b serving as buffer layers are continuously formed on an insulating substrate 0 by a plasma CVD method. The first base nitride film 6a is made of SiN
_x , using a mixture of SiH ₄ gas and NH ₃ gas as a source gas, RF = 13.56 MHz, power =
0.06 W / cm ² or more, substrate temperature 300 to 350 ° C
Was formed. Thereafter, a base oxide film 6b is subsequently formed. Specifically, a SiH ₄ gas is used as a raw material, an O ₂ gas is mixed with the SiH ₄ gas, and the SiO ₂ gas is mixed by a plasma CVD method.
Was formed. The condition at this time is RF = 13.56 MH
z, power = 0.06 W / cm ² , substrate temperature 300 to 350 ° C. The thickness of the base oxide film 6b made of SiO ₂ is 100 nm to 2000 nm. Note that SiN
_The film thickness of the base nitride film 6a made of _x is, for example, 50 nm. In addition, Si ₂ H ₆ was used instead of SiH ₄ as a source gas.
Can also be used. A semiconductor thin film 4 made of amorphous silicon is formed on the base oxide film 6b to a thickness of about 40 nm. Next, after performing dehydrogenation annealing at 400 ° C. for about 2 hours, the semiconductor thin film 4 is converted from amorphous to polycrystalline by irradiating a laser beam. At this time, under the influence of the laser annealing, the surface of SiO ₂ forming the base oxide film 6b is densified, and the flat band voltage becomes TEOS-SiO 2.
Substantially equal to or less than ₂ .

Next, as shown in FIG. 1B, after the polycrystalline semiconductor thin film 5 is patterned in an island shape, TEOS-SiO ₂ is formed thereon to a thickness of about 50 to 100 nm, and the gate is formed. The oxide film 3 is used. The gate oxide film 3 constituting the upper insulating layer is made of SiO ₂ formed by decomposition of an organic silane compound, has a dense composition, and has a low defect state density. In some cases, impurities of a carbon-based compound, which is a by-product of decomposition of an organic silane gas, adhere to the gate oxide film 3. However, since this impurity does not possibly exist at the interface between the semiconductor thin film 5 and the gate oxide film 3, there is no possibility that the reliability or operation characteristics of the thin film transistor will be adversely affected.

Finally, as shown in (c), the gate oxide film 3
A metal such as Al, Mo, Ta, Ti, Cr, W, etc. is formed thereon, patterned into a predetermined shape, and processed into the gate electrode 1. The gate electrode 1 may be made of a highly-doped polycrystalline silicon and the metal or a laminated structure or alloy of the metals. After that, impurities are implanted by ion doping or the like using the gate electrode 1 as a mask to form a source region S and a drain region D in the semiconductor thin film 5. As a result, the channel region Ch is left directly below the gate electrode 1. Next, an interlayer insulating film 7 of SiO _{2 is} formed to a thickness of about 400 nm so as to cover the gate electrode 1. This interlayer insulating film 7 is made of TE
It is desirable to use OS-SiO ₂ for the same reason as in the first embodiment. After the formation of the interlayer insulating film 7, S
iN _x is deposited to a thickness of about 100 to 400 nm by a plasma CVD method to form a passivation film (cap film) 8. At this stage, a nitrogen gas, a forming gas, or 300
Annealing is performed at a temperature of about 400 ° C. for about 1 to 2 hours to diffuse hydrogen contained in the interlayer insulating film 7 into the semiconductor thin film 5. Thereafter, a contact hole is opened. Further, Mo, Al, or the like is formed on the passivation film 8 by sputtering, and then patterned into a predetermined shape to process the wiring electrode 9. Further, after applying a flattening layer 10 made of an acrylic resin or the like, a contact hole is opened in this. A transparent conductive film made of ITO or the like is sputtered on the flattening layer 10, patterned into a predetermined shape, and processed into the pixel electrode 11. As in the first embodiment, in the second embodiment,
The semiconductor thin film 5 is made of non-single-crystal silicon (polycrystalline silicon). The underlying oxide film 6b as a lower insulating layer uses SiO ₂ generated by decomposition of an inorganic silane compound, and the gate oxide film 3 as an upper insulating layer uses SiO ₂ generated by decomposition of an organic silane compound. I have.

FIG. 4 is a schematic partial sectional view showing a third embodiment of the thin film transistor according to the present invention. Basically, it has a configuration similar to that of the first embodiment shown in FIGS. 1 and 2, and corresponding parts are denoted by corresponding reference numerals to facilitate understanding. FIG. 4 corresponds to step (c) of FIG. 2 and shows a semi-finished product state of the thin film transistor. As shown in the figure, a lower insulating layer is provided under a gate oxide film 3 made of SiO ₂ formed by decomposition of an inorganic silane compound, and another gate oxide film made of SiO ₂ formed by decomposition of an organic silane compound. 3x. The entire gate insulating film has a stacked structure of a gate nitride film 2, a gate oxide film 3x, and a gate oxide film 3 which are sequentially stacked from the bottom. The lowermost gate nitride film 2 is the first
The film is formed by the same method as in the embodiment. The middle gate oxide film 3x is formed to a thickness of 30 to 80 nm by a plasma CVD method using TEOS of an organic silane gas. Subsequently, the raw material gas was switched to inorganic silane gas, and was
An upper gate oxide film 3 is formed with a thickness of 0 nm. Further, the semiconductor thin film 4 made of amorphous silicon is continuously
The film is formed to a thickness of 50 to 50 nm. With such a laminated structure, the gate insulating film can be made denser and the reliability can be improved. At the same time, the gate oxide film 3 directly in contact with the lower portion of the active layer of the semiconductor thin film 4 is made of inorganic silane gas. Since the decomposed SiO ₂ is used, the problem of carbon-based impurities can be avoided. Further, the gate oxide film 3x consisting TEOS-SiO ₂ of the middle layer with has excellent step coverage with respect to the gate electrode 1, the withstand voltage of the entire gate insulating film because it has a dense composition is improved.

FIG. 5 shows an example of an active matrix type liquid crystal display device using the thin film transistors according to the first, second or third embodiment. As illustrated, the display device has a panel structure including a pair of insulating substrates 101 and 102 and an electro-optical material 103 held between the pair of insulating substrates 101 and 102. As the electro-optic material 103, a liquid crystal material is widely used. On the lower insulating substrate 101, a pixel array section 104 and a drive circuit section are integrally formed. The drive circuit section is divided into a vertical drive circuit 105 and a horizontal drive circuit 106. Further, a terminal portion 107 for external connection is formed at an upper end of a peripheral portion of the insulating substrate 101. The terminal portion 107 is connected to a vertical drive circuit 105 and a horizontal drive circuit 106 via a wiring 108. Pixel array unit 104
, A row-shaped gate wiring 109 and a column-shaped signal wiring 110 are formed. A pixel electrode 111 and a thin film transistor 112 for driving the pixel electrode 111 are formed at the intersection of the two wires. The gate electrode of the thin film transistor 112 is connected to the corresponding gate wiring 109, the drain region is connected to the corresponding pixel electrode 111, and the source region is connected to the corresponding signal wiring 110. The gate wiring 109 is connected to the vertical driving circuit 105, while the signal wiring 110 is connected to the horizontal driving circuit 106. The thin film transistor 112 for switching and driving the pixel electrode 111 and the thin film transistors included in the vertical drive circuit 105 and the horizontal drive circuit 106 are formed according to the present invention. That is, the semiconductor thin film is made of non-single-crystal silicon, and the absolute value of the flat band voltage of each of the insulating layers holding these from above and below is controlled to 2 V or less. Since the thin film transistor is hardly affected by hot electrons, the reliability can be maintained without adopting the LDD structure. Therefore, when a thin film transistor is used for the vertical drive circuit 105 and the horizontal drive circuit 106, it is not necessary to employ an LDD structure, and a sufficient on-current can be secured. The flat band voltage is measured with a MIS structure in which SiO ₂ is interposed between an aluminum electrode and a silicon substrate (n-type). When SiO ₂ is sandwiched between an aluminum electrode and a silicon substrate from both sides, a potential difference occurs depending on the film quality of SiO ₂ . The applied voltage required to cancel this potential difference is called a flat band voltage. Therefore, the flat band voltage is an index indicating the quality (defect density) of the film of SiO ₂ , and further indicates the denseness of the film. It is said that the closer the absolute value of the flat band voltage is to 0, the better the film quality. Incidentally, a normal plasma CV using SiH ₄
The absolute value of the flat band voltage of the SiO ₂ film formed by the method D may exceed 2 V and may be up to about 20 V.

FIG. 6 is a graph showing VGS / IDS characteristics of a thin film transistor prepared as a comparative example.
(A) shows the characteristics of an n-channel thin film transistor;
(B) shows the characteristics of the p-channel thin film transistor. In each graph, the horizontal axis represents the gate-source voltage VGS, and the vertical axis represents the drain-source current IDS. The drain / source voltage VDS is set to 5 V and 10 V as a parameter. This comparative example has a bottom gate structure, in which an active layer of a semiconductor thin film is held by TEOS-SiO ₂ from above and below. As is clear from the graph, the threshold voltage of the n-channel thin film transistor is largely shifted in the enhancement direction, and the threshold voltage of the p-channel thin film transistor is largely shifted in the depletion direction.

FIG. 7 shows the VGS / IDS characteristics of the thin film transistor according to the present invention. (A)
Indicates the characteristics of an n-channel thin film transistor, and (b)
Represents the characteristics of the p-channel thin film transistor. Unlike the comparative example, the lower insulating layer is TEOS-SiO ₂
Instead of using SiO ₂ generated by decomposition of SiH ₄ , and densified by laser annealing. As is clear from the graph, no remarkable shift of the threshold voltage is observed. This is because the lower insulating layer in contact with the lower portion of the active layer was formed by decomposition of an inorganic silane gas, so that there was no impurity contamination on the SiO ₂ surface which would be a problem with the organic silane gas. On top of the active layer, high quality SiO decomposed organic silane gas
_{Since 2} is used, the withstand voltage against hot carriers is greatly improved, and high reliability can be secured.

FIG. 8 is a process chart showing a fourth embodiment of the method for manufacturing a thin film transistor according to the present invention. In this embodiment, a method of manufacturing an n-channel thin film transistor is described for convenience, but the same applies to a p-channel thin film transistor only by changing the impurity species (dopant species). Here, a method for manufacturing a thin film transistor having a bottom gate structure is described. First, as shown in (a), Al, Ta, Mo, W, Cr, Cu or an alloy thereof is formed on an insulating substrate 0 made of glass or the like to a thickness of 100 to 200 nm, and is patterned to form a gate electrode 1. Process into

Next, a gate insulating film is formed on the gate electrode 1 as shown in FIG. In the present embodiment, the gate insulating film is a gate nitride film 2 (SiN _x ) / gate oxide film 3
A (SiO ₂ ) two-layer structure was used. The gate nitride film 2 is made of S
A film was formed by a plasma CVD method (PCVD method) using a mixture of iH ₄ gas and NH ₃ gas as a source gas. It should be noted that, instead of plasma CVD, normal pressure CVD or reduced pressure C
VD may be used. In the present embodiment, the gate nitride film 2
Was deposited to a thickness of 50 nm. Subsequent to the formation of the gate nitride film 2, a gate oxide film 3 is formed with a thickness of about 200 nm. Further, a semiconductor thin film 4 made of amorphous silicon was continuously formed on the gate oxide film 3 to a thickness of about 30 to 80 nm. The two-layered gate insulating film and the amorphous semiconductor thin film 4 were continuously formed without breaking the vacuum system of the film forming chamber. When the plasma CVD method is used for the above film formation, heat treatment is performed in a nitrogen atmosphere at a temperature of 400 to 450 ° C. for about 1 hour to release hydrogen contained in the amorphous semiconductor thin film 4. A so-called dehydrogenation anneal is performed. In the above-described steps, the gate oxide film 3 constituting the lower insulating layer is formed by decomposing an inorganic silane gas (such as SiH ₄ or Si ₂ H ₆ ). Instead, SiO ₂ may be deposited by a sputtering method or an evaporation method. However, when an organic silane gas is used for forming SiO ₂ , impurities remain on the surface layer of the film, which may cause a shift in transistor characteristics, which is not preferable.

Here, for the purpose of controlling Vth of the thin film transistor, Vth ion implantation is performed as necessary. In this example, the dose of B + is 1 × 10
Ions are implanted at ¹² to 6 × 10 ¹² / cm ² approximately. In this Vth ion implantation, a line beam of ions shaped to a width of 620 nm was used. Next, the amorphous semiconductor thin film 4 is crystallized by irradiation with a laser beam 50. An excimer laser beam can be used as the laser beam 50. So-called laser annealing is an effective means for crystallizing a semiconductor thin film at a process temperature of 600 ° C. or lower. In the present embodiment, crystallization is performed by irradiating the amorphous semiconductor thin film 4 with a laser beam 50 excited in a pulse shape and shaped into a rectangular shape or a band shape. In some cases, a solid phase growth method may be used instead of laser annealing. After that, the semiconductor thin film is patterned according to the element region of each thin film transistor.

As shown in FIG. 1C, the polycrystalline semiconductor thin film 5 crystallized in the previous step is formed on the polycrystalline semiconductor thin film 5 by, for example, plasma CVD.
iO ₂ is formed with a thickness of about 100 nm to 300 nm. In this example, normal silane gas SH ₄ and oxygen gas were plasma-decomposed to deposit SiO ₂ . More preferably,
For forming SiO ₂ , TEOS which is an organic silane gas can be used. SiO ₂ can be formed by decomposition of TEOS under the conditions of RF of 10 to 30 MHz and substrate temperature of 300 to 450 ° C. TEOS-SiO
_{The two} films have a dense composition. By combining the TEOS technique and the RTA technique described later, an extremely dense SiO ₂ film can be formed, so that the hot carrier breakdown voltage can be remarkably improved.

The thus formed SiO ₂ is patterned into a predetermined shape and processed into an etching stopper film 6. In this case, the etching stopper film 6 is patterned so as to be aligned with the gate electrode 1 using a backside exposure technique. The portion of the polycrystalline semiconductor thin film 5 located immediately below the etching stopper film 6 is protected as a channel region Ch. As described above, Vt is previously stored in the channel region Ch.
B + ions are implanted at a relatively low dose by the h ion implantation. Subsequently, impurities (for example, P + ions) are implanted into the semiconductor thin film 5 by ion doping using the etching stopper film 6 as a mask.
A DD region is formed. The dose at this time is, for example, 6 ×
It is 10 ^{12 to} 5 × 10 ¹³ / cm ² . Further, after a photoresist is formed by patterning so as to cover the stopper film 6 and the LDD regions on both sides thereof, impurities (for example, P + ions) are implanted at a high concentration using the photoresist as a mask to form a source region S and a drain region D. . For impurity implantation, for example, ion doping (ion shower) can be used. This is to implant impurities by electric field acceleration without applying mass separation. In this embodiment, 1 ×
Impurities were implanted at a dose of about 10 ¹⁵ / cm ² to form a source region S and a drain region D. Although not shown, in the case of forming a p-channel thin film transistor, the impurity is switched from P + ions to B + ions after covering the region of the n-channel thin film transistor with a photoresist, and the dose is about 1 × 10 ¹⁵ / cm ^2. Ion doping. Here, the impurities may be implanted using a mass separation type ion implantation apparatus.

Thereafter, the impurities implanted into polycrystalline semiconductor thin film 5 are activated by RTA 60. Conventionally, laser activation annealing using an excimer laser has been performed for the activation process. In the present embodiment, the impurity is activated by using a rapid heating method (RTA) instead.
The RTA 60 activates impurities by irradiating the polycrystalline semiconductor thin film 5 with light having a wavelength in the ultraviolet region for a short time. Since the RTA has excellent heating temperature uniformity, there is an advantage that variation in electric resistance in the LDD region is suppressed and throughput is faster than laser activation annealing using an excimer laser. In the laser activation annealing, the glass substrate is irradiated while scanning the pulse of the excimer laser, whereas in the RTA, the ultraviolet light emitted from the arc lamp is instantaneously irradiated on the glass substrate for a very short time (for example, about 1 second). The polycrystalline semiconductor thin film 5 is rapidly heated.

In addition to the above advantages, the RTA has a great advantage that a process temperature of 500 ° C. or more can be performed, so that the insulating layer made of SiO ₂ can be densified, thereby improving the hot carrier breakdown voltage. If RTA is used in the activation process of the impurities implanted in the semiconductor thin film, the etching stopper film 6 and the gate oxide film 3 sandwiching the polycrystalline semiconductor thin film 5 from above and below can be simultaneously densified. In order to improve the hot carrier breakdown voltage, it is indispensable to simultaneously densify the SiO ₂ films sandwiching the polycrystalline semiconductor thin film 5 from above and below. By RTA activation process, Si
Due to the densification of O _2, the etch rate of the SiO ₂ film was reduced by 30 to 50% as compared with the case of excimer laser activation. The etch rate is an index indicating the film quality, and the lower the value, the denser the film quality.

[0033] As shown in the last (d), the the SiO ₂ about 2
The interlayer insulating film 7 is formed with a thickness of 00 nm. After the formation of the interlayer insulating film 7, SiN _x is applied for about 20
A film having a thickness of 0 to 400 nm is formed as a passivation film (cap film) 8. At this stage, a heat treatment of about 350 ° C. is performed in a nitrogen gas, a forming gas, or a vacuum atmosphere.
The hydrogen atoms contained in the interlayer insulating film 7 are diffused into the semiconductor thin film 5 for a while. Thereafter, a contact hole is opened, and Mo, Al, or the like is sputtered with a thickness of 200 to 400 nm, and then patterned into a predetermined shape to process the wiring electrode 9. Further, after a flattening layer 10 made of an acrylic resin or the like is applied with a thickness of about 1 μm, a contact hole is opened. After a transparent conductive film made of ITO, IXO, or the like is sputtered on the flattening layer 10, it is patterned into a predetermined shape and processed into the pixel electrode 11.

FIG. 9 shows the RT used in the rapid heating method described above.
A device is shown. RTA has a wavelength of 240 to 400
This is a technology that enables high-temperature heat treatment (500 to 700 ° C.) without damaging the substrate itself by irradiating ultraviolet light of nm instantaneously (about 1 second) to the insulating substrate 0 made of glass or the like. As shown in the figure, the insulating substrate 0 is preheated gradually (gradual heating) in zones 1 to 3 in which infrared heaters 71 to 73, such as infrared lamps, are arranged.
Is done. In this preheating, the insulating substrate 0 is, for example, 400 ° C.
Heated to a degree. This insulating substrate 0 is 10 to 25 m
The sheet is conveyed at a speed of about m / sec, and sent to an RTA unit sandwiched between Xe arc lamps 81 at the top and bottom. Each arc lamp 81 is covered with a reflector 82,
A radiation thermometer 83 is provided in the vicinity thereof. The semiconductor thin film formed on the insulating substrate 0 made of glass or the like absorbs ultraviolet light emitted from the arc lamp 81 and is heated to 500 to 700 ° C. in about one second. After passing through the RTA unit, the insulating substrate 0 is transported to the cooling zone 4 where the infrared heater 74 is also arranged, where it is cooled. The process temperature is measured by a radiation thermometer 83 disposed immediately before and immediately after the RTA unit. The process temperature of RTA is R
It is determined by three parameters: the output (power) of the Xe arc lamp 81 in the TA unit, the power of the infrared heaters 71 to 73 arranged in the pre-heating zone, and the transfer speed of the insulating substrate 0. The optimum conditions for the RTA vary depending on the material of the glass material used, the thickness of the glass, the size of the substrate, and the like. If the optimum conditions are not satisfied, the temperature gradient in the insulating substrate 0 becomes large, and the insulating substrate 0 may be thermally contracted. In this example, the activation process using RTA for the experiment
The temperature was set to four conditions of 530, 590, 620 and 680 ° C. These temperatures are measured by the radiation thermometer 83 arranged near the RTA unit.

FIG. 10 is a schematic graph showing a temperature profile of the RTA apparatus shown in FIG. As shown in the drawing, the substrate is gradually heated to about 300 ° C. in zone 1, gradually heated to about 350 ° C. in zone 2, and heated to 400 ° C. to 450 ° C. in zone 3 located immediately before the RTA unit. In some cases, zone 1 and zone 2 may be configured as one stage. After passing through the zone 3, the insulating substrate 0 is instantaneously heated to 550 ° C. to 600 ° C. by the RTA unit. Thereafter, the process proceeds to zone 4 where cooling is performed.

According to the present invention, the hot carrier withstand voltage of the thin film transistor is greatly improved, as shown in FIG. In order to explain the graph of FIG. 11, first, a method of measuring the hot carrier breakdown voltage will be described. Hot carriers are significantly generated in a subthreshold region of the thin film transistor. The thin film transistor used for the measurement has a gate width of 20 μm and a gate length of 7 μm. In this case, the gate voltage Vgs is 0
Under driving conditions of about V to 8 V and a drain voltage Vds of about 15 V, hot carriers are easily generated. In the case where deterioration due to hot carriers has occurred, when the on-current is measured with the source / drain direction reversed from that at the time of stress application, a decrease in the on-current is observed compared to before the inversion. Therefore, first, Vds is fixed at 15 V, and Vgs = 15
V is applied for 5 seconds, after which the source / drain direction is reversed and the on-current is measured. Subsequently, with Vds = 15 V fixed, Vgs is reduced to 10 V for the same sample, and a similar on-current measurement is performed after applying a stress for 5 seconds. Hereinafter, with the same sample fixed at Vds = 15 V, Vgs was applied to the condition of 7.5 V, 5 V close to the condition where hot carriers easily occur, and a stress was applied to the source / source.
The on-current is measured with the drain direction reversed. FIG.
Indicates the hot carrier deterioration of the n-channel thin film transistor obtained by such a measurement. The vertical axis represents the on-current value after inversion when the on-current before source / drain inversion is set to 1. The closer this value is to 1, the higher the hot carrier breakdown voltage and the higher the reliability. As is clear from FIG. 11, in the case of the conventional laser-activated thin film transistor indicated by Ref, deterioration has already started even under the condition of Vgs = 15 V where the hot carrier stress is weak. On the other hand, in the thin film transistor processed according to the present invention, the temperature of RTA is 530 ° C.,
It can be seen that the hot carrier withstand voltage is improved as compared with Ref, and the hot carrier withstand voltage dramatically increases as the RTA temperature increases. From the graph of FIG. 11, the RTA temperature is 50
It is also understood that 0 ° C. or higher is necessary and 590 ° C. or higher is desirable.

FIG. 12 is a process chart showing a fifth embodiment of the method for manufacturing a thin film transistor according to the present invention. Unlike the fourth embodiment, this embodiment forms a thin film transistor having a top gate structure. First, as shown in (a),
On an insulating substrate 0, a two-layer base film 6a serving as a buffer layer,
6b is continuously formed by a plasma CVD method. The first underlayer 6a is made of SiN _x and has a thickness of 100 to 200 nm. The second base film 6b is made of SiO ₂
And the film thickness is also 100 nm to 200 nm.
It is. Here, similarly to the fourth embodiment, the SiO ₂ film of the buffer layer is formed of an inorganic silane gas (SiH ₄ , Si ₂ H _6).
, Etc.) to form a film. Or,
SiO ₂ may be deposited by a sputtering method or an evaporation method.
A semiconductor thin film 4 made of amorphous silicon is formed on the base film 6b made of SiO ₂ by plasma CVD or LPCVD to a thickness of about 30 to 80 nm.
When the plasma CVD method is used to form the semiconductor thin film 4 made of amorphous silicon, annealing is performed at 400 ° C. to 450 ° C. for about 1 hour in a nitrogen atmosphere in order to desorb hydrogen in the film. . Then, the amorphous silicon is crystallized by irradiation with a laser beam 50 to be converted into polycrystalline silicon.

Subsequently, the semiconductor thin film 5 converted into polycrystalline silicon is patterned in an island shape as shown in FIG. On top of this, SiO 2 is formed by plasma CVD, normal pressure CVD, low pressure CVD, ECR-CVD, sputtering, etc.
₂ is grown to 50 to 400 nm to form a gate insulating film 3. Preferably, the gate insulating film 3 is made of SiO ₂ formed by a plasma CVD method using TEOS gas. If necessary, Vth ion implantation is performed as described above, and B + ions are implanted into the semiconductor thin film 5 at a dose of, for example, about 0.5 × 10 ^{12 to} 4 × 10 ¹² / cm ² . The acceleration voltage in this case is about 80 KeV. This Vth ion implantation may be performed before the gate insulating film 3 is formed. Vth
In the ion implantation, a line beam shaped to a width of 620 mm was used. Next, on the gate insulating film 3, Al, Ti, Mo, W, Ta, doped polycrystalline silicon, or the like, or an alloy thereof is 200 to 800 nm.
The gate electrode 1 is formed by patterning into a predetermined shape. Next, P + ions are implanted into the semiconductor thin film 5 by an ion implantation method using mass separation to provide an LDD region. This ion implantation is performed on the entire surface of the insulating substrate 0 using the gate electrode 1 as a mask. The dose is 6 × 10 ¹²
To 5 × 10 ¹³ / cm ² . Note that the channel region Ch located immediately below the gate electrode 1 is protected, and V
B + implanted in advance by th ion implantation
The ions are kept as they are. After ion implantation into the LDD region, a resist pattern is formed so as to cover the gate electrode 1 and the periphery thereof, and P + ions are implanted at a high concentration by a mass non-separable ion shower doping method to form a source region S and a drain region D. To form The dose in this case is, for example, about 1 × 10 ¹⁵ / cm ² . A 20% PH ₃ gas diluted with hydrogen was used as a doping gas. CM
In the case of forming an OS circuit, a resist pattern for a p-channel thin film transistor is formed, and then a doping gas is applied for 5 minutes.
% To 20% B ₂ H ₆ / H ₂ gas system, and ion implantation may be performed at a dose of about 1 × 10 ^{15 to} 3 × 10 ¹⁵ / cm ² . Note that the source region S and the drain region D
May be formed using a mass separation type ion implantation apparatus.
Thereafter, the activation process of the dopant injected into the semiconductor thin film 5 is performed. This activation process is similar to the fourth embodiment,
By using the RTA 60, the base film 6b and the gate oxide film 3 constituting the buffer layer can be densified simultaneously. That is,
S sandwiching the semiconductor thin film 5 made of polycrystalline silicon from above and below
The iO ₂ film can be densified at the same time.

Finally, as shown in (c), an interlayer insulating film 7 made of PSG or the like is formed so as to cover the gate electrode 1. After the formation of the interlayer insulating film 7, SiN _x is plasma C
A passivation film (cap film) 8 is deposited by VD to a thickness of about 200 to 400 nm. At this stage, 35
Anneal at a temperature of 0 ° C. for about 1 hour to diffuse hydrogen contained in the interlayer insulating film 7 into the semiconductor thin film 5. Thereafter, a contact hole is opened. Further, Al-Si or the like is formed on the passivation film 8 by sputtering, and then patterned into a predetermined shape to process the wiring electrode 9. Further, a flattening layer 10 made of an acrylic resin or the like is applied with a thickness of about 1 μm, and a contact hole is opened in this. A transparent conductive film made of ITO, IXO, or the like is sputtered on the flattening layer 10, patterned into a predetermined shape, and processed into the pixel electrode 11.

[0040]

As described above, according to the first aspect of the present invention, in the thin film transistor, since the insulating layer made of high quality SiO ₂ is in contact with the active layer from above and below, the adverse effect of hot carriers is suppressed. Thus, a highly reliable thin film transistor can be obtained without using a means such as an LDD structure. That is, the reliability can be improved without lowering the on-current of the thin film transistor, and the thin film transistor can be applied to a peripheral circuit of a liquid crystal display that requires a complicated integrated circuit configuration. This can greatly contribute to the realization of a large-scale system formed on an insulating substrate.

According to the second aspect of the present invention, the lower insulating layer and the upper insulating layer are simultaneously densified by activating the impurities implanted in the semiconductor thin film by the rapid heating method. The densification of the upper and lower insulating layers improves the hot carrier breakdown voltage, and can greatly improve reliability. This allows
The LDD region of the n-channel thin film transistor used in the peripheral circuit can be omitted or shortened, and the on-current of the thin film transistor can be increased. Therefore, it greatly contributes to performance improvement such as speeding up of the peripheral drive circuit.

[Brief description of the drawings]

FIG. 1 is a partial sectional view showing a first embodiment of a thin film transistor according to the present invention.

FIG. 2 is a process chart showing a method for manufacturing a thin film transistor according to the first embodiment.

FIG. 3 is a process chart showing a method for manufacturing a thin film transistor according to a second embodiment of the present invention.

FIG. 4 is a partial sectional view showing a third embodiment of the thin film transistor according to the present invention.

FIG. 5 is a perspective view showing an example of an active matrix type liquid crystal display device which is an application example of the present invention.

FIG. 6 shows a gate voltage /
4 is a graph showing drain current characteristics.

FIG. 7 shows the gate voltage / of the thin film transistor according to the present invention.
4 is a graph showing drain current characteristics.

FIG. 8 is a process chart showing a fourth embodiment of the method for manufacturing a thin film transistor according to the present invention.

FIG. 9 is a conceptual diagram showing a rapid heating device used for carrying out the present invention.

FIG. 10 is a graph showing a temperature profile of the rapid heating device shown in FIG.

FIG. 11 is a graph showing a hot carrier breakdown voltage of a thin film transistor manufactured according to the present invention.

FIG. 12 is a process chart showing a fifth embodiment of the method for manufacturing a thin film transistor according to the present invention.

[Explanation of symbols]

0: insulating substrate, 1: gate electrode, 2: gate nitride film, 3: gate oxide film, 5: semiconductor thin film, 6: etching stopper film, 7: interlayer Insulating film, 8 ... passivation film, 9 ... wiring electrode,
10 ... flattening layer, 11 ... pixel electrode, 20 ...
Insulating substrate, 21: counter electrode, 22: electro-optical material

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 29/78 627G 627A

Claims (13)

[Claims] 1. A semiconductor thin film including an active layer made of non-single-crystal silicon, a lower insulating layer formed in contact with a lower surface side of the active layer, and an upper insulating layer formed in contact with an upper surface side of the active layer. A thin film transistor formed on an insulating substrate at a process temperature of 600 ° C. or lower, having a stacked structure including a layer and a gate electrode superposed on the semiconductor thin film via the lower insulating layer or the upper insulating layer, The thin film transistor according to claim 1, wherein the lower insulating layer is made of SiO ₂ generated by decomposing an inorganic silane compound, and the upper insulating layer is made of SiO ₂ generated by decomposing an organic silane compound. 2. The method according to claim 1, wherein the lower insulating layer is provided under a layer made of SiO ₂ generated by decomposition of the inorganic silane compound.
_2. The thin film transistor according to claim 1, comprising a layer of SiO ₂ formed by decomposition of an organic silane compound. 3. The thin film transistor according to claim 1, wherein the upper insulating layer is made of SiO ₂ formed at a temperature of 450 ° C. or less by plasma decomposition of an organic silane compound. 4. The semiconductor thin film is crystallized by laser annealing using laser light irradiation, and the lower insulating layer located below the semiconductor thin film is affected by the laser annealing to improve the film quality. The thin film transistor according to claim 1, wherein: 5. The lower insulating layer is a base oxide film interposed between the insulating substrate and the semiconductor thin film, and the gate electrode is located above the semiconductor thin film via a gate oxide film formed of an upper insulating layer. 2. The thin film transistor according to claim 1, wherein the thin film transistor has a top gate structure. 6. The bottom gate structure wherein said upper insulating layer is an etching stopper film located on said semiconductor thin film and said gate electrode is located below said semiconductor thin film via a gate oxide film comprising a lower insulating layer. The thin film transistor according to claim 1, wherein 7. A pair of insulating substrates joined to each other via a predetermined gap and an electro-optic material held in the gap, and one of the insulating substrates is formed with a pixel electrode and a thin film transistor for driving the pixel electrode. A display device in which a counter electrode is formed on the other insulating substrate, wherein the thin film transistor is formed in contact with a semiconductor thin film including an active layer made of non-single-crystal silicon and a lower surface side of the active layer. It has a laminated structure including a lower insulating layer, an upper insulating layer formed in contact with the upper surface side of the active layer, and a gate electrode stacked on the semiconductor thin film via the lower insulating layer or the upper insulating layer. 600 ° C. is formed on an insulating substrate in the following process temperature, the lower insulating layer is made of SiO ₂ produced by the decomposition of the inorganic silane compound, the upper insulating layer raw by the decomposition of the organic silane compound Display device characterized by comprising a SiO ₂ was. 8. A semiconductor thin film including an active layer made of non-single-crystal silicon, a lower insulating layer formed in contact with a lower surface of the active layer, and an upper insulating layer formed in contact with an upper surface of the active layer. A thin film transistor having a layered structure including a layer and a gate electrode superposed on the semiconductor thin film via the lower insulating layer or the upper insulating layer and formed on an insulating substrate at a process temperature of 600 ° C. or lower. A step of decomposing an inorganic silane compound and depositing SiO ₂ on the insulating substrate to form the lower insulating layer; a step of forming the semiconductor thin film over the lower insulating layer; Irradiating light to crystallize the semiconductor thin film and simultaneously modify the lower insulating layer; and decomposing an organic silane compound and depositing SiO ₂ on the semiconductor thin film to form the upper insulating layer. And characterized by including A method of manufacturing a thin film transistor. 9. A semiconductor thin film including an active layer made of non-single-crystal silicon, a lower insulating layer formed in contact with a lower surface of the active layer, and an upper insulating layer formed in contact with an upper surface of the active layer. A thin film transistor having a layered structure including a layer and a gate electrode superposed on the semiconductor thin film via the lower insulating layer or the upper insulating layer and formed on an insulating substrate at a process temperature of 600 ° C. or lower. A lower deposition step of depositing SiO ₂ on the insulating substrate to form the lower insulating layer; a film forming step of forming the semiconductor thin film overlying the lower insulating layer; Implanting step of forming a source region and a drain region of a thin film transistor by selectively implanting SiO ₂ , an upper depositing step of depositing SiO ₂ on the semiconductor thin film to form the upper insulating layer, and rapidly heating the implanted impurities. To the law Ri rapid heating step and a method of manufacturing the thin film transistor and performing simultaneously densifying the said lower insulating layer and the upper insulating layer with activated. 10. The method according to claim 9, wherein in the lower deposition step, SiO ₂ is deposited by a decomposition method, a sputtering method, or a vapor deposition method of an inorganic silane compound. 11. The method for manufacturing a thin film transistor according to claim 10, wherein said upper deposition step also deposits SiO ₂ by a method of decomposing an inorganic silane compound, a sputtering method or a vapor deposition method. 12. The method according to claim 10, wherein in the upper deposition step, SiO ₂ is deposited by decomposing an organic silane compound. 13. The process according to claim 13, wherein said rapid heating step has a process temperature of 5.
The method according to claim 9, wherein the temperature is not lower than 00 ° C. 10.