JPH11102591A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent memory data from being outputted wrongly by detecting deterioration of a nonvolatile memory transistor from a state of a floating voltage, storing an address and a bit number to a second memory device, and forming and outputting data corresponding to a write state at a logic circuit to read the data. SOLUTION: A sense amplifier is set inside a data read means 3. When a threshold voltage at the write time is lower than a predetermined value, it is judged as a first abnormality. When a threshold voltage at the read time is higher than a predetermined value, it is judged as a second abnormality. At the occurrence of such abnormality, a control circuit 4 stores an address and a bit number to a second memory device 5. When an address of a memory matrix 1 of a nonvolatile memory transistor required to read stored data agrees with the address stored in the second memory device 5, the control circuit 4 outputs data corresponding to a high threshold value in the case of the first abnormality, and data corresponding to a low threshold value in the case of the second abnormality to the read means 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a semiconductor memory device.

[0002]

2. Description of the Related Art A conventional semiconductor memory device is, for example, one shown in FIG. 9 (Japanese Patent Laid-Open No. Hei 3-238697).
There is. Hereinafter, the structure and operation of the conventional example will be described with reference to FIG. The conventional example includes a CPU 101, a memory matrix 102, a timer 103, and a writing circuit 104 including a control circuit. The CPU 101, the memory matrix 102, the timer 103, the writing circuit 1
04 is connected, and the writing circuit 104 is further connected to the memory matrix 102 and the timer 103. The nonvolatile memory transistors forming each bit of the memory matrix 102 are a flash memory,
It is composed of a PROM such as an EPROM or EPROM.
Here, a non-volatile memory transistor generally used for a PROM has a floating gate surrounded by an insulating film. However, in a PROM, as shown in FIG. 10, a high threshold voltage state by injecting an electron charge into a floating gate is used to write data,
The low threshold voltage state by extracting the electron charge is defined as data erasure. However, it is known that it is difficult to guarantee that stored data is kept stable in the PROM due to the following three problems. First, when the use environment temperature is high, for example, in the case of an automobile, the charge in the floating gate is easily lost, that is, the so-called retention characteristic is deteriorated. Second, there is a disturbance caused by applying a voltage to a bit line or a word line when writing or erasing data in another bit. Third, there is a soft write in which electrons are injected into the floating gate when reading the data of the bit. Next, the operation of this conventional example will be described. The CPU 1 operates according to a program stored in the memory matrix 102.
01 sends a data rewrite signal to the timer 103 and the write circuit 104. Then, the timer 103 sends the time necessary for rewriting the data of each bit to the writing circuit 104, and the writing circuit 104 rewrites, ie, refreshes, the data of each bit of the memory matrix 102 in order. That is, the data is refreshed before the data of each bit of the memory matrix disappears, thereby preventing data destruction.

[0003]

However, such a conventional semiconductor memory device has the following problems. In the conventional example, the CPU 101 refreshes data of all bits at regular intervals. Here, it is generally known that there is a relationship shown in FIG. 11 between the average failure rate related to data retention of each bit and the use environment temperature. Therefore, in order to prevent the retention characteristics from deteriorating in a high temperature environment, it is necessary to refresh at shorter time intervals as the use environment temperature increases. Further, in order to prevent data destruction due to disturb or soft write, it is necessary to refresh at a time interval corresponding to a bias condition in which disturb or soft write is most likely to occur. As described above, as a first problem, if the refresh time interval is shortened in order to prevent data destruction, the number of refreshes increases. In general, the number of times of writing data in a nonvolatile memory transistor is limited to about 10 ⁴ to 10 ⁵ times. Therefore, in the conventional example, the number of times of refreshing becomes too large, and the nonvolatile memory transistor itself may be destroyed. That is, since the refresh interval according to the actual use state of the semiconductor memory device, that is, the refresh frequency is not set,
Refreshing becomes excessively frequent, and the semiconductor memory device itself is destroyed. Furthermore, when the continuous application time of the power supply voltage to the semiconductor storage device is not permanent, such as in the case of automobile use, and is generally assumed to be several hours, at least within the continuous application time of the power supply voltage. 1
Times, the refresh must be performed. As a result, the number of refreshes is further increased, and the possibility of destruction of the semiconductor memory device is further increased. As a second problem, there is an influence on the read operation of the CPU 101.
In this conventional example, all bits are refreshed. Generally, however, the data write time of the nonvolatile memory transistor is long, and it takes several minutes for all bits. During the refresh, the CPU 101 cannot read data and perform an operation. For this reason, a serious adverse effect of stopping the original operation of the CPU 101 for several minutes occurs.
Third, data destruction cannot be completely prevented. That is, when a temperature stress or a voltage stress more severe than originally expected is applied to the semiconductor memory device, or when a bit whose data retention characteristic is inferior to other bits due to a process defect or the like is generated, the refresh operation is not performed. Data corruption can occur before the The present invention has been made in view of such conventional problems, and provides a highly reliable semiconductor memory device S free from erroneous output of stored data and destruction of the semiconductor memory device itself due to bit destruction. It is intended to be.

[0004]

According to an aspect of the present invention, there is provided a semiconductor memory device having a nonvolatile memory transistor having a floating gate surrounded by an insulating film. Data writing means for storing data in the nonvolatile memory transistor according to a high threshold voltage state and a low threshold voltage state caused by the amount of electronic charge, and for writing the data in the nonvolatile memory transistor; Data reading means for reading data to the outside, and control means for controlling the data writing means and the data reading means, wherein the data reading means is configured so that the high threshold voltage of the nonvolatile memory transistor is equal to If the voltage is lower than the first predetermined voltage, the first abnormality is determined. A first means, wherein the control means stores an address and a bit corresponding to the nonvolatile memory transistor in which the first abnormality is detected in a second storage device using a second nonvolatile memory transistor Second means for performing the data reading corresponding to the bit when an address of the nonvolatile memory transistor requested to read stored data is the same as the address stored in the second storage device Means for transmitting a first signal, and the data reading means, when receiving the first signal, does not read data stored in the non-volatile memory transistor; A configuration including fourth means for reading data corresponding to the threshold voltage to the outside is adopted. Claim 2
2. The semiconductor memory device according to claim 1, wherein said data read means is configured to set said low threshold voltage of said nonvolatile memory transistor to said first predetermined voltage in addition to said first means. The second of the smaller values
The fifth abnormality is determined when the voltage is higher than the predetermined voltage.
Means, and the control means includes, in addition to the second means, an address and a bit of the nonvolatile memory transistor in which the second abnormality is detected, and the first abnormality and the second A sixth means for storing which of the abnormalities has occurred in the second storage device, and an address of the nonvolatile memory transistor requested to read storage data is stored in the second storage device. In the case where the address coincides with the address, if the first abnormality occurrence is stored in the second storage device, the first signal is sent to the data reading means corresponding to the bit, If the second storage device stores the second abnormality occurrence, a seventh means for sending a second signal to the data reading means corresponding to the bit is provided. The output means further generates data corresponding to the low threshold voltage in the logic circuit without reading out the storage data of the nonvolatile memory transistor when receiving the second signal, and The configuration includes an eighth unit that also performs a reading operation. According to a third aspect of the present invention, in the semiconductor memory device according to the first aspect, the semiconductor memory device is a part of a semiconductor memory device including a nonvolatile memory transistor which is built in a microcomputer or the like that uses data stored in the memory device. The second storage device is configured to perform the functions of the second and third means. According to a fourth aspect of the present invention, in the semiconductor memory device according to the second aspect, the semiconductor memory device is a part of a semiconductor memory device using a nonvolatile memory transistor, which is built in a microcomputer or the like that uses data stored in the memory device. The second storage device is configured to perform the functions of the sixth and seventh means. Claim 5
4. The semiconductor memory device according to claim 3, wherein the second memory is stored in an SRAM or a logic circuit built in the memory device while a power supply voltage is applied to the memory device. The storage data of the device is transferred, and the function of the third means is performed using the storage data. According to a sixth aspect of the present invention, in the semiconductor memory device according to the fourth aspect, while the power supply voltage is applied to the storage device, the SRAM or the logic circuit built in the storage device stores the second data in the SRAM or the logic circuit. The configuration is such that the storage data of the second storage device is transferred and the function of the seventh means is performed using the storage data.

According to a seventh aspect of the present invention, in the semiconductor memory device of the first to sixth aspects, the nonvolatile memory transistor is any one of a flash memory, an EEPROM, and an EPROM. In the semiconductor memory device according to claim 8, in the semiconductor memory device according to any one of claims 1 to 7, the data read unit detects that an on-resistance of the nonvolatile memory transistor is larger than the third predetermined value. Thus, the configuration is made to perform the function of the first means. In the semiconductor memory device according to the ninth aspect, in the semiconductor memory device according to any one of the second to seventh aspects, the data reading unit may be configured to determine that the on-resistance of the nonvolatile memory transistor is higher than a fourth predetermined value. It is configured to perform the function of the fifth means by detecting that the value is larger than the value.

[0006]

[Operation] Detects a bit in which stored data is degraded,
After that, without reading out the stored data of the bit, the data readout means outputs the output data determined at the time of the deterioration detection and corresponding to the threshold voltage originally possessed by the bit to the outside. First, since the bit in which the data deterioration has occurred is not read, there is no erroneous output of the stored data, and the reliability is improved. Secondly, since writing such as refreshing is not frequently performed on bits in which data deterioration has occurred, destruction of the semiconductor storage device itself due to bit destruction can be prevented. Third, since the data of the deteriorated bit is not read, the read time of the deteriorated bit becomes longer than the read time of the normal bit which has not deteriorated. There is no problem of adversely affecting the operation of the CPU. Fourth, since data deterioration is actually detected, erroneous output of stored data can be prevented even when a severer temperature stress or voltage stress than originally assumed is applied to the semiconductor memory device.

[0007]

Hereinafter, the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a configuration of the first embodiment. First, the configuration will be described. A plurality of nonvolatile memory transistors each having a floating gate surrounded by an insulating film and storing data according to a high threshold voltage state and a low threshold state caused by the amount of electronic charge in the floating gate. And a memory matrix 1 having the transistor as a bit is formed. A data writing means 2 comprising a writing circuit, a high voltage generating circuit and a decoder is connected to the memory matrix 1, and a data reading means 3 comprising a reading circuit using a sense amplifier and a decoder is also connected to the memory matrix 1. Here, a part or most of the decoder included in the data writing unit 2 and the decoder included in the data reading unit 3 can be shared with each other. Further, both the data writing means 2 and the data reading means 3 are connected to a control circuit 4 for controlling the respective operations, and the second storage device 5 using the second nonvolatile memory transistors is connected to the data writing means 2 and the data reading means. 3 and the control circuit 4 respectively. Note that other circuit means (not shown) may be used for writing and reading data to and from the second storage device 5 without connecting to the data writing means 2 and the data reading means 3.

Next, the operation will be described. The function of newly writing or erasing data in each bit of the memory matrix 1 or the function of reading data of each bit is performed by the control circuit 4, the data writing means 2, and the data reading means 3. Since this portion is not a portion directly related to the present invention, a detailed description is omitted. Here, it is assumed that the relationship between the data state of the nonvolatile memory transistor and the threshold voltage distribution is the same as the relationship in FIG. 10 shown in the section of the conventional example. That is, a state in which electrons are injected into the floating gate in the nonvolatile memory transistor to increase the threshold voltage is referred to as a write state, and a state in which electrons are removed from the floating gate and the threshold voltage is lowered is referred to as a state. Set to the erased state. The high threshold voltage state is defined as data 0, and the low threshold voltage state is defined as data 1.

First, the effect of the present embodiment will be described for the case where the nonvolatile memory transistor is a flash memory. As described in the section of the conventional example, in the flash memory, data stored in the flash memory is easily destroyed due to deterioration of retention characteristics in a high temperature environment, disturb, soft write, and the like. That is, the electrons injected into the floating gate escape to the surroundings, and the threshold voltage of the flash memory which has been in the high threshold voltage state decreases. Alternatively, electrons are injected into the floating gate, and the threshold voltage of the flash memory in the low threshold voltage state increases. Here, the cause of data deterioration, deterioration of retention characteristics in a high-temperature environment, disturb, the most problematic in data retention among soft write, the deterioration of the retention characteristics in a high-temperature environment, Generally known. In particular, when the maximum use environment temperature reaches 80 to 150 ° C. as in the case of an automobile, a significant problem occurs. What matters in retention is a nonvolatile memory transistor in a written state rather than an erased state. The reason will be described with reference to FIG. When no power supply voltage is applied to the semiconductor memory device, both the P-type substrate 16 and the control gate 14 have the GND potential. In the nonvolatile memory transistor in the erased state, no electrons are injected into the floating gate 15, so that there is no excess charge. Therefore, from the floating gate 15 to the P-type substrate 16 or the control gate 1
Since there is no electric field to 4, the charge of the floating gate 15 does not easily increase or decrease. On the other hand, in the non-volatile memory transistor in the written state, an electric field 21 to the P-type substrate 16 and the control gate 14 is generated due to the surplus charge 20 in the floating gate 15. Therefore, electrons in the floating gate 15 may flow out.
The present embodiment focuses on this point, and particularly prevents erroneous output of stored data in a bit in a write state.

This embodiment has a first function of detecting data deterioration, a second function of storing the address and bit number of a non-volatile memory transistor having data deterioration in a second storage device, A third function of notifying the data reading means corresponding to the above-mentioned bits of the data abnormality when a request is made to read the storage data corresponding to the above-mentioned address; And a fourth function of creating and outputting data corresponding to the above by a logic circuit. As a result, there is no erroneous data output, and the reliability is improved. In addition, the non-volatile memory transistor itself caused by excessive refresh is prevented from being destroyed, and there is almost no delay in the read time. Further, the degree of integration of the semiconductor memory device is hardly impaired.

First, for example, the following method is used to realize a first function of detecting a first abnormality in which data deterioration has occurred in a bit in a write state. Inside the data reading means 3, there is provided a sense amplifier 30 capable of detecting whether the degree of turn-on of the nonvolatile memory transistor is equal to or less than a predetermined value.
An example of the sense amplifier 30 is shown in FIG. 3, and the operation principle will be described. The operating point of the PchTr 31 changes depending on whether a nonvolatile memory transistor (not shown) connected to the bit line 36 is on or off. Therefore, when the input voltage of the inverter 32 changes, the output voltage of the inverter 32 changes, and the data stored in the nonvolatile memory transistor is read. For example, if the nonvolatile memory transistor is turned on, a voltage drop occurs in the PchTr 31 and the input of the inverter 32 becomes Low. Therefore, the output 33 of the inverter 32 becomes High level. In the sense amplifier, the inverting input of the comparator 34 is connected in parallel with the input of the inverter 32. The reference voltage VREF is connected to the non-inverting input of the comparator 34. The value of VREF is set equal to or lower than the Vcc voltage and equal to or higher than the logical threshold voltage of the inverter 32. Then, a voltage equal to or slightly lower than the high threshold voltage of the nonvolatile memory transistor is applied to the word line of the nonvolatile memory transistor. If no data is written to the nonvolatile memory transistor, that is, if the state is a low threshold voltage state, the output 33 goes to the high level as described above. On the other hand, data is written to the nonvolatile memory transistor,
In addition, when no data deterioration occurs, the output 33 and the output 35 of the comparator 34 are at the low level. However, when data is written in the non-volatile memory transistor, but the data is deteriorated, the threshold voltage of the non-volatile memory transistor is slightly lower than the value in the high threshold voltage state. As a result, the nonvolatile memory transistor is weakly turned on (has a large on-resistance).
The drain voltage of the PchTr 31 becomes higher than the logic threshold voltage of the inverter 32 and lower than VREF. Therefore, while the output 33 is at the low level, the output 35 is at the high level.
Become a level. As described above, it is possible to detect a bit due to the non-volatile memory transistor in which data deterioration has occurred.

Next, the above-mentioned second function is realized by a method described below. The control circuit 4 controls the data reading means 3
The address and bit number corresponding to the above-described nonvolatile memory transistor having data deterioration detected by the internal sense amplifier 30 are stored in the second storage device 5 by the data writing means 2.

The above-mentioned third function is realized by the following method. If the control circuit 4 determines that the address of the nonvolatile memory transistor requested to read the stored data matches the address stored in the second storage device 5,
Data 0 is sent as a first signal to data reading means corresponding to the bit number stored in the second storage device 5 together with the address.

The above-described fourth function is realized by a method described below. The logic circuit 50 shown in FIG. 4 is connected inside the data reading means 3 for each bit. The configuration of the logic circuit 50 will be described with reference to FIG. The logic circuit 50 includes an AND circuit formed by connecting a two-input NAND 51 and an inverter 54 in series. One input 52 of the two-input NAND 51 is connected to the output of the sense amplifier 30, and the other input 53 is connected to the control circuit 4. The output of the two-input NAND 51 is connected to the input of the inverter 54, and the output of the inverter 54 is used as the output 55 of the logic circuit 50. The logic circuit 50 is formed in each sense amplifier 30 for each bit. Then, the data 53 is input to the input 53 to the logic circuit 50 corresponding to the bit to which the data 0 as the first signal has been sent as described in the third function. On the other hand, 1 is input from the control circuit 4 to the input 53 of the logic circuit 50 corresponding to another normal bit. Then, as shown in the truth table of the logic circuit 50 shown in FIG.
, The signal of the input 52 appears as it is. On the other hand, input 53
Is input to the output 55 irrespective of the signal of the input 52. Therefore, the data corresponding to the write state can be created and output by the logic circuit 50 without reading the data of the bit that has caused the data deterioration as it is.

According to the above-described embodiment, the following effects are produced. First, since the data of the bit in which the data deterioration has occurred is not read out, no erroneous data output occurs, and the reliability of the semiconductor memory device is improved. Secondly, since writing such as refreshing is not frequently performed on bits having data degradation, bit destruction due to refreshing does not occur. Furthermore, even if a bit is destroyed, the bit is not used, so that the function of the entire semiconductor memory device is not affected. Third, the read time of a bit in which data degradation has occurred is later than the read time of a normal bit in which no data degradation has occurred, which adversely affects the operation of a CPU such as a microcomputer using data in the storage device. Is not given. That is, when reading data of normal bits, an address is specified, and after the operation of the decoder, the word line is charged, and the data is determined by the sense amplifier, the data is output via the logic circuit 50. On the other hand, the reading of the data corresponding to the deteriorated bit does not require the charging of the word line or the operation of the sense amplifier, and the control circuit 4 sends the first signal to the logic circuit 50 based on the data stored in the second nonvolatile memory transistor 5. , And the logic circuit 50 only operates. Generally, charging of a word line and operation of a sense amplifier occupy most of the reading time. The logic circuit 50 is a simple AND circuit, and its operation time occupies a small proportion in the read time. Therefore, the data read time does not increase. Fourth, since the present embodiment operates on bits that actually have data degradation,
Even if a severer temperature stress or voltage stress than originally assumed is applied to the semiconductor memory device, erroneous output of stored data can be prevented. Fifth, in the present embodiment, since only the address and bit number of the deteriorated bit are stored in the second storage device 5, it is not necessary to increase the capacity of the second storage device 5. Therefore, the second storage device 5 does not impair the degree of integration of the semiconductor storage device even when compared with the following (1) to (3). (1) A spare memory matrix composed of spare nonvolatile memory transistors is formed inside the memory matrix 1, and the address of a byte including the nonvolatile memory transistor causing data deterioration is switched to the wiring inside the semiconductor memory device. Is not allocated to other bytes in the semiconductor memory device by forming a memory matrix using spare nonvolatile memory transistors and a circuit such as a decoder for selecting the spare nonvolatile memory transistor. Does not impair the degree of integration. (2) There is no configuration in which the CPU of a microcomputer or the like uses the spare memory block or sector without using the memory block or sector including the non-volatile memory transistor whose data has been deteriorated. Therefore, similarly to the above (1), the degree of integration of the semiconductor memory device is not impaired. (3) A configuration in which error correction bits for parity bits are provided corresponding to all bits, such as an ECC circuit, and an error correction circuit including a large number of logic circuits is connected to the original bits and the parity bits. By comparison,
The reading time of each bit is not significantly delayed, and the degree of integration of the semiconductor memory device is not significantly impaired. In the above description, the configuration of the logic circuit 50 has been described as an AND circuit. However, as long as the circuit operates in a similar manner, all the effects described so far occur.

Next, a second embodiment will be described. First, the configuration will be described with reference to FIG. Second storage device 62
Is not provided inside the semiconductor memory device 60 including the memory matrix 1, the data writing means 2, the data reading means 3, and the control circuit 4, and the semiconductor memory device 60
A part of a storage device using a nonvolatile memory transistor in a microcomputer or the like (hereinafter simply referred to as a microcomputer) 61 utilizing the stored data of the above is formed.
Other configurations are the same as those of the first embodiment.

Next, the operation will be described. In the present embodiment, all of the first to fifth effects described in the section of the first embodiment are satisfied. (1) In the nonvolatile memory transistor inside the semiconductor memory device 60, 10 to 20 V
In a structure in which it is difficult to write data in an actual use state because a certain amount of current needs to flow while applying a high voltage of about The effect can prevent a failure of the semiconductor storage device due to data deterioration. (2) As in the second configuration shown in FIG. 7, a third storage device 63 such as an SRAM having a short read time is formed in the semiconductor storage device 60. During the operation of the semiconductor storage device 60, the data stored in the second storage device 62 is transferred to the third storage device 6.
3 and performing the third function using the data stored in the third storage device 63, the time required for performing the third function is further reduced. Therefore, the influence on the read time of the stored data of the semiconductor memory device is further reduced. Here, the third storage device 63 does not necessarily need to be an SRAM, and may be a logic circuit having a data latch function. The effect described in (2) is equally obtained even when the nonvolatile memory transistor is the same as the EPROM described in (1).

FIG. 8 shows the configuration of the third embodiment. First, the configuration will be described with reference to FIG. In the configuration of the first embodiment, a control circuit 70 is connected instead of the control circuit 4, and a data reading unit 71 is connected instead of the data reading unit 3. Other configurations are the same as those of the first embodiment.
Then, the data reading means 71 performs an operation of detecting a second abnormality in which the low threshold voltage of the nonvolatile memory transistor is higher than a second predetermined value, together with the operation of the first function of the first embodiment. It has a fifth function.

Here, the data reading means 71 includes two kinds of reference voltages VR applied to the non-inverting input of the comparator 34 constituting the sense amplifier 30 in the data reading means 3.
The difference from the data reading means 3 is that EF1 and VREF2 can be applied. The value of VREF1 is the same as VREF described in the first embodiment, and the value of VREF2 is equal to or lower than the logical threshold voltage of inverter 32. Therefore VR
EF1> VREF2. This data reading means 7
1 performs the operation of the first function as in the first embodiment. Further, a fifth function of detecting a second abnormality in which data is degraded in an erased bit is realized as follows. A voltage higher than the low threshold voltage of the nonvolatile memory transistor, for example, a Vcc voltage is applied to the word line of the nonvolatile memory transistor. If data has been written to the nonvolatile memory transistor, the output 33 goes low. On the other hand, if the nonvolatile memory transistor is in the erased state and no data deterioration has occurred, both the output 33 and the output 35 are High.
h level. However, when the non-volatile memory transistor is in the erased state and data deterioration has occurred,
That is, when the threshold voltage of the nonvolatile memory transistor is higher than the second predetermined value which is the value in the low threshold voltage state, the degree of ON of the nonvolatile memory transistor is weakened. Therefore, while the output 33 is at the high level, the output 35 is at the low level. For this reason the second
And the fifth function can be performed.

Next, the control circuit 70 operates according to the second embodiment of the first embodiment.
Along with the operation of the function, the second memory device 5 stores the address and bit of the nonvolatile memory transistor in which the second abnormality has been detected, and whether the first abnormality or the second abnormality has occurred in the second storage device 5. 6 functions.

Further, when the address of the nonvolatile memory transistor requested to read the stored data matches the address stored in the second storage device 5, the control circuit 70 If the first abnormality occurrence is stored in the device 5, the first signal is sent to the data reading means 71 corresponding to the bit, and the second abnormality occurrence is stored in the second storage device 5. If so, the data reading means 71 corresponding to the bit
And has a seventh function of transmitting a second signal to the second controller.

The data reading means 71 connects the output 55 to one end of an OR circuit (not shown) in the logic circuit 50 inside the data reading means 3 described in the first embodiment, and Control circuit 4
And the output of the OR circuit is used as the output of the data reading means 71. Thereby, the data reading unit 71 performs the second operation together with the fourth operation of the first embodiment.
When the above signal is received, data corresponding to the low threshold voltage is created by the above-described logic circuit, and the eighth function of reading the data to the outside is also performed. That is, 0 as the first signal, or the second signal
Is applied to the other input of the above-mentioned OR circuit. Then, the output of the OR circuit has 0 corresponding to the high threshold voltage state, or 1 corresponding to the low threshold voltage state.
Appears. If no data abnormality has occurred, O
If 0 is applied to the other input of the R circuit, the stored data is output as it is.

Next, the operation will be described. In the present embodiment, not only the nonvolatile memory transistor in the written state,
The same operation as the operation described in the first embodiment also occurs in the nonvolatile memory transistor in the erased state. Therefore, all of the first to fifth effects described in the first embodiment also occur for the nonvolatile memory transistor in the erased state. Further, also in the third embodiment, the first embodiment
As in the second embodiment, a second storage device 62 is used instead of the second storage device 5, or
Further, by using the third storage device 63, the same effects as (1) and (3) described in the second embodiment can be obtained. In each of the embodiments described above, the nonvolatile memory transistor is a flash memory.
The same effect is obtained with M or EPROM. Also,
The high threshold voltage state and the low threshold voltage state of the nonvolatile memory transistor have been described as the write state and the erased state, respectively.

[0024]

As described above, according to the semiconductor memory device of the present invention, even if a severer temperature stress or voltage stress than originally assumed is applied to the semiconductor memory device, there is no erroneous output of stored data and reliability can be improved. The performance is improved. Further, the operation of the CPU such as a microcomputer is not adversely affected, and further, the destruction of the semiconductor memory device itself due to the destruction of bits can be prevented.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a first embodiment.

FIG. 2 is a diagram illustrating a principle of data deterioration of a memory Tr.

FIG. 3 is a diagram illustrating an example of a sense amplifier according to the first embodiment;

FIG. 4 is a diagram illustrating an example of a logic circuit in Embodiment 1.

FIG. 5 illustrates an operation principle of a logic circuit in Embodiment 1;

FIG. 6 is a diagram showing a configuration of a second embodiment.

FIG. 7 is a diagram showing a second configuration of the second embodiment.

FIG. 8 is a diagram showing a configuration of a third embodiment.

FIG. 9 is a diagram showing a configuration of a conventional example.

FIG. 10 is a diagram showing an operation state of a memory Tr.

FIG. 11 is a diagram showing a relationship between an average failure rate and temperature.

[Explanation of symbols]

 Reference Signs List 1 memory matrix 2 writing means 3 reading means 4 control circuit 5 second storage device 14 control gate 15 floating gate 16 P-type substrate 20 surplus charge 21 electric field 30 sense amplifier 31 PchTr 32 inverter 33 output 34 comparator 35 output 36 bit line 50 Logic circuit 51 2-input NAND 52 input 53 input 54 inverter 55 output 60 semiconductor storage device 61 microcomputer 62 second storage device 63 third storage device 70 control circuit 71 reading means 101 CPU 102 memory matrix 103 tire 104 writing circuit

Claims (9)

[Claims] A non-volatile memory transistor having a floating gate surrounded by an insulating film, wherein a high threshold voltage state and a low threshold voltage state caused by the amount of electronic charges in the floating gate are provided. The nonvolatile memory transistor stores data, and controls a data writing unit that writes the data to the nonvolatile memory transistor, a data reading unit that reads the data to the outside, and controls the data writing unit and the data reading unit. A semiconductor memory device having a control unit, wherein the data read unit determines that the first abnormality is determined when the high threshold voltage of the nonvolatile memory transistor is lower than a first predetermined voltage. And the control unit is configured to detect the first abnormality Means for storing an address and a bit corresponding to the non-volatile memory transistor in a second storage device using a second non-volatile memory transistor, and an address of the non-volatile memory transistor requested to read stored data is A third unit that sends a first signal to the data reading unit corresponding to the bit when the address is the same as the address stored in the second storage device; A semiconductor memory, comprising: fourth means for, when receiving a first signal, reading out data corresponding to the high threshold voltage to the outside without reading out storage data of the nonvolatile memory transistor. apparatus. 2. The semiconductor memory device according to claim 1, wherein said data read means has said low threshold voltage of said nonvolatile memory transistor smaller than said first predetermined voltage in addition to said first means. A second abnormality judging unit for judging a second abnormality when the value is higher than a second predetermined voltage; and the control unit includes the second unit in addition to the second unit.
Sixth means for storing, in the second storage device, an address and a bit of the nonvolatile memory transistor in which the abnormality has been detected, and which of the first abnormality and the second abnormality has occurred; When the address of the nonvolatile memory transistor requested to read storage data matches the address stored in the second storage device, the first abnormality occurs in the second storage device. If stored, sending the first signal to the data read means corresponding to the bit;
If the second storage device stores the second abnormality occurrence, a seventh unit for sending a second signal to the data reading unit corresponding to the bit is provided. Further, when the second signal is received, an operation of creating data corresponding to the low threshold voltage by the logic circuit without reading the storage data of the nonvolatile memory transistor and reading the data to the outside is also provided. A semiconductor memory device having an eighth means for performing. 3. The semiconductor memory device according to claim 1, wherein said semiconductor memory device is a part of a semiconductor memory device using a nonvolatile memory transistor, which is built in a microcomputer or the like that uses data stored in said memory device. A semiconductor storage device comprising a storage device and performing the functions of the second and third means. 4. The semiconductor memory device according to claim 2, wherein the semiconductor memory device is a part of a semiconductor memory device including a nonvolatile memory transistor, which is built in a microcomputer or the like that uses data stored in the memory device. A semiconductor storage device comprising a storage device and performing the functions of the sixth and seventh means. 5. The semiconductor memory device according to claim 3, wherein while a power supply voltage is applied to said storage device, an SRAM or a logic circuit built in said storage device includes:
A semiconductor memory device wherein the storage data of the second storage device is transferred, and the function of the third means is performed using the storage data. 6. The semiconductor memory device according to claim 4, wherein while a power supply voltage is applied to said storage device, an SRAM or a logic circuit built in said storage device includes:
A semiconductor memory device wherein the storage data of the second storage device is transferred, and the function of the seventh means is performed using the storage data. 7. The semiconductor memory device according to claim 1, wherein said non-volatile memory transistor is any one of a flash memory, an EEPROM, and an EPROM. 8. The semiconductor memory device according to claim 1, wherein said data read means detects that an on-resistance of said nonvolatile memory transistor is greater than said third predetermined value, and A semiconductor memory device that performs the function of the means. 9. The semiconductor memory device according to claim 2, wherein said data read means includes a fourth memory transistor having an on-resistance of said non-volatile memory transistor larger than said third predetermined value.
A semiconductor memory device that performs the function of the fifth means by detecting that the value is larger than