JPH11102348A - Multiprocessor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the bus traffic and to improve the throughput by allowing processors of a common memory multiprocessor system to access the same address of a common memory at the same time. SOLUTION: This multiprocessor system includes a bus arbitrating circuit 7a which selects one processor and gives the access right thereto at requests to access the common memory 8 made by processors 1 and 2 and bus control means 4a and 5a which input common memory read data on a common bus 12 to the processor in the unselected state in synchronism with common memory read cycles of the processor selected by the bus arbitrating means.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system, and more particularly, to a bus control device and a boot method in a system in which a plurality of processors share a bus.

[0002]

2. Description of the Related Art In a multiprocessor system, when a plurality of processors and a memory are connected via a shared bus, a contention for an access request to the shared memory from each processor occurs, and an arbitration circuit for arbitrating this contention is provided. A provided configuration is used. For this arbitration circuit,
Various arbitration methods have been proposed so that a plurality of processors can efficiently access a shared memory and improve system performance.

However, the general arbitration system aims at evenly allocating the empty state of the bus to a plurality of processors, and does not improve the access speed of the shared memory of each processor. Therefore, to increase the shared memory access speed of each processor, reduce the bus traffic, and improve the processing performance of the system, increase the bus width, separate the bus, divide the shared memory, There is generally known a technique of providing a data buffer in a computer, and various schemes have been proposed.

Japanese Patent Laid-Open Publication No. Hei 5-20262 proposes a technique for reducing bus traffic by employing a split transaction bus. The split transaction method is a method of dividing a transaction without occupying a bus between read and write transactions. For example, at the time of reading, the data is divided into a read request transaction containing an address and a response transaction containing data, and while the memory is reading data from the requested address, another bus master can use the bus to improve system performance. Is realized.

[0005] The technique disclosed in Japanese Patent Application Laid-Open No. H5-220262 is disclosed in Japanese Patent Application Laid-Open No. H5-220262.
If the read target address of the own processor and the read request address of another processor executed on the shared bus match, the transmission of the bus access right request is stopped and
This is a technology for reducing bus traffic by waiting for a response to a PU read request and loading the data into its own processor, thereby processing the same memory address read that occurred at the same time in the same cycle.

[0006]

However, the technique disclosed in Japanese Patent Application Laid-Open No. H5-220262 is based on the premise that a shared transaction bus is used as a shared bus. At present, a one-chip processor called a microprocessor does not employ a split transaction bus, and in order to apply the above-described conventional technology to a multiprocessor system using a general-purpose microprocessor, it is necessary for each processor and a shared memory to be used. A complicated bus control circuit for controlling the bus of the split transaction method is required, which increases the amount of hardware and increases the cost, and is not suitable for a small-scale multiprocessor system.

In addition, complicated techniques are required for techniques such as increasing the bus width, separating the bus, dividing the shared memory, and providing a data buffer between the bus and the shared memory, and the amount of hardware increases. However, it is disadvantageous in terms of cost and is not suitable for a small multiprocessor system. Therefore, the present invention can be applied to a small-scale multiprocessor system using a general-purpose microprocessor of a non-split transaction type, can be realized with simple hardware, and reduces bus traffic and improves processing performance of shared memory access. A bus control circuit was required.

[0008]

According to a first aspect of the present invention, there is provided a multiprocessor system comprising: an instruction unit for instructing a plurality of processors to operate simultaneously; and a shared memory access request generated by the plurality of processors. Bus arbitration means for selecting one processor to give access right according to the above, and deselecting shared memory read data on the shared bus in synchronization with a shared memory read cycle of the processor selected by the bus arbitration means Bus control means for taking in a processor in a state, wherein the shared memory read requests of the plurality of processors are simultaneously executed in the same bus cycle.

According to a second aspect of the present invention, there is provided a multiprocessor system according to the first aspect, wherein the bus arbitration means generates a shared memory generated from the plurality of processors at different timings. A wait signal transmitting means for synchronizing the read request is provided.

According to a third aspect of the present invention, there is provided a multiprocessor system as set forth in the first or second aspect, wherein the bus arbitration means has a simultaneous operation designated by the instruction means. When a write request to the shared memory occurs, access is granted to one processor and only a response is returned to the other processor, so that write requests to the shared memory by a plurality of processors can be simultaneously performed in the same bus cycle. It is characterized by executing.

According to a fourth aspect of the present invention, there is provided a multiprocessor system according to any one of the first to third aspects, wherein the bus arbitration unit includes an address comparison unit, and the access from the plurality of processors is performed. A feature is that simultaneous operation of a plurality of processors is terminated by detecting a mismatch of request addresses.

According to a fifth aspect of the present invention, there is provided a multiprocessor system as set forth in any one of the first to third aspects, wherein the bus arbitration means includes an address comparison means, and the access from the plurality of processors. It is characterized in that the coincidence of the request addresses is detected and the simultaneous operation is performed only in the case of the comparison coincidence.

According to a sixth aspect of the present invention, there is provided a multiprocessor system according to any one of the first to fifth aspects, further comprising a shared memory storing a boot program of the plurality of processors, wherein a system reset is performed. When released, a plurality of processors execute the start-up program stored in the shared memory at the same time.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a multiprocessor system according to the present invention will be described in detail with reference to the drawings.

[First Embodiment] FIG. 1 is a configuration diagram showing a first embodiment of a multiprocessor system according to the present invention. 1, the multiprocessor system of the present invention connects two processors, a processor 1 and a processor 2, local memories 101 and 201 connected to local buses 102 and 202 of each processor, and each processor to a shared bus 12. Control circuits 4a, 5
a, a bus arbitration circuit 7a for arbitrating a shared bus access request from each processor. Further, control lines 10 and 11 are connected between the bus control circuits 4a and 5a and the bus arbitration circuit 7a.

FIG. 2 is a block diagram of the bus control circuit 4a. 2, a bus control circuit 4a connects the local bus 102 and the shared bus 12 of the processor 1, and includes an address decoder 405, a buffer gate 40
1 to 403, a timing control circuit 404, a gate circuit 4
20 to 423, and a D-type flip-flop 410. Although not shown, the configuration of the bus control circuit 5a is the same as that of the bus control circuit 4a.

FIG. 3 is a configuration diagram of the bus arbitration circuit 7a. In FIG. 3, a bus arbitration circuit 7a is for arbitrating shared bus access of each processor, and includes an arbitration circuit 701, a timing control circuit 702, and gate circuits 710 to 713.

FIG. 4 is a timing chart for explaining the operation of the first embodiment of the multiprocessor system of the present invention. The shared memory 8 is connected to the shared bus 12 so as to be accessible from each processor, and includes a ROM and a RAM (not shown). Shared memory 8
In the ROM portion, operation programs of each processor such as a start program are stored. Although not shown, each processor is supplied with a common RESET signal and CLK signal.

The activation of the multiprocessor system is started by turning on the power and resetting the system.
A signal is supplied to each processor and each control circuit. When the RESET signal is input to the processor 1, the processor 1 initializes internal registers and the like, and starts a read operation of a start vector. The start vector indicates the program execution start address, and the memory address 000000
It is stored at address 00h. This operation is performed by the processor 2
The same applies to the operation of each processor when the system is started, including initialization of the stack pointer, memory management unit, interrupt register, local memory area, etc., and loading of the operation program to the local memory. Execute the same program at the same time.

When each processor is started by the RESET signal, the processor 1 and the processor 2 transmit the time t1
, A read request for the memory address 00000000h, which is the start vector, is generated, and the addresses A31 to A0 and AEN (A
ddress Enable) signal becomes active. At time t1, when a read request from the processor 1 occurs, the address decoder 405 detects that the address of the shared memory has been selected, and since the AEN signal is active, the condition of the AND gate 421 is satisfied and the BRQ1 signal becomes active.

Since the flip-flop 410 is preset by the RESET signal and the SYNC1 signal indicating the simultaneous operation mode of each processor is active, the AND signal is activated when the READ signal becomes active.
The output RDRQ1 signal of the gate 423 becomes active and is output to the bus arbitration circuit 7a together with the BRQ1 signal. Similarly, in processor 2, the BRQ2 signal, R
The DRQ2 signal becomes active and is output to the bus arbitration circuit 7a.

In the bus arbitration circuit 7a, the arbitration circuit 70 receives the bus request signals BRQ1 and BRQ2.
1, one of the requests is selected according to a predetermined priority. Here, BRQ1 is selected, the ADEN1 signal as a response signal thereof is activated, and the RDRQ1 is selected.
1, the DTEN1 and DTEN2 signals become active in synchronization with the CLK signal in the timing control circuit 702 via the OR gates 711 and 713 in response to the RDRQ2 signal.

As a result, the buffer gates 401, 402
Is enabled, and the address signal A3 of the processor 1 is
1-0, the AEN signal adjusted at a predetermined timing by the timing control circuit 404, and the read command RE
The AD signal is output on the shared bus 12 and the data bus D3
1-0 is connected to the shared bus 12, and reading of the address 00000000h of the shared memory 8 is started. On the shared bus 12, data is output from the shared memory 8 at a timing of time t2 after a predetermined access time tac has elapsed.

The memory access cycle of the processors 1 and 2 according to the first embodiment of the multiprocessor system of the present invention is performed in two clock cycles of T1 and T2 unless the WAIT signal which is an access cycle request signal becomes active. . Therefore, at time t3, the READ signal is negated, and the processor 1 reads the read data of the shared memory 8 on the shared bus 12 via the bus control circuit 4a.

Similarly, in processor 2, ADEN
2 signal is negated and only the DTEN2 signal is active, so only the data bus of the shared bus 12 is connected to the local bus 202, and the shared memory data read by the processor 1 is taken in. As a result, the data of the shared memory 8 is read. , And each processor can simultaneously read data at the same address in the shared memory. The address 00000000h of the shared memory is a start vector, in which a program start address is stored.
Since it is 0h, each processor starts an instruction fetch operation from the address 00001000h of the shared memory 8.

At time t4, each processor issues a read request at the address 000010000h at the same timing, and the addresses A31 to A0 and the AEN signal indicating that the address is valid become active. By the same operation as that in the bus cycle 1, the processor 1 and the processor 2 simultaneously fetch an instruction at the address 00001000h of the shared memory 8. Here, a timing chart in the case where BRQ1 is selected in the bus cycle 1 and BRQ2 in the bus cycle 2 is described in the arbitration circuit 701, but the arbitration method of the arbitration circuit 701 is set to a fixed priority, Round robin method with variable priority, etc.
Any desired arbitration scheme can be applied.

In this way, it becomes possible for each processor to simultaneously read instructions in the shared memory and execute the program. When the simultaneous execution processing of each processor such as the initial setting is completed, each processor resets a SYNC flag designating the simultaneous operation. Processor 1
In the example, the SYNC flag is an output SYNC1 signal of the D-type flip-flop 410 in the bus control circuit 4a, and is activated by the RESET signal. S
The YNC flag is allocated to the memory address space of the processor 1 and can be freely set / reset by a program. This is the same in the processor 2.

When the SYNC flags SYNC1 and SYNC2 are reset by the respective processors, the simultaneous operation mode is terminated. In the subsequent shared memory access, an access request is arbitrated by the bus arbitration circuit 7a, and each access is independent. When one processor is performing shared memory access, the other processor is in a wait state. Thus, when the simultaneous operation mode ends, the operation of the ordinary multiprocessor system starts.

[Second Embodiment] Next, a multiprocessor system according to a second embodiment of the present invention will be described. The multiprocessor system of the present invention is composed of three processors. FIG. 5 is an overall configuration diagram, FIG. 6 is a configuration diagram of the bus control circuit 4b, and FIG. 7 is a configuration diagram of the bus arbitration circuit 7b.

In FIG. 6, a bus control circuit 4b connects the local bus 102 of the processor 1 and the shared bus 12, and includes an address decoder 405, buffer gates 401 to 403, a timing control circuit 404, and gate circuits 420 to 424. , D-type flip-flop 411
Consists of Although not shown, the bus control circuit 5
The configurations of b and 6b are the same as those of the bus control circuit 4b.

FIG. 7 is a diagram showing a configuration of the bus arbitration circuit 7b. In FIG. 7, a bus arbitration circuit 7b is for arbitrating shared bus access of each processor and includes an arbitration circuit 701, a timing control circuit 702, an address comparison circuit 703, and gate circuits 715 to 734.

FIG. 8 is a timing chart for explaining the operation of the second embodiment. As in the first embodiment, when the RESET signal is input to the processor 1, the processor 1 initializes internal registers and the like, and starts reading the memory address 00000000h for the read operation of the start vector. Similarly, the processors 2 and 3 start reading the memory address 00000000h. The read request of the memory address 00000000h from each processor is generated at the timing synchronized with the common clock, but is not always generated at the same time, and is not always performed at the same time.
As shown in the bus cycle 1 of FIG. 1, some processors have a delay of one clock cycle. This is because the timing at which the RESET signal is detected by each processor is slightly different.

At the time t1 from the processors 1 and 3, a read request for the memory address 00000000h, which is the start vector, is generated at the time t2 from the processor 2, and the addresses A31 to 0 indicate that the addresses are valid. The AEN signal becomes active. Time t1
, When a read request from the processor 1 occurs, the BRQ1 and RDRQ1 signals become active and output to the bus arbitration circuit 7b as in the first embodiment. Similarly,
In the processor 3, the BRQ3 and RDRQ3 signals are activated and output to the bus arbitration circuit 7b.

In the bus arbitration circuit 7b, when the bus request signals BRQ1 and BRQ3 are inputted, the arbitration circuit 70
1, one of the requests is selected according to a predetermined priority. Here, BRQ1 is selected, the ADEN1 signal as a response signal thereof is activated, and the RDRQ1 is selected.
1, OR gates 717, 723,
DTEN1, DT via the timing control circuit 702
The EN3 signal becomes active. As a result, the address signal A31-0 of the processor 1 and the READ signal as the read command are output onto the shared bus 12, and reading of the address 00000000h of the shared memory 8 is started.

On the shared bus 12, data is output from the shared memory 8 at a time t3 after a predetermined access time tac has elapsed. Also, DTEN1, DTE
The buffer gate 401 of the bus control circuits 4b and 6b is enabled by the N3 signal, and the data bus D31-0 of the processor 1 and the processor 3 is connected to the shared bus 12. Also, the conditions of the AND gates 727 and 733 are satisfied, and the BWAIT1 signal output from the OR gate 726, O
The BWAIT3 signal output from the R gate 732 becomes active.

The BWAIT1 signal is input to the bus control circuit 4b, and the buffer gate 403 is already enabled by the BRQ1 signal. Therefore, the WAIT signal for causing the processor 1 to wait for a read cycle becomes active. Shared memory 8 from 1
A wait cycle is inserted for the read operation.
Similarly, a wait cycle is inserted into the processor 3. The processor 2 issues a read request at time t2, one clock later than the processor 1, and the BRQ2 and RDRQ2 signals become active as in the case of the processor 1.

At this time, in the bus arbitration circuit 7b, DT
The EN2 signal becomes active, the data bus D31-0 of the processor 2 is connected to the shared bus, and
Since the condition of the D gate 724 is satisfied, the BWAIT1 signal is negated, the WAIT signal of the processor 1 is negated, and the wait cycle of the processor 1 ends.
In the processor 1, when the WAIT signal is negated, the next cycle is the T2 cycle, and at time t4, the READ signal is negated and the shared bus 12 is turned off.
The read data of the shared memory 8 is transferred to the bus control circuit 4b
Is read by the processor 1 via. Similarly, the WAIT signal is negated in the processor 3 and the read data of the shared memory 12 is read together with the processor 2. At this time, in the processors 2 and 3, only the data bus of the shared bus 12 is connected to the local bus as in the first embodiment.

Further, in the second embodiment, simultaneous operation is possible not only when the shared memory is read from each processor but also when the shared memory is written. This allows subroutine operations to be performed even during system initialization or program loading.If each processor executes the same subroutine at the same time, it can save the processor internal registers to the stack area. It has become. When each processor executes the same program synchronously, when each processor makes a subroutine call, the values of the internal registers such as the program counter indicate the same value in each processor, and the stack area is in the shared area. If they are allocated, a write request of the same data to the same shared memory address occurs at the same timing. In this case, simultaneous execution of the write operation is effective.

The state of the simultaneous write operation is shown in the time chart of FIG. 8, and a write request of the memory address 00002000h is generated from the processor 1, the processor 2 and the processor 3 at the timing of time t5, and the addresses A31 to A0 are output. , The AEN signal indicating that the address is valid becomes active. At time t5, when a write request from the processor 1 occurs, the address decoder 405
Detects the selection of the address of the shared memory, and since the AEN signal is active, the condition of the AND gate 421 is satisfied and BR
Since the Q1 signal becomes active and is a write request, A
The condition of the ND gate 424 is satisfied, and the WTRQ1 signal becomes active.

Similarly, in the processors 2 and 3, the BR
The signals Q2, WTRQ2, BRQ3, and WTRQ3 become active and are output to the bus arbitration circuit 7b. In the bus arbitration circuit 7b, the bus request signals BRQ1, BRQ2,
When the BRQ3 signal is input, one of the requests is selected in the arbitration circuit 701 according to a predetermined priority. Here, the BRQ1 is selected, the ADEN1 signal as a response signal thereof is activated, and the WTRQ1 signal is used.
The condition of the AND gate 715 is satisfied, and the OR gate 717,
The DTEN signal becomes active via the timing control circuit 702.

As a result, the buffer gates 401 and 402
Is enabled, and the address signal A3 of the processor 1 is
1-0, the AEN signal adjusted at a predetermined timing by the timing control circuit 404, and the write command WR
An ITE signal is output on the shared bus 12 and the data bus D
31-0 is connected to the shared bus 12, and writing to the address 00002000h of the shared memory 8 is started. On the shared bus 12, data is written from the processor 1 to the shared memory 8 at the timing of time t6, which is the falling timing of the WRITE signal. Here, since the processors 2 and 3 are the same address and the same data write request as the processor 1, ADEN2, 3, DTEN2,
The three signals remain negated, and the writing process can be performed only by returning an access response (in the second embodiment, not activating the WAIT signal) without connecting the bus.

In this way, each processor simultaneously reads instructions in the shared memory 8 and executes the program at the same time. When the simultaneous execution processing of each processor such as initialization is completed, each processor executes its own processing. Start execution of the routine. At this time, each processor issues a read request for the individual address of the shared memory 8 at the same timing, at time t7.

In FIG. 8, the processor 1 sends an address 00
A read request at address 010000h, an address at address 00020000h from processor 2, and a read request at address 00030000h from processor 3 are shown. At time t7, the addresses from the respective processors are compared by the address comparison circuit 703 of the bus arbitration circuit 7b, and when the RDRQ1, 2, and 3 signals from all the processors are aligned and a mismatch is detected, the SYNCRST signal becomes active. And the D-type flip-flop 411 in the bus control circuit 4b is reset, the simultaneous operation mode ends, and SYNC1, 2, 3, RDQRQ1,.
A few signals are all negated.

At the same time, the access request of the processor 1 is selected by the arbitration circuit 701, the ADEN1 signal becomes active, the condition of the AND gate 716 is satisfied, and DT
The EN1 signal is also activated. Thereby, the read request of the processor 1 is selected, and the read operation of the address 00010000h of the shared memory 8 is executed.

At this time, in the processor 2, the ADE
Since the N2 and SYNC2 signals are negated, AN
The condition of the D gate 728 is satisfied, and the BWAIT2 signal becomes active. Similarly, in processor 3, BWA
The IT3 signal becomes active, and processors 2 and 3
The wait state is set by the IT signal, and the process waits until the read cycle of the processor 1 ends. Thereafter, the arbitration circuit arbitrates the access requests, and accesses the shared memory in order according to a predetermined priority.

Third Embodiment Next, a third embodiment of the multiprocessor system according to the present invention will be described. In the third embodiment, the configuration diagram of the multiprocessor system and the configuration diagram of the bus control circuit 4b are shown in FIGS. 5 and 6 similarly to the second embodiment, and FIG. 9 shows the bus arbitration circuit of the third embodiment. 7c shows the configuration of FIG. In FIG. 5, the difference from the second embodiment is that the bus control circuit 7b is replaced with a bus control circuit 7c. As shown in FIG. 9, the bus arbitration circuit 7c is for arbitrating shared bus access of each processor, and includes an arbitration circuit 701, a timing control circuit 702, an address comparison circuit 703, and gate circuits 734 to 734.
743.

FIG. 10 is a timing chart for explaining the operation of the third embodiment. At the timing of the time t1, when a read request for the memory address 00001000h of the shared memory 8 is generated from the processors 1, 2, and 3, the BRQs 1, 2, 3, RDRQ1, and RDRQ1 are transmitted from the processors as in the first and second embodiments. A few signals become active and are output to the bus arbitration circuit 7c. In the bus arbitration circuit 7c, the bus request signals BRQ1, 2, 3
When a signal is input, an arbitration circuit 701 selects any request according to a predetermined priority.

Here, BRQ1 is selected, and the response signal ADEN1 becomes active, and the address comparison circuit 703 compares the read request addresses of the processors. In this example, all the processors are at the address 00001000h. Request to read
The address match signal becomes active, and the AND gate 7
35, 737, and 739, and RDRQ1, 2, and 3
The signals make the DTEN1,2,3 signals active through the OR gates 736,738,740 and the timing control circuit 702. As a result, the address signal A31-0 of the processor 1 and the READ signal as a read command are output on the shared bus 12, and reading of the address 00001000h of the shared memory 8 is started.

On the shared bus 12, data is output from the shared memory 8 at a time t2 after a predetermined access time tac has elapsed. Also, DTEN1,2,3
The signal, the buffer gate 40 of the processor 1, 2, 3
1 is enabled, the data buses D31-0 of the processors 1, 2, and 3 are connected to the shared bus 12, and the time t
At timing 3, the READ signal is negated, and the processor 1 reads the read data of the shared memory 8 on the shared bus 12 via the bus control circuit 4b. Similarly, in the processors 2 and 3, the data on the shared bus 8 is fetched and the shared memory 8 is read.

Next, at time t4, when a read request for a different address is issued from each processor, BRQ1, BRQ1,
2, 3, RDRQ1, 2, 3 signals become active,
Output to the bus arbitration circuit 7c. In the arbitration circuit 701,
BRQ1 is selected, the response signal ADEN1 becomes active, and the address comparison circuit 703 is selected.
The read request address of each processor is compared at
In this example, since the processor 1 requests the reading of the address 00010000h, the processor 2 requests the reading of the address 00020000h, and the processor 3 requests the reading of the address 00030000h, the address match signal does not become active and the signals DTEN2 and DTEN3 remain negated.

Processor 1 is already selected and ADEN1
Since the signal is active, the OR gate 736
Becomes valid, and the DTEN1 signal becomes active. As a result, the read request of the processor 1 is selected, the address 00010000h of the shared memory 8 is output onto the shared bus 12, and the reading of the address 00010000h of the shared memory 8 is started. On the shared bus 12, data is output from the shared memory 8 at a timing of time t5 after a predetermined access time tac has elapsed. The buffer gate 401 is enabled by the DTEN1 signal,
The data bus D31-0 of the processor 1 is connected to the shared bus 12, the READ signal is negated at time t6, and the read data of the shared memory 8 on the shared bus 12 is transferred via the bus control circuit 4b. The processor 1 leads.

At this time, in the processors 2 and 3, A
The DEN2 and DEN3 signals and the address match signal are negated, and the AND gates 742 and 743 become valid,
When the WAIT2 and BWAIT3 signals become active, the WAIT signal for each processor becomes active and the processor enters a wait state.

Next, at the timing of time t7, the processor 1 next issues a read request at the address 00001004h, and the BRQ1 and RDRQ1 signals become active. The BRQ2 signal, which is a request, is selected, and its response signal ADE
The N2 signal becomes active, a read request from the processor 2 is selected, and reading of the address 00020000h of the shared memory 8 is executed. At this time, the processors 1 and 3 are in the wait state.

Subsequently, at the timing of time t8, the processor 2 issues a read request at the address 00001004h, but the processor 3 is selected in this bus cycle and the address 000300000 in the shared memory 8 as described above.
The reading of address h is executed. At this time, the processors 1 and 2 are in the wait state.

Thereafter, when the processor 3 issues a read request at the address 00001004h at the timing of the time t9, the processors 1 and 2 have already sent the address 000010 from the processor 1.
Since the request at address 004h has occurred and the read request addresses of all the processors are at address 00001004h, the read request addresses of the processors are compared by the address comparison circuit 704 in the same manner as in the bus cycle 1, and the address matches. The signal becomes active, and the DTEN1, 2, and 3 signals become active. Thereby, the processors 1, 2,
3 read requests are executed simultaneously.

Thereafter, the read request addresses from the processors are similarly compared, and if all the processors have the same address, the simultaneous operation is performed. If the addresses are different, the shared memory is accessed according to a predetermined priority. Becomes possible.

[0057]

As described above, according to the multiprocessor system of the present invention, in a multiprocessor system in which a plurality of processors access the shared memory, the same address access of the shared memory can be executed simultaneously, and the shared bus Bus traffic is reduced. Especially,
Since the common operation of each processor at the time of system startup can be performed in parallel, the system startup time can be reduced.
Further, the same data such as a program and shared data can be simultaneously transferred to a plurality of processors, so that the data transfer time can be reduced and the system performance can be improved.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a first embodiment of a multiprocessor system of the present invention.

FIG. 2 is a configuration diagram of a bus control circuit 4a of FIG.

FIG. 3 is a configuration diagram of a bus arbitration circuit 7a of FIG. 1;

FIG. 4 is a timing chart showing an operation of the multiprocessor system according to the first embodiment of the present invention;

FIG. 5 is an overall configuration diagram of Embodiments 2 and 3 of the multiprocessor system of the present invention.

FIG. 6 is a configuration diagram of a bus control circuit 4b of FIG. 5;

FIG. 7 is a configuration diagram of a bus arbitration circuit 7b of FIG. 5;

FIG. 8 is a timing chart showing an operation of the multiprocessor system according to the second embodiment of the present invention.

FIG. 9 is a configuration diagram of a bus arbitration circuit 7c according to a third embodiment of the multiprocessor system of the present invention.

FIG. 10 is a timing chart showing an operation of the multiprocessor system according to the third embodiment of the present invention.

[Description of Signs] 1, 2, 3 Processors 4a, 5a, 4b, 5b, 6b Bus control circuit 7a, 7b, 7c Bus arbitration circuit 8 Shared bus 10, 11 Control information line 101, 201, 301 Local memory 102, 202 , 302 Local bus 401, 402, 403 Buffer gate 404 Timing control circuit 405 Address decoder 410, 411 Flip-flop 420-424 Gate circuit 701 Arbitration circuit 702 Timing control circuit 703 Address comparison circuit 710-743 Gate circuit

Claims (6)

[Claims] An instruction means for instructing a plurality of processors to perform simultaneous operations; a bus arbitration means for selecting one processor and granting an access right in response to a shared memory access request generated from the plurality of processors; Bus control means for taking in the shared memory read data on the shared bus to the unselected processor in synchronization with the shared memory read cycle of the processor selected by the bus arbitration means; A multiprocessor system wherein requests are executed simultaneously in the same bus cycle. 2. The multi-path arbitration means according to claim 1, wherein said bus arbitration means comprises wait signal sending means for synchronizing shared memory read requests generated at different timings from a plurality of processors. Processor system. 3. The bus arbitration means permits access to one processor and returns only a response to the other processor when a write request to the shared memory is generated in a state where the simultaneous operation is designated by the instruction means. By doing
3. The multiprocessor system according to claim 1, wherein write requests to a shared memory of a plurality of processors are executed simultaneously in the same bus cycle. 4. The bus arbitration unit includes an address comparison unit, and detects a mismatch between access request addresses from the plurality of processors, and terminates the simultaneous operation of the plurality of processors. 4. The multiprocessor system according to any one of claims 3 to 3. 5. The bus arbitration unit includes an address comparison unit, detects a match of an access request address from the plurality of processors, and performs a simultaneous operation only in the case of a comparison match. 4. The multiprocessor system according to 3. 6. A shared memory storing a boot program of the plurality of processors, wherein the plurality of processors simultaneously execute the boot program stored in the shared memory when a system reset is released. The multiprocessor system according to claim 1.