JPH1098162A - Method for manufacturing semiconductor integrated circuit device - Google Patents

Abstract

[PROBLEMS] To prevent a reaction product having a low vapor pressure from adhering to a side wall of a pattern when a Pt film or a PZT film is dry-etched to form a predetermined pattern. SOLUTION: A Pt film 53 deposited on a semiconductor substrate 50 is provided.
Is used, a resist mask 54 having a rounded outer peripheral portion of the head is used. After dry etching, an appropriate amount of over-etching is performed to completely remove the sidewall adhesion film 55 remaining on the side surfaces of the pattern. The resist mask 54 is formed by exposing and developing a benzophenone-based novolak resist, and then heating and curing it while irradiating ultraviolet rays as necessary.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit device having a ferroelectric (high) dielectric capacitor, and more particularly to a method for manufacturing a semiconductor integrated circuit device using a conductive material which generates a reaction product having a low vapor pressure during dry etching. The present invention relates to a technique effective when applied to a process for manufacturing a (high) dielectric capacitor.

[0002]

2. Description of the Related Art Large capacity D of 256 Mbit to 1 Gbit or more
A RAM (Dynamic Random Access Memory) has a capacitance insulating film of an information storage capacitor (capacitor) formed of Ta ₂ as a countermeasure to compensate for a decrease in the amount of stored charge due to miniaturization of a memory cell.
High dielectric materials such as O ₅ and BST ((Ba, Sr) TiO ₃ ) having a relative dielectric constant of 20 or more, and PZT (Pb
Zr _X Ti _1-X O ₃ ), PLT (PbLa _X Ti
_1-X O ₃ ), PLZT, PbTiO ₃ , SrTiO ₃ , B
It is required to be made of a ferroelectric material having a relative dielectric constant of more than 100, such as aTiO ₃ .

On the other hand, in the field of non-volatile memory,
Development of a ferroelectric memory utilizing the above-described polarization inversion of the ferroelectric material for storing data has been advanced.

When the capacitor insulating film of a capacitor is made of a ferroelectric (high) dielectric material as described above, a conductive film for an electrode sandwiching the capacitor insulating film also has a high affinity for these materials. It must be made of a high melting point metal material such as Pt.

However, a problem in forming a capacitor using Pt or PZT is that when a thin film of Pt or PZT deposited on a substrate is processed by dry etching, a reaction product having a low vapor pressure may cause a pattern. It is known that a large amount adheres to the side surface of the capacitor, which causes a short circuit between the capacitors.

Conventionally, when a Pt film is processed by dry etching, as a countermeasure for preventing reaction products from adhering to a side surface of a pattern, a method of providing a taper on a side surface of a photoresist used as an etching mask, a method of forming a photoresist, and the like. Instead, a method using a hard mask such as a silicon oxide film or a metal film is known.

[0007] In 1996, the 43rd Joint Lecture on Applied Physics, Proceedings of the Lecture Series, No. 2, 27p-N-9 dry-etches a three-layer film of Pt / PZT / Pt deposited on a substrate. In this case, it is reported that a clean capacitor without a sidewall adhesion film can be formed by using a resist mask having a taper of about 75 degrees on the side surface. This is because, when a taper is provided on the side surface of the resist mask, etching ions are also irradiated on the side surface of the pattern, so that the taper angle is made larger than a certain value (approximately 75 degrees) so that the side wall adhesion film is deposited. This is considered to be because the rate of removal by etching is higher than the rate of removal.

No. 2, 26a-ZT-4, 1995, The 56th Annual Meeting of the Japan Society of Applied Physics, Proceedings of the Lectures, No. 2 uses a silicon oxide film etched in a predetermined pattern as a mask when dry etching a Pt film. It is reported that by using an etching gas obtained by adding oxygen to Ar and using an etching gas, the Pt film is processed into a tapered shape, and etching without a sidewall adhesion film becomes possible.

Japanese Patent Application Laid-Open No. Hei 5-89662 discloses a method of forming a good Pt pattern without a sidewall adhesion film by etching a Pt film using a Ti film etched into a predetermined pattern as a mask. I have.

[0010] Brian Chapma
n) "Glow Discharge Processes SPUTTERING AND PLAS
MA ETCHING "p244 to p253 discloses an RIE etching technique using a tapered resist mask.

[0011]

However, according to studies made by the present inventor, the conventional method of patterning a Pt film using a resist mask having a tapered side surface involves a process of forming a tapered side surface of the resist mask. However, there is a problem that it is not only complicated but also difficult to form a fine Pt pattern with high dimensional accuracy.

On the other hand, a method using a hard mask such as a silicon oxide film or a metal film forms a hard mask pattern by dry-etching these films deposited on a Pt film, and is therefore less effective than a method using a resist mask. Therefore, there is a problem that the number of steps increases. In addition, since it is necessary to heat the hard mask to about 300 ° C. during the etching, when the Pt film on the ferroelectric (high) dielectric film is etched, the underlying ferroelectric (high) dielectric film is deteriorated. There is also a problem that it is difficult to remove the hard mask by ashing after the etching is completed.

An object of the present invention is to provide a method for patterning a thin film of Pt or the like deposited on a substrate by dry etching using a resist mask without leaving a reaction product having a low vapor pressure on the side of the pattern and having a high size. It is an object of the present invention to provide a technique capable of forming a fine pattern with high accuracy.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0015]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) A method of manufacturing a semiconductor integrated circuit device according to the present invention comprises a single or a plurality of films including a film which is formed directly or indirectly on a first main surface of a wafer and which easily causes side wall adhesion. A thin film is formed by using a photoresist of a predetermined pattern in which at least the lower half side is substantially vertical and a forward taper or roundness is formed on the outer periphery of the head as a mask, and a forward taper reaching the lower end is formed on the side of the thin film pattern. To perform patterning by dry etching.

(2) The method of manufacturing a semiconductor integrated circuit device according to the present invention includes a step of forming the thin film pattern and then performing an over-etching to remove a sidewall adhesion film remaining on a side surface of the thin film pattern. I have.

(3) The thin film contains a platinum thin film.

(4) The thin film includes a high dielectric thin film or a ferroelectric thin film.

(5) The method of manufacturing a semiconductor integrated circuit device according to the present invention comprises the steps of: (a) directly forming a thin film composed of a single film or a plurality of films including a film which easily causes side wall adhesion on the first main surface of the wafer; Or a step of indirectly forming (b) on the thin film,
A step of directly or indirectly forming a predetermined pattern of photoresist having at least a lower half side surface substantially vertical and having a forward taper or roundness at the outer periphery of the head; (c) using the photoresist of the predetermined pattern as a mask Patterning the thin film by dry etching such that a forward taper reaching the lower end is formed on the side surface of the thin film pattern.

(6) The method of manufacturing a semiconductor integrated circuit device according to the present invention includes a step of forming the thin film pattern and then performing an over-etching to remove a sidewall adhesion film remaining on a side surface of the thin film pattern. I have.

(7) The thin film contains a platinum thin film.

(8) The thin film includes a high dielectric thin film or a ferroelectric thin film.

(9) The method of manufacturing a semiconductor integrated circuit device according to the present invention comprises the steps of: (a) directly forming a thin film composed of a single film or a plurality of films including a film that easily causes side wall adhesion on the first main surface of the wafer; Or (b) a step of directly or indirectly spin-coating a positive-type benzophenone-based novolak resist on the thin film; (c) exposing and developing the positive-type benzophenone-based novolak resist to a predetermined resist pattern (D) heating at least the resist pattern and irradiating the surface with ultraviolet rays to cure the resist pattern; and (e) using the cured resist pattern as a mask to form the thin film. Pattern by dry etching so that a forward taper reaching the lower end is formed on the side surface of the thin film pattern. (F) removing the sidewall adhesion film remaining on the side surface of the thin film pattern by performing over-etching after forming the thin film pattern, and after completion of the (d) process, removing the resist pattern. In order to weaken the surface insolubilization of the unexposed portion during development of the positive benzophenone-based novolak resist so that the outer periphery of the head is rounded.

(10) The thin film contains a platinum thin film.

(11) The thin film includes a high dielectric thin film or a ferroelectric thin film.

(12) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, a photolithography process by reduced projection exposure using a positive type or negative type photoresist and exposure light having substantially the same wavelength is repeated. In patterning a plurality of thin films, in some of the steps of the photolithography process, the positive or negative first photoresist is used, and in some other steps or substantially all other steps. In the above method, a second photoresist having the same positive and negative types as the first photoresist and having different pattern shape characteristics is used.

(13) The first photoresist is a positive benzophenone novolak resist, and the second photoresist is a positive non-benzophenone novolak resist.

(14) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, a thin film comprising a single film or a plurality of films including a film which is liable to adhere to a side wall, using the resist pattern composed of the first photoresist as a mask. Patterning step.

(15) The method of manufacturing a semiconductor integrated circuit device according to the present invention includes a step of patterning the thin film and then performing over-etching to remove a sidewall-adhering film remaining on a side surface of the thin film pattern. .

(16) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, (a) a first thin film composed of a single or a plurality of films is formed directly or indirectly on a first main surface of a wafer. A step of (b) directly or indirectly forming a first photoresist film made of a positive non-benzophenone-based novolak resist on the first thin film, and (c) reducing projection of the first photoresist film. After exposing by an exposure process, developing the first photoresist film on which the exposure has been completed to form a first resist pattern on the first thin film, and (d) the first resist Patterning the first thin film by dry etching using a pattern as a mask to form a gate electrode of a MISFET on a first main surface of the wafer; (e) forming the gate electrode On a first main surface of the wafers,
A step of directly or indirectly forming a second thin film comprising a single film or a plurality of films including a film which is liable to adhere to a side wall during dry etching; (f) forming a second thin film on the second thin film from a positive benzophenone-based novolak resist; (G) spin-coating the second photoresist film directly or indirectly, and (g) exposing the second photoresist film by a reduced projection exposure process, and then removing the exposed second photoresist film. A developing process to form a second resist pattern on the second thin film; (h) dry etching using the second resist pattern as a mask to convert the second thin film to a side surface of the thin film pattern; Patterning such that a forward taper reaching the lower end is formed. (I) After the thin film pattern is formed, overetching is further performed. Removing the sidewall deposited film remaining on the side surface of the thin film pattern performed includes.

(17) The second thin film is a thin film constituting a capacitor of a DRAM memory cell.

(18) The second thin film is made of a ferroelectric RA
This is a thin film forming a capacitor of the M memory cell.

(19) The second thin film is made of Pt, Ir,
IrO ₂ , Rh, RhO ₂ , Os, OsO ₂ , Ru, R
It contains one or more metal thin films or conductive metal oxide thin films selected from the group selected from uO ₂ , Re, ReO ₃ , Pd and Au.

(20) The second thin film is made of PZT, PL
One or two members selected from the group consisting of T, PLZT, SBT, PbTiO ₃ , SrTiO ₃ and BaTiO ₃
It contains more than one kind of ferroelectric thin film.

(21) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, (a) a first thin film composed of a single film or a plurality of films is directly or indirectly formed on a first main surface of a wafer. (B) forming, directly or indirectly, a positive type first photoresist film on the first thin film, wherein the cross-sectional shape of the upper end or upper half of the pattern side surface is orthogonal.
(C) after exposing the first photoresist film by a reduced projection exposure process, developing the exposed first photoresist film to form a first resist pattern on the first thin film; (D) patterning the first thin film by dry etching using the first resist pattern as a mask to form a gate electrode of a MISFET on a first main surface of the wafer; (E) a step of directly or indirectly forming a second thin film composed of a single film or a plurality of films on a first main surface of the wafer on which the gate electrode is formed, (f) the second thin film A step of directly or indirectly spin-coating a second photoresist film of a positive type in which a cross-sectional shape of an upper end portion or an upper half of a pattern side surface is not perpendicular to that of the first photoresist film. After exposure by reduction projection exposure process (g) of the second photoresist film, and developing the second photoresist film the exposure is completed,
Forming a second resist pattern on the second thin film, and (h) reaching the lower end of the second thin film on the side surface of the thin film pattern by dry etching using the second resist pattern as a mask. And (i) removing the sidewall adhesion film remaining on the side surface of the thin film pattern by performing over-etching after forming the thin film pattern.

(22) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, (a) a first thin film composed of a single film or a plurality of films is formed directly or indirectly on a first main surface of a wafer. (B) forming directly or indirectly, on the first thin film, a first photoresist film in which the cross-sectional shape of the upper end portion or the upper half of the pattern side surface is orthogonal, and (c) the first photoresist film. Exposing the photoresist film by a reduced projection exposure process, and then developing the exposed first photoresist film to form a first resist pattern on the first thin film; (d (E) forming a gate electrode of a MISFET on a first main surface of the wafer by patterning the first thin film by dry etching using the first resist pattern as a mask;
Forming directly or indirectly a second thin film including a conductive film composed of a single film or a plurality of films on a first main surface of the wafer on which the gate electrode is formed; (G) spin-coating directly or indirectly on the thin film a second photoresist film in which the cross-sectional shape of the upper end portion or upper half of the pattern side surface is not perpendicular to that of the first photoresist film; Exposing the second photoresist film by a reduced projection exposure process, and then developing the exposed second photoresist film to form a second resist pattern on the second thin film. ,
(H) patterning the second thin film by dry etching using the second resist pattern as a mask such that a forward taper reaching the lower end thereof is formed on a side surface of the thin film pattern; (i) the thin film After the pattern is formed, a step of performing overetching to remove the side wall adhesion film remaining on the side surface of the thin film pattern is included.

(23) The method of manufacturing a semiconductor integrated circuit device according to the present invention includes the steps of (a) directly forming a thin film composed of a single film or a plurality of films including a film which easily causes side wall adhesion on the first main surface of the wafer. Or (b) a step of directly or indirectly forming a positive resist pattern on the thin film, wherein at least the lower half side is substantially vertical and the outer periphery of the head is rounded; Using the resist pattern as a mask, the thin film is formed on the side surface of the thin film pattern by forming a forward taper reaching the lower end thereof and at the side surface of the side wall adhesion film adhering to the respective side surfaces of the resist pattern and the thin film pattern. Patterning by dry etching so as to form a forward taper reaching the lower end, (d) after forming the thin film pattern,
The method further includes a step of removing the sidewall adhesion film remaining on the side surface of the thin film pattern by performing over-etching.

(24) The method of manufacturing a semiconductor integrated circuit device according to the present invention comprises the steps of: (a) directly forming a thin film composed of a single film or a plurality of films including a film which easily causes side wall adhesion on the first main surface of the wafer; Or indirectly forming a resist pattern; (b) directly or indirectly forming a positive resist pattern having a substantially vertical side surface on the thin film; and (c) baking the resist pattern to form the resist pattern. Forming a forward taper on the outer peripheral portion of the head portion of the thin film; (d) using the resist pattern as a mask, forming a forward taper on the side surface of the thin film pattern to reach the lower end thereof; The pattern is formed by dry etching so that a forward taper reaching the lower end is formed on the side surface of the side wall film adhering to each side surface of the thin film pattern. A step of grayed includes the step, of removing the sidewall deposited film remaining on the side surface of the (e) after forming the thin film pattern, the thin film pattern by performing a further over-etching.

(25) The method of manufacturing a semiconductor integrated circuit device according to the present invention includes the steps of (a) directly forming a thin film composed of a single film or a plurality of films including a film which easily causes side wall adhesion on the first main surface of the wafer. Or (b) spin-coating a photoresist directly or indirectly on the thin film; (c) exposing and developing the photoresist to form a predetermined resist pattern; (d) Using the resist pattern as a mask, patterning the thin film by dry etching so that a forward taper reaching the lower end of the thin film pattern is formed on the side surface of the thin film pattern;
(E) removing the side wall attached film remaining on the side surface of the thin film pattern by performing over-etching after forming the thin film pattern, and controlling a focus condition of exposure light when exposing the photoresist. Thereby, a forward taper or roundness is formed on the outer peripheral portion of the head of the resist pattern.

(26) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, (a) a first thin film composed of a single film or a plurality of films is directly or indirectly formed on a first main surface of a wafer. (B) forming directly or indirectly a first photoresist film made of a positive chemically amplified photoresist on the first thin film, and (c) exposing the first photoresist film. And developing to form a first resist pattern on the first thin film; (d) patterning the first thin film by dry etching using the first resist pattern as a mask, Forming a gate electrode of a MISFET on the first main surface of (a), and (e) including, on the first main surface of the wafer on which the gate electrode is formed, a film which is likely to cause side wall adhesion during dry etching. (F) directly or indirectly forming a second thin film made of one or more films, and (f) directly or indirectly forming a second photoresist film made of a negative chemically amplified photoresist on the second thin film. Indirectly spin-coating, and (g) exposing and developing the second photoresist film to form a second resist pattern on the second thin film having a rounded outer periphery of a head. ,
(H) patterning the second thin film by dry etching using the second resist pattern as a mask.

(27) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, (a) a first thin film composed of a single film or a plurality of films is directly or indirectly formed on a first main surface of a wafer. (B) forming directly or indirectly a first photoresist film made of a positive chemically amplified photoresist on the first thin film, and (c) exposing the first photoresist film. And developing to form a first resist pattern on the first thin film; (d) patterning the first thin film by dry etching using the first resist pattern as a mask, Forming a gate electrode of a MISFET on the first main surface of (a), and (e) including, on the first main surface of the wafer on which the gate electrode is formed, a film which is likely to cause side wall adhesion during dry etching. (F) directly or indirectly forming a second thin film composed of one or a plurality of films, and (f) directly or indirectly forming a second photoresist film composed of a positive chemically amplified photoresist on the second thin film. Indirectly spin coating, (g) exposing and developing the second photoresist film to form a second resist pattern on the second thin film, (h) the second resist pattern Irradiating ultraviolet rays to dissolve only the surface,
(I) After spin-coating an acidic polymer on the surface of the second resist pattern in which only the surface is dissolved, baking treatment is performed on the second resist pattern, so that the second resist pattern has a rounded outer peripheral portion. And (j) patterning the second thin film by dry etching using the second resist pattern as a mask.

(28) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, (a) a first thin film composed of a single film or a plurality of films is directly or indirectly formed on a first main surface of a wafer. A step of (b) directly or indirectly forming a first photoresist film made of a positive-type methacrylic acid-based photoresist on the first thin film, and (c) exposing the first photoresist film to light. And developing to form a first resist pattern on the first thin film; (d) patterning the first thin film by dry etching using the first resist pattern as a mask, Forming a gate electrode of a MISFET on the first main surface of (a), (e) forming, on the first main surface of the wafer on which the gate electrode is formed, a film which is likely to cause side wall adhesion during dry etching. (F) directly or indirectly forming a second thin film composed of a single or a plurality of films, and (f) forming a second photoresist film composed of a negative type methacrylic acid-based photoresist on the second thin film. Directly or indirectly spin-coating, (g) exposing and developing the second photoresist film to form a second resist pattern on the second thin film having a rounded outer periphery of a head (H) patterning the second thin film by dry etching using the second resist pattern as a mask.

(29) The method of manufacturing a semiconductor integrated circuit device according to the present invention comprises the steps of (a) directly or indirectly forming a thin film composed of a single film or a plurality of films including a film that easily causes side wall adhesion on a main surface of a wafer. (B) a step of directly or indirectly spin-coating a positive photoresist on the thin film; (c) a step of exposing and developing the photoresist to form a predetermined resist pattern; (d) By performing dry etching for a short time under such a condition that only the resist pattern is etched, and that abrasion proceeds in an oblique direction from a corner of the head of the resist pattern,
Forming a forward taper on the outer periphery of the head of the resist pattern, (e) patterning the thin film by dry etching using the resist pattern as a mask, and (f) further patterning the thin film after patterning. Removing the side wall adhered film remaining on the side surfaces of the thin film pattern by performing etching.

[0045]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) Pt of the present embodiment
A method for dry-etching a film will be described with reference to FIGS.

First, as shown in FIG. 1, after a silicon oxide film 51 is formed on a single crystal silicon semiconductor substrate 50, a 20 nm-thick Ti film 52 is deposited thereon as a barrier metal by a sputtering method. Further, a Pt film 53 having a thickness of 100 nm is deposited thereon by a sputtering method.

Next, as shown in FIG. 2, a positive type photoresist spin-coated on the Pt film 53 is exposed and developed, and at least the lower half of the side surface is almost vertical and the outer periphery of the head is A rounded resist mask 54 is formed. In order to form the resist mask 54 having such a shape, a positive resist (Tokyo, Japan) having a relatively high solubility of the unexposed part in the developing solution, such as a benzophenone-based novolak resist, has a weak insolubilization on the surface of the unexposed part. Positive resist "TSMR9200-" manufactured by Oka Kogyo Co., Ltd.
B2 ").

Next, as shown in FIG. 3, a heat treatment at about 200 ° C. is performed while irradiating the resist mask 54 with ultraviolet rays. When this process is performed, the cross-linking reaction of the polymer constituting the resist is promoted and the degree of polymerization is increased, so that the resist mask 54 is hardened.

Next, the Pt film 53 and the underlying Ti film 52 are dry-etched using a magnetron RIE etcher. It is effective that the etching conditions at this time are high vacuum, high power, and high chlorine flow rate. For example, the degree of vacuum in the chamber = 5 mTorr, RF bias = 120.
0 W (13.56 MHz), chlorine gas flow rate = 40 sccm, Ar
The gas flow rate is set to 10 sccm. Increasing the degree of vacuum in the chamber is effective for quickly evaporating the reaction product.

When the etching of the Pt film 53 starts, FIG.
As shown in (1), a part of the reaction product generated on the surface of the Pt film 53 adheres to the side surfaces of the resist mask 54 and the Pt film 53 under the resist mask 54 to form the side wall adhesion film 55.
At this time, if the head of the resist mask 54 is round, the cross-sectional shape of the side wall adhesion film 55 is such that the lower portion has a large thickness,
The upper portion has a thin forward tapered shape.

As shown in FIG. 5, in parallel with the formation of the sidewall adhesion film 55, the sidewall adhesion film 55 is removed together with the resist by chlorine ions which are high-energy etchants generated in the RIE plasma. Go. At this time, since the cross-sectional shape of the side wall adhesion film 55 is a forward taper, the shaving proceeds smoothly. In addition, since the hardening process is performed on the resist mask 54, the shaving amount due to the etchant is reduced, so that the problem that the resist mask 54 disappears before the sidewall adhesion film 55 is shaved can be prevented.

Ar ions, which are another kind of etchant generated in RIE plasma, have a lower ability to scrape resist than chlorine ions, but contribute to increase the etching rate. The flow rate ratio between chlorine and Ar has an optimum value. For example, when the flow rate of chlorine is small and the flow rate of Ar is large, the etching rate of the Pt film 53 increases, but the ability to remove the sidewall adhesion film 55 together with the resist decreases. As a result, the side wall adhesion film 55 remains. Conversely, if the flow rate of Ar is too small even if the flow rate of chlorine is large, the etching rate of the Pt film 53 will decrease, and the throughput will decrease.

Thereafter, the process shown in FIG. 4 and the process shown in FIG. 5 are repeated while the Pt film 53 and the T
The i film 52 is etched. FIG. 6 shows a state immediately after the etching of the Ti film 52 is completed and the surface of the underlying silicon oxide film 51 is exposed. At this time, the sidewall adhesion film 55 remains on the side surfaces of the resist mask 54 and the Pt film 53. After that, an appropriate amount of over-etching is performed to completely remove the side wall adhering film 55,
A Pt pattern 56 as shown in FIG. 7 is obtained. The optimal amount of overetching at this time is about 15%.

Next, the above-described etching mechanism will be described in more detail based on an experiment using a non-benzophenone-based novolak resist.

Unlike the benzophenone-based novolak resist in which the surface of the unexposed portion is weakly insoluble, the non-benzophenone-based novolak resist in which the surface of the unexposed portion is strongly insolubilized (“TSMR CR-N” manufactured by Tokyo Ohka Kogyo Co., Ltd.)
2)), a resist mask having an outer periphery of the head close to a right angle and a flat top is obtained as shown in FIG. Next, when this resist mask is subjected to an additional bake (two-time bake), its shape changes in accordance with the bake temperature (FIGS. 9B and 9C).
(D)).

For example, when additional baking is performed at 150 ° C., a forward taper of about 80 degrees is formed on the entire side surface of the resist mask. In addition, at the additional baking at 170 ° C., the root portion is almost vertical (90 degrees), but about 7
A forward taper of 5 degrees is formed. Further, the additional baking at 190 ° C. results in a hemispherical shape. In this hemispherical resist, it can be said that the root portion is almost vertical (90 degrees) and the head is 45 degrees.

Therefore, using these four types of resists, P
The t film was etched and further over-etched by 15%. As a result, in both the case without the additional baking and the case with the additional baking at 150 ° C., the side wall adhered film remained on the side surface of the Pt pattern. On the other hand, Pt patterns without side wall adhered films were obtained in each of those additionally baked at 170 ° C. and those baked at 190 ° C.

From the above experimental results, it was found that P
In order to obtain the t-pattern, it is not always necessary to use a resist having a forward taper on the entire side surface as in the related art.
It can be seen that a resist having a forward taper only at the head may be used. In other words, the angle at the base of the resist is
It can be said that there is no effect on the presence or absence of the sidewall adhesion film. When a benzophenone-based novolak resist having a weak insolubilization on the surface of the unexposed portion described above is used, a shape having the same effect as that of a resist having a forward taper on the outer peripheral portion of the head (the root portion is almost vertical, (A rounded shape) can be realized without additional baking, so that the process can be shortened as compared with the case where a non-benzophenone-based novolak resist is used.

Next, the reason why the hardening treatment is performed on the resist mask having a rounded head so that the etching of the Pt film is performed more favorably will be described with reference to the following resist mask hardening experiment.

The irradiation and heating of the ultraviolet rays are performed by FUSION SEMICONDUCTOR SYSTE
MS) using M150PT (version 2.0)
Curing was performed according to the sequence shown in FIG.

Step 1: A wafer having a resist mask formed on a Pt film (diameter = 6 inches) is heated at 115 ° C. for 15 seconds.

Step 2: Temperature higher than 115 ° C. (T
C)), the UV lamp is set to a low mode while heating is started, and ultraviolet rays are irradiated at 600 mW / cm ² for 30 seconds.

Step 3: While continuing the heating, the UV lamp is set to the high mode, and the ultraviolet light is applied at 850 mW / cm ² .
Irradiate for 0 seconds.

Step 4: When the temperature reaches T ° C., the UV lamp is turned off, and heating at T ° C. is continued for t seconds.

The resist mask was a benzophenone-based novolak resist ("TSMR9200-
B2 ") and a non-benzophenone-based novolak resist (" TSMR CR-N2 ") whose head periphery is near a right angle, and T = 140 ° C. to 220 ° C., t = 15 to 60 seconds, the Pt film was etched using a magnetron RIE etcher, and further over-etched by 15%. At this time, in order to judge the ability of the resist having a rounded head, the conditions under which the reaction product easily adheres to the side surface of the Pt pattern (the degree of vacuum in the chamber = 5 mTorr,
RF bias = 800 W, chlorine gas flow rate = 15 sccm, A
Etching was performed at an r gas flow rate of 15 sccm). The surface of the wafer is divided into ten regions as shown in FIG.
The presence or absence of the side wall adhering film in each region was observed using a cross-sectional SEM (scanning electron microscope). The results are shown in FIG. In the figure, the mark ○ indicates that there was no side wall attached film, the mark △ indicates that there was a small amount of side wall attached film, and the mark x indicates that there was a large amount of side wall attached film.

From the above experimental results, when a resist having a rounded head (“TSMR9200-B2”) is used,
It was found that the higher the heating temperature (T) and the longer the heating time (t), the more the area without the sidewall adhesion film. That is, in order to eliminate the side wall adhesion film, it is advantageous that the heating temperature (T) is higher and the heating time (t) is longer. However, if the heating temperature (T) exceeds 220 ° C., the resist is burned and denatured, so that the temperature cannot be raised any higher. From another experiment, it was found that, even when the heating temperature (T) was in the range of 200 ° C. to 220 ° C., if the heating time (t) exceeded 15 seconds, the resist was burned and denatured. Therefore, in order to eliminate the side wall adhering film, the heating temperature (T) = 200 ° C. to 220 ° C. and the heating time (t) = 15 seconds are optimal.

As is apparent from the figure, when a non-benzophenone-based novolak resist resist (“TSMR CR-N2”) whose head periphery is nearly right-angled is used, even if the heating temperature (T) is increased. Even if the heating time (t) was lengthened, the side wall adhered film could not be eliminated. However, from another experiment, after exposing and developing this non-benzophenone-based novolak resist, if additional baking was performed to form a taper only on the head, almost the same result as a resist with a rounded head was obtained. .

FIG. 1 shows the difference between the Pt pattern when using a resist mask having a rounded head and the case when using a resist mask having a taper of about 75 degrees over the entire side surface.
1 will be described.

First, a resist mask (A
In the case where 1) is used, as described above, when the etching of the Pt film starts, the resist mask (and the Pt under the resist mask) is used.
A side-adhesion film having a forward taper is formed on the side surface of the film (A).
2). Therefore, even if the etching proceeds, the developed size of the resist mask and the shape near the root do not change (A3). During the progress of the etching, the sidewall-adhering film and the resist are scraped off by the chlorine ions near the upper portion of the sidewall-adhering film. Further, the surface of the tapered portion of the side wall adhesion film is also scraped off by an etchant such as chlorine ions. When the Ti film under the Pt film is etched (just etching), the sidewall adhesion film remains. However, by performing an appropriate amount of over-etching, a Pt pattern without the sidewall adhesion film is formed. Obtained (A4). At this time, since the cross-sectional shape of the side wall adhering film has a forward tapered shape, the shaving proceeds smoothly. The dimension of the uppermost part of the obtained Pt pattern is not different from the developed dimension of the resist mask, but the dimension of the lowermost part is slightly larger than the developed dimension of the resist mask because a taper is formed on the side surface.

On the other hand, when a resist mask (B1) having a taper of 75 degrees on the entire side surface is used, the speed at which the reaction product is removed by the etchant is higher than the speed at which the reaction product adheres to the side surface of the resist mask. Therefore, no sidewall adhesion film is formed (B2). Therefore, as the etching proceeds, not only the upper part but also the side surfaces of the resist mask are cut. Along with this, a taper is also formed on the side surface of the Pt pattern (B3). As a result, at the end of the etching, the uppermost dimension of the Pt pattern becomes smaller than the developed dimension of the resist mask, and the lowermost dimension becomes larger than the developed dimension. A large angle taper is formed on the side surface of the Pt pattern (B
4).

As described above, when a resist mask having a rounded head is used and when a resist mask having a taper of about 75 degrees is formed on the entire side surface, a taper is formed on the side surface of the Pt pattern. However, when a resist mask having a taper formed on the entire side surface is used, a taper having a larger angle is formed, so that it becomes difficult to obtain a desired size when the pattern size becomes fine. Therefore,
In order to form a fine Pt pattern with high dimensional accuracy, a resist mask having a rounded head (or a resist mask having a forward taper only in the head) is used rather than a resist mask having a tapered entire side surface. ) Is better.

Next, a DRAM which is a kind of semiconductor memory
The manufacturing method of the present embodiment applied to the manufacturing method of FIG.
This will be described with reference to FIGS.

FIG. 12 is a plan view showing a layout of a memory cell of a DRAM. The memory cell of this DRAM employs a two-intersection cell and a COB (Capacitor Over Bitline) structure in which an information storage capacitor is arranged above a bit line. The transistor (memory cell selection MISFET) of each memory cell is connected to a peripheral circuit via a bit line BL. The bit line BL is connected to the semiconductor region 8 of the memory cell selecting MISFET through the connection hole 14.
(Source region, drain region). The operation of the memory cell selection MISFET is controlled by the word line WL (gate electrode 6). This word line WL (gate electrode 6) is connected to a peripheral circuit.
Information storage capacitive element C arranged above bit line BL
Is a MISFET for selecting a memory cell through the connection hole 13.
Of the semiconductor region 8 (source region, drain region). The information storage capacitor C is connected to a peripheral circuit via the plate electrode 26.

The first feature of this planar layout is that one plate electrode 26 is arranged for two word lines WL. With such a layout, the capacitance of the plate electrode 26 can be made smaller than that of a normal DRAM, so that the potential of the plate electrode 26 can be easily controlled by a peripheral circuit. The number of plate electrodes 26 may be one for one word line WL,
One word line may be provided for three word lines WL. However, when the number of plate electrodes 26 with respect to the word line WL increases, it becomes difficult to increase the degree of integration. Conversely, when the number decreases, the capacitance of the plate electrodes 26 increases, and control by peripheral circuits becomes difficult. The number of plate electrodes 26 is D
The optimum number varies depending on the use of the RAM.

A second feature of this planar layout is that the plate electrode 26 extends in the same direction as the word line WL (gate electrode 6). Thereby, the plate electrode 2
When the peripheral circuit controls the potential of No. 6, the potential can be controlled in synchronization with the potential of the word line WL.

In order to manufacture the memory cell of this DRAM, first, FIG. 13 (a cross-sectional view taken along line AA 'of FIG. 12)
As shown in, p ^- and a semiconductor substrate 1 made of the type of single crystal silicon, after forming a field oxide film 2 by selective oxidation (LOCOS) method on the surface, the semiconductor substrate 1 p
The p-type well 3 is formed by ion-implanting the type impurity (B). Subsequently, after the p-type impurity (B) is ion-implanted into the p-type well 2 to form the p-type channel stopper layer 4, the surface of the active region of the p-type well 3 surrounded by the field oxide film 2 is thermally oxidized. A gate oxide film 5 is formed by a method.

Next, as shown in FIG. 14, the gate electrode 6 (word line WL) of the memory cell selecting MISFET is formed. The gate electrode 6 (word line WL) is formed, for example, by depositing a polycrystalline silicon film on the semiconductor substrate 1 by a CVD method, then depositing a TiN film and a W film by a sputtering method, and further a silicon nitride film serving as a cap insulating film. 7 are deposited by a plasma CVD method, and these films are patterned and formed by etching using a photoresist as a mask.
The polycrystalline silicon film forming a part of the gate electrode 6 (word line WL) is doped with an n-type impurity (P) in order to reduce its resistance. Here, the resist used for forming the gate electrode 6 (word line WL) is a non-benzophenone-based novolak resist in which the periphery of the head is near a right angle.

Next, as shown in FIG.
Is implanted with an n-type impurity (P) to form n-type semiconductor regions 8, 8 (source region, drain region) of the memory cell selecting MISFET in the p-type well 2 on both sides of the gate electrode 6 (word line WL). After that, as shown in FIG. 16, a sidewall spacer 9 is formed on the side surface of the gate electrode 6 (word line WL). The sidewall spacer 9 is formed by processing a silicon nitride film deposited by plasma CVD on the gate electrode 6 (word line WL) by anisotropic etching.

Next, as shown in FIG. 17, a silicon oxide film 1 is formed on the memory cell selecting MISFET by the CVD method.
0 and a BPSG (Boron-doped Phospho Silicate Glass) film 11 are deposited, and then a chemical mechanical polishing (Chemical Mechanic) is performed.
The BPSG film 11 is polished by a mechanical polishing (CMP) method to flatten its surface.

Next, as shown in FIG.
After depositing a polycrystalline silicon film 12 on the substrate 1 by a CVD method,
Using a non-benzophenone-based novolak resist as a mask, the periphery of the head of which is close to a right angle as a mask,
By etching the G film 11, the silicon oxide film 10, and the gate oxide film 5, the memory cell selecting MISF
A connection hole 13 is formed above one (n-type semiconductor region 8) of the source region and the drain region of the ET, and a connection hole 14 is formed above the other (n-type semiconductor region 8). At this time, the silicon nitride film 7 formed on the gate electrode 6 (word line WL) of the memory cell selection MISFET and the silicon nitride sidewall spacer 9 formed on the side surface are:
Since they are only slightly etched, the connection holes 13, 1
The connection holes 13 and 14 having a fine diameter can be formed in a self-aligned manner (self-alignment) without providing a margin for aligning the gate electrode 4 with the gate electrode 6 (word line WL).

Next, as shown in FIG.
A plug 15 of polycrystalline silicon is buried in the inside of the substrate.
The plug 15 is formed by depositing a polycrystalline silicon film on the polycrystalline silicon film 12 by a CVD method and removing the polycrystalline silicon film and the polycrystalline silicon film 12 by etch-back. The polycrystalline silicon film forming the plug 15 is doped with an n-type impurity (P). The plug 15 may be formed by embedding, for example, TiN, W, Ti, Ta, or the like, in addition to polycrystalline silicon.

Next, as shown in FIG.
After the silicon oxide film 16 is deposited on the upper portion of the substrate 1 by the CVD method, and then, the silicon oxide film 16 above the connection hole 14 is removed by etching using a non-benzophenone-based novolak resist having a substantially right-angled periphery as a mask. As shown in FIG. 21, a bit line BL is formed above the connection hole 14.
The bit line BL is formed by depositing a TiN film and a W film on the silicon oxide film 16 by a sputtering method and further depositing a silicon nitride film 17 serving as a cap insulating film by a plasma CVD method. These films are patterned and formed by etching using a non-benzophenone-based novolak resist near a right angle as a mask.

Next, as shown in FIG.
Is formed on the side surface of the substrate. The sidewall spacer 18 is formed by processing a silicon nitride film deposited on the bit line BL by a plasma CVD method by anisotropic etching.

Next, as shown in FIG.
BPSG film 19 having a thickness of about 300 nm by CVD
Is deposited and reflowed. Then, using a non-benzophenone-based novolak resist as a mask, the periphery of the head of which is near a right angle is used as a mask.
By etching the PSG film 19 and the silicon oxide film 16, a connection hole 20 is formed on the connection hole 13 formed on the other of the source region and the drain region (the n-type semiconductor region 8) of the memory cell selection MISFET Qt. To form At this time, since the silicon nitride film 17 above the bit line BL and the side wall spacers 18 on the side surfaces serve as etching stoppers, the connection holes 20 are formed by self-alignment (self-alignment) similarly to the connection holes 13 and 14. You.

Next, as shown in FIG. 24, a plug 21 is embedded in the connection hole 20. Plug 21 is BPSG
On top of the film 19, for example, a TiN film and W
After depositing the films, these films are formed by etching back. The plug 21 is made of polycrystalline silicon, TiN, W, T
It can also be formed by embedding i, Ta, or the like.

Next, an information storage capacitor is formed above the plug 21. To form an information storage capacitor,
First, as shown in FIG. 25, after depositing a barrier metal 22 on the BPSG film 19 by a sputtering method or the like, a Pt film 23a having a thickness of about 175 nm is deposited on the barrier metal 22 by a sputtering method. Although the barrier metal 22 is not always necessary, it is effective for suppressing the diffusion of the lower electrode material (Pt) of the information storage capacitor. The barrier metal 22 is made of TiN, Ti, or the like, and has a thickness of about 20 nm.

Next, as shown in FIG. 26, the Pt film 23a
After depositing the capacitance insulating film 24 of the information storage capacitor, a Pt film 25a, which is the upper electrode material of the information storage capacitor, is deposited on the capacitor insulation film 24. The capacitor insulating film 24 is formed by depositing PZT, which is a ferroelectric material, by a sputtering method, and has a thickness of about 250 nm. The Pt film 25a is deposited by a sputtering method, and has a thickness of about 100 nm.
Depending on the material of the capacitor insulating film 24, a crystallization heat treatment is performed as necessary after the film formation.

In this embodiment, Pt is used as the electrode material of the information storage capacitance element, and Pt is used as the capacitance insulation film material.
The case where ZTBST is used will be described, but the present invention is not limited thereto.

In consideration of application to a nonvolatile RAM or the like, in addition to Pt, Ir, IrO ₂ , R
h, RhO ₂ , Os, OsO ₂ , Ru, RuO ₂ , R
e, ReO ₃ , Pd, Au or a laminated film of these can be used. MOCV for RuO ₂ and IrO ₂
By depositing using the D method, a thin film having good coverage can be formed. Further, by stacking Ru, Ir, or the like having a high barrier property against oxygen on the upper portion, the oxidation resistance of the film can be improved. Furthermore, if oxidation at the interface of the capacitive insulating film can be suppressed, W, Al, TiN, Ta, C
u, Ag, or a stacked film of these materials can also be used.

As the material of the capacitive insulating film, in addition to PZT, CV
Ta ₂ O ₅ deposited by the method D, silicon oxide, silicon nitride, or the like may be used. Various ferroelectric materials,
For example, PbZrO ₃ , LiNbO ₃ , Bi4 Ti
₃ O ₁₂ , BaMgF ₄ , PLZT, BST ((Ba, S
r) TiO ₄ ), Y ₁ type (SrBi ₂ (Nb, Ta) ₂ O ₉ )
Etc. can also be used. These ferroelectric materials can be deposited by a sputtering method, an MOCVD method, a sol-gel method, a laser ablation method, or the like.

Next, as shown in FIG. 27, a benzophenone-based novolak resist is spin-coated on the Pt film 25a, which is the upper electrode material, and is exposed and developed to form a resist whose head has a rounded outer periphery. After forming the mask 27, the resist mask 27 is cured by heating to about 200 ° C. while irradiating the resist mask 27 with ultraviolet rays.

Alternatively, a non-benzophenone-based novolak resist is exposed and developed to form a resist mask in which the outer periphery of the head is close to a right angle, and the resist mask is subjected to additional baking (bake twice) to taper only the head. After being formed, the film may be cured by heating while being irradiated with ultraviolet rays.

Next, as shown in FIG. 28, using a magnetron RIE etcher, the Pt film 25a, the capacitor insulating film 24, and the Pt film 25 in the region not covered with the resist mask 27 are formed.
The Pt film 23a is formed on the barrier metal 22 by successively dry-etching the film 23a and the barrier metal 22.
Electrode 23 composed of a PZT film and a lower electrode 23 composed of a PZT film
4 and an upper electrode 25 made of a Pt film 25a to form an information storage capacitance element (capacitor) C.

The Pt film 25a, the capacitance insulating film 24 and the Pt
The etching of the film 23a may be performed individually using different resist masks. In this case, the resist mask 2
After the upper electrode 25 is formed by dry-etching the Pt film 25a using
7 is removed by ashing, and then a benzophenone-based novolak resist is spin-coated, exposed and developed to form a second resist mask having a rounded outer peripheral portion of the head. To cure.

Next, after the capacitive insulating film 24 is dry-etched using the second resist mask, the resist mask is removed by ashing, and then a benzophenone-based novolak resist is spin-coated, exposed and developed.
After forming a third resist mask having a rounded outer peripheral portion of the head, the resist mask is cured by the above-described method. Next, a Pt film 23a is formed using a third resist mask.
After the lower electrode 23 is formed by dry-etching the gate electrode and the barrier metal 22, the resist mask is removed by ashing.

Thereafter, the resist film 27 and the side wall adhesion film 5 remaining on the side surfaces of the information storage capacitance element (capacitor) C are formed.
Then, over-etching for removing 5 is performed.

FIG. 29 shows a capacitor insulating film 24 made of PZT.
It is a graph which shows the intensity change of plasma light at the time of etching the upper Pt film 25a (film thickness 100 nm). 0 on the horizontal axis
~t ₁ The time Pt film 25a are etched, t
₁ ~t ₂ is the time required from when the capacitor insulating film 24 of the base begins to expose to expose the entire surface (Pt film 25a has completely disappeared), t ₂ ~t ₃ is a time required for the over-etching.

Here, the time t ₂ is the just etching time, the time t _{3 to} t ₂ (= tOE) is the over etching time,
When the time t ₃ is defined as the total etching time, appropriate over-etching time (tOE) is a time corresponding to 15% of _{t 2 (t 2 × 0.15)} . That is, the just etching time (t) of the 100 nm thick Pt film 25a is
_{If 2} ) is, for example, 52 seconds, the over-etching time (tOE) is set to 52 × 0.15 = 7.8 seconds. In this case, the total etching time (t ₃ ) is 52 + 7.8 = 59.8 seconds.

FIG. 30 is a graph showing a change in intensity of plasma light (wavelength 406 nm) when a capacitance insulating film (PZT film) 24 (film thickness 250 nm) on the Pt film 23a is etched. Capacitive insulating film suitable over-etching time of 24 (tOE) is the time corresponding to 10% of the t ₂ (t ₂ × 0.
1). That is, the capacitive insulating film 24 having a thickness of 250 nm
If the just etching time (t ₂ ) is 54 seconds, for example, the over etching time (t OE) is 54 × 0.1 =
5.4 seconds. In this case, the total etching time (t
₃ ) is 54 + 5.4 = 59.4 seconds.

FIG. 31 shows the Pt film 23 on the BPSG film 19.
6 is a graph showing a change in intensity of plasma light when a (film thickness: 175 nm) is etched. 0 to t ₁ on the horizontal axis time Pt film 23a are etched, t ₁ ~t ₂ in the barrier metal 22 of the base begins to expose to expose the entire surface (Pt film 23a has completely disappeared) The required time (just etching time), t _{2 to} t _3, is the time required for over-etching. At this time, the Pt film 23a
If the just etching time (t ₂ ) is, for example, 71 seconds, the over-etching time (tOE) is 71 × 0.15.
= 10.6 seconds. In this case, the total etching time (t ₃ ) is 71 + 10.6 = 81.6 seconds.

Next, after the resist mask 27 remaining on the information storage capacitive element C is removed by ashing, FIG.
As shown in FIG. 2, a BPSG film 28 which is a reflowable insulating film is deposited to protect the information storage capacitive element C,
The surface is flattened by a chemical mechanical polishing (CMP) method to expose the surface of the upper electrode 25. In this case, complete flattening is not essential, but it is desirable to flatten the BPSG film 28 as much as possible in order to increase the reliability of the wiring formed thereon in a later step. In order to enhance the protection effect of the information storage capacitor C, the information storage capacitor C
The BPSG film 28 may be deposited after depositing a thin film made of an oxide such as Ti, Sr, or Ba that is compatible with the constituent material described above. Further, instead of the BPSG film 28, a CVD / silicon oxide film using an organic Si gas may be used, or an organic insulator such as a polyimide resin may be used. The planarization of the insulating film may be performed by an etch-back method instead of the CMP method, or may not be particularly performed when a step due to the information storage capacitor C is small.

Next, as shown in FIG.
8, a plate electrode 26 common to a plurality of memory cells
To form Various conductive materials used in the conventional silicon LSI process, such as a polycrystalline silicon film and a W film, can be used as the plate electrode material. When the base is sufficiently flat, a conductive material which can be formed by a sputtering method is used. When the base has a step, a conductive material which can be formed by a CVD method is used.

By the above steps, the DRA of the present embodiment
M memory cells are substantially completed. In an actual DRAM, it is necessary to form about two more layers of wiring above the plate electrode 26 to connect the memory cells and peripheral circuits, and to package the semiconductor substrate 1 with a resin or the like. Needless to say.

(Embodiment 2) FIG. 34 is a plan view showing a layout of a memory cell of a DRAM according to the present embodiment. The memory cell of this DRAM employs a two-intersection cell and a COB structure in which an information storage capacitor is arranged above a bit line. The transistor (memory cell selection MISFET) of each memory cell is connected to a peripheral circuit via a bit line BL. The bit line BL is connected to the connection hole 1
4 is connected to one of the semiconductor regions 8 (source region, drain region) of the memory cell selection MISFET. The operation of the memory cell selection MISFET is controlled by the word line WL (gate electrode 6). This word line WL (gate electrode 6) is connected to a peripheral circuit.
Information storage capacitive element C arranged above bit line BL
Is a MISFET for selecting a memory cell through the connection hole 13.
Of the semiconductor region 8 (source region, drain region). The information storage capacitor C is connected to a peripheral circuit via the plate electrode 26.

The first feature of this planar layout is that one plate electrode 26 is arranged for one bit line BL. With such a layout, the capacitance of the plate electrode 26 can be made smaller than that of a normal DRAM, so that the potential of the plate electrode 26 can be easily controlled by a peripheral circuit. The number of plate electrodes 26 may be one for two or more bit lines BL. However, when the number of the plate electrodes 26 with respect to the bit lines BL is reduced, the capacitance of the plate electrodes 26 is increased, and it becomes difficult to control the peripheral circuits.
The optimal number of the plate electrodes 26 varies depending on the use of the DRAM.

The second feature of this planar layout is that plate electrode 26 extends in the same direction as bit line BL. Thus, when the potential of the plate electrode 26 is controlled by the peripheral circuit, the potential can be controlled in synchronization with the potential of the bit line BL.

The memory cell of the DRAM of this embodiment is also
It can be manufactured by the same method as in the first embodiment.

(Embodiment 3) FIG. 35 is a plan view showing a layout of a memory cell of a DRAM of this embodiment.

The feature of this planar layout is that one plate electrode 26 having an increased area allows the information storage capacitor C to be used.
Is to control. With such a layout, it becomes easy to apply the reference potential required for the DRAM operation to the information storage capacitor C. If the driving capability of the peripheral circuit is sufficiently increased, the operation as a nonvolatile RAM is also possible. The number of information storage capacitive elements C controlled by the plate electrode 26 may be adjusted according to the use of the memory.

FIG. 36 is a sectional view taken along the line AA 'of FIG. The structure and manufacturing method of the DRAM memory cell of the present embodiment are the same as those of the first embodiment except that the plate electrode 26 is omitted.
This is basically the same as the memory cell of the DRAM of the first embodiment. The processing of the plate electrode 26 is performed in the first embodiment.
And the size may be adjusted to the required size.

(Embodiment 4) The structure of a memory cell of this embodiment will be described with reference to FIG. The figure shows
FIG. 3 is a cross-sectional view showing a stage in which a capacitor of a one-transistor one-capacitor type memory is formed. PZT which is a ferroelectric material is used for the capacitor insulating film 24 of the capacitor, and Pt is used for the lower electrode 23 and the upper electrode 25 of the capacitor.

In this memory, transistors are electrically separated by a field oxide film 2 on a semiconductor substrate 1.
The transistor is a MISFET including a semiconductor region 8 (source region and drain region), a gate electrode 6 of polycrystalline silicon, and a gate oxide film 5 thereunder. After the upper portion of the MISFET is planarized using the BPSG film 11, a capacitor is formed. Capacitors and MISFE
T is electrically connected to a polycrystalline silicon plug 15 embedded in a part of the BPSG film 11. The capacitor is a three-dimensional capacitor formed on the lower electrode 23 of Pt. A capacitor insulating film 24 of PZT is formed on the lower electrode 23, and an upper electrode 25 of Pt is formed on the capacitor insulating film 24. To form a three-dimensional capacitor. Further, in order to suppress the diffusion of Pt from the lower electrode 23 into the plug 15, a T
An iN barrier metal 22 is provided.

In order to actually operate as a memory,
In addition to those shown in this figure, wiring (usually about two layers of wiring are required above the upper electrode 25) and peripheral circuits for controlling the memory operation and exchanging signals with the outside are required. However, these are well-known structures and are not directly related to the present embodiment, so description thereof will be omitted.

The capacitor of the present embodiment can be formed by the same method as in the first embodiment.

(Embodiment 5) A method of manufacturing a memory cell according to the present embodiment will be described with reference to FIG.

In this embodiment, after the lower electrode 23 is formed, a flattening process using the BPSG film 28 is performed, and thereafter, the capacitive insulating film 24 of PZT and the upper electrode 25 of Pt are formed. Otherwise, it is the same as the manufacturing method of the fourth embodiment. Such a three-dimensional capacitor can also be manufactured according to the manufacturing method of the first embodiment.

(Embodiment 6) Both the benzophenone-based novolak resist and the non-benzophenone-based novolak resist described above can be applied to the outer periphery of the head of the resist pattern by controlling the focus condition of the exposure light during the exposure of the photoresist. A forward taper or roundness can be formed. In the present embodiment, “TSMR9200
Using “-B2” (benzophenone-based novolak resist) and “TSMR CR-N2” (non-benzophenone-based novolak resist), exposure is performed under the following exposure conditions, thereby forming a roundness on the outer periphery of the head of the resist pattern. did.

The reduction projection exposure apparatus is “FPA” manufactured by Canon.
1550M3 ”, the coater and the developer use Hitachi“ PHOTO MAX1600 ”, respectively.
Exposure time 60 seconds, post exposure bake (PEB) 110 ° C
After performing exposure while changing the focus offset under an exposure condition of / 120 seconds, development was performed using a developing solution "NMD-3 / 2.38%", and the results shown in FIG. 39 were obtained. Here, the focus offset corresponds to an operation of changing the distance from a point at which the best focus can be obtained when the distance between the lens and the wafer is set to 0, which changes the focus. The cross-sectional shape can be changed.

As shown in the figure, “TSMR9200-B
In the case of “2”, the head of the resist pattern was rounded under any focus condition, but the focus offset was ± 0 to ± 0.
When the angle is +1.0 μm, the root angle of the resist pattern is 9
The temperature was close to 0 ° C., and the shape was most suitable for fine processing.
In the case of “TSMR CR-N2”, the head of the resist pattern was rounded when the focus offset was −1.5 μm or less.

The above-mentioned method is applicable not only to benzophenone-based novolak resists and non-benzophenone-based novolak resists, but also to chemically amplified resists (for example, polyhydroxystyrene; PHS), Ar
The present invention can be applied to a case where a resist pattern mainly composed of an alicyclic ring, which is exposed by an F excimer laser, is used to form a rounded or forward tapered head portion of a resist pattern.

(Embodiment 7) The positive type chemically amplified resist can be formed with a rounded top portion of the resist pattern by using the following method.

First, as shown in FIG.
After a silicon oxide film 51 is formed thereon, a Ti film 52 is deposited thereon as a barrier metal, and a Pt film 53 is further deposited thereon.

Next, as shown in FIG. 41, a positive-type chemically amplified resist (for example, PHS) spin-coated on the Pt film 53 is exposed and developed to form a resist mask 54 whose outer peripheral portion of the head is almost perpendicular. To form

Next, when the resist mask 54 is irradiated with short-wavelength light, for example, ultraviolet light (deep UV) having a wavelength of about 200 nm, the ultraviolet light is absorbed only on the surface of the resist mask 54 as shown in FIG. Only the area dissolves.

Next, as shown in FIG. 43, by spin-coating the surface of the resist mask 54 with an acidic polymer and then performing a baking process, the head of the resist mask 54 is rounded.

On the other hand, in the case of a negative-type chemically amplified resist such as a three-component negative-type chemically amplified resist comprising a novolak resin, an acid generator and a cross-linking agent such as hexamethylolmelamine, a developing solution using an alkaline aqueous solution is used. After forming the negative pattern, the resist mask is exposed to X-rays, so that a rounded portion is formed on the head of the resist mask.

(Embodiment 8) In the above-mentioned novolak resist or chemically amplified resist, a forward taper can be formed only at the head of the pattern by performing light etching as pretreatment etching after forming the resist pattern.

In this case, as shown in FIG. 44, after a silicon oxide film 51 is formed on a semiconductor substrate 50, a Ti film 52 is deposited thereon as a barrier metal, and a Pt film 53 is further formed thereon. accumulate.

Next, as shown in FIG. 45, for example, a non-benzophenone-based novolak resist is spin-coated on the Pt film 53, and then a normal exposure and development are performed to form a resist mask whose outer peripheral portion of the head is close to a right angle. 54 are formed.

Next, as shown in FIG. 46, prior to the etching of the Pt film 53, only the surface of the resist mask 54 is lightly etched. The etching apparatus uses, for example, an RIE etcher. The etching conditions are, for example, the degree of vacuum in the chamber = 30 mTorr, RF power = 100 W, O ₂ (or CF ₄ ) gas flow rate = 100 sccm, etching time =
20 seconds. In such low power etching, P
The t film 53 is not etched, only the surface of the resist mask 54 is etched, and further, the abrasion proceeds in a diagonal direction from the corner of the head of the resist mask 54. Therefore, by shortening the etching time to several tens of seconds,
As shown in FIG. 47, a forward taper can be formed only at the head of the resist mask 54. The etching apparatus for performing this light etching may be of any type as long as it is a plasma etcher, for example, a barrel type etcher.

(Embodiment 9) For example, when the design rule is 0.2
When an ultrafine pattern of less than μm is formed, a methacrylic acid-based resist to which a hydrocarbon group containing an alicyclic ring such as adamantane is added to improve etching resistance, or a resist for direct writing of electron beam (EB) (novolak resist) Alternatively, a chemically amplified resist such as PHS) is used. In the case of a methacrylic acid-based resist, the use of a negative-type resist makes it possible to form roundness on the head of the resist mask. In the case of electron beam resist,
By controlling the electron beam exposure,
Roundness can be formed at the head of the resist mask.

As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the gist of the invention. It goes without saying that it is possible.

The etching method of the present invention is not limited to etching using a magnetron RIE type plasma etching apparatus, but includes ECR, helicon, and IC.
The present invention can be applied to etching using various types of plasma etching apparatuses such as P and TCP.

[0135]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the manufacturing method of the present invention, when dry etching a thin film deposited on a semiconductor substrate, it is possible to reliably prevent a reaction product having a low vapor pressure from adhering to the side surface of the pattern. As a result, the production yield of the semiconductor integrated circuit device can be improved. Also, since a fine thin film pattern can be formed with high dimensional accuracy,
Miniaturization of a semiconductor integrated circuit device can be promoted.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a principal part of a semiconductor substrate showing a dry etching method for a Pt film according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of a main part of the semiconductor substrate, illustrating a dry etching method of the Pt film according to the first embodiment of the present invention;

FIG. 3 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for dry-etching the Pt film according to the first embodiment of the present invention;

FIG. 4 is a cross-sectional view of a principal part of the semiconductor substrate, illustrating a dry etching method of the Pt film according to the first embodiment of the present invention;

FIG. 5 is a cross-sectional view of a principal part of the semiconductor substrate, illustrating a Pt film dry etching method according to the first embodiment of the present invention;

FIG. 6 is a cross-sectional view of a principal part of the semiconductor substrate, illustrating a dry etching method of the Pt film according to the first embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for dry-etching the Pt film according to the first embodiment of the present invention;

FIG. 8 is an explanatory diagram showing a relationship between a shape of a resist mask and an amount of a reaction product attached to a side surface of a Pt pattern.

FIG. 9A is a flowchart showing a sequence of ultraviolet irradiation and heating, and FIG. 9B is a plan view of a wafer displaying an area for confirming the presence or absence of a side surface deposited film.

FIG. 10 is an explanatory diagram showing a relationship between a curing process of a resist mask and an amount of a reaction product attached to a side surface of a Pt pattern.

FIG. 11 is an explanatory diagram showing a relationship between a shape of a resist mask and a Pt pattern dimension.

FIG. 12 is a plan view showing a layout of the DRAM according to the first embodiment of the present invention;

FIG. 13 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 14 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 15 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 16 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 17 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 18 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 19 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 20 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 21 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 22 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 23 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 24 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 25 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 26 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 27 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 28 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 29 is a graph showing a change in intensity of plasma light when a Pt film on a PZT film is etched.

FIG. 30 is a graph showing a change in plasma light intensity when a PZT film on a Pt film is etched.

FIG. 31 is a graph showing a change in plasma light intensity when a Pt film on a BPSG film is etched.

FIG. 32 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 33 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 34 is a plan view showing a layout of the DRAM according to the second embodiment of the present invention;

FIG. 35 is a plan view showing a layout of a DRAM according to a third embodiment of the present invention;

FIG. 36 is a sectional view taken along the line A-A ′ in FIG. 35;

FIG. 37 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the memory cell according to Embodiment 4 of the present invention;

FIG. 38 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the memory cell according to Embodiment 5 of the present invention;

FIG. 39 is an explanatory diagram showing a relationship between focus control and a resist cross-sectional shape according to the sixth embodiment of the present invention.

FIG. 40 is an essential part cross sectional view of the semiconductor substrate, showing the method of forming the resist pattern according to the seventh embodiment of the present invention.

FIG. 41 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of forming a resist pattern according to Embodiment 7 of the present invention;

FIG. 42 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of forming a resist pattern according to Embodiment 7 of the present invention;

FIG. 43 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for forming the resist pattern according to the seventh embodiment of the present invention;

FIG. 44 is an essential part cross sectional view of the semiconductor substrate, showing the method of forming the resist pattern according to the eighth embodiment of the present invention;

FIG. 45 is an essential part cross sectional view of the semiconductor substrate, showing the method of forming the resist pattern according to the eighth embodiment of the present invention.

FIG. 46 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method of forming the resist pattern according to the eighth embodiment of the present invention;

FIG. 47 is an essential part cross sectional view of the semiconductor substrate, showing the method of forming the resist pattern according to the eighth embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 field oxide film 3 p-type well 4 p-type channel stopper layer 5 gate oxide film 6 gate electrode 7 silicon nitride film 8 semiconductor region (source region, drain region) 9 sidewall spacer 10 silicon oxide film 11 BPSG film 12 Polycrystalline silicon film 13 Connection hole 14 Connection hole 15 Plug 16 Silicon oxide film 17 Silicon nitride film 18 Side wall spacer 19 BPSG film 20 Connection hole 21 Plug 22 Barrier metal 23 Lower electrode 23a Pt film 24 Capacitive insulating film 25 Upper electrode 25a Pt Film 26 Plate electrode 27 Resist mask 28 BPSG film 50 Semiconductor substrate 51 Silicon oxide film 52 Ti film 53 Pt film 54 Resist mask 55 Side wall adhesion film 56 Pt pattern C Information storage capacitor (capacitor) BL Tsu door line WL word line

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 27/04 H01L 27/04 C 21/822 27/10 451 (72) Inventor Jun Abe 5-chome, Josuihoncho, Kodaira-shi, Tokyo No. 20 No. 1 Semiconductor Division, Hitachi, Ltd. 280 Hitachi Central Research Laboratory, Ltd.

Claims (29)

[Claims] 1. A thin film comprising one or more films including a film which is likely to cause side wall adhesion formed directly or indirectly on a first main surface of a wafer, wherein at least a lower half of the side surface is substantially vertical. Using a photoresist of a predetermined pattern having a forward taper or roundness on the outer periphery of the head as a mask,
A method for manufacturing a semiconductor integrated circuit device, comprising a step of patterning by dry etching so that a forward taper reaching the lower end of a side surface of a thin film pattern is formed. 2. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein after forming the thin film pattern, overetching is further performed to remove a sidewall adhesion film remaining on a side surface of the thin film pattern. A method for manufacturing a semiconductor integrated circuit device, comprising: 3. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein said thin film includes a platinum thin film. 4. The method for manufacturing a semiconductor integrated circuit device according to claim 3, wherein said thin film includes a high dielectric thin film or a ferroelectric thin film. 5. A method for manufacturing a semiconductor integrated circuit device, comprising the following steps. (A) a step of directly or indirectly forming a thin film composed of a single film or a plurality of films including a film that easily causes side wall adhesion on a first main surface of a wafer; A step of directly or indirectly forming a predetermined pattern of photoresist having a half side surface substantially vertical and having a forward taper or roundness on the outer periphery of the head, (c) using the photoresist of the predetermined pattern as a mask, Patterning the thin film by dry etching such that a forward taper reaching the lower end is formed on the side surface of the thin film pattern. 6. The method for manufacturing a semiconductor integrated circuit device according to claim 5, wherein after forming the thin film pattern, overetching is further performed to remove a sidewall adhesion film remaining on a side surface of the thin film pattern. A method for manufacturing a semiconductor integrated circuit device, comprising: 7. The method for manufacturing a semiconductor integrated circuit device according to claim 5, wherein said thin film includes a platinum thin film. 8. The method for manufacturing a semiconductor integrated circuit device according to claim 7, wherein said thin film includes a high dielectric thin film or a ferroelectric thin film. 9. A step of (a) directly or indirectly forming a thin film composed of one or more films including a film that easily causes side wall adhesion on a first main surface of a wafer; and (b) forming a thin film on the first main surface of the wafer. Directly or indirectly spin-coating a positive benzophenone-based novolak resist, (c) exposing and developing the positive benzophenone-based novolak resist to form a predetermined resist pattern, and (d) forming at least the resist pattern. Heating and irradiating the surface with ultraviolet rays to cure the resist pattern; (e) using the cured resist pattern as a mask, forming the thin film on a side surface of the thin film pattern by a forward taper reaching the lower end thereof; Patterning by dry etching such that a thin film pattern is formed. Removing the side wall adhered film remaining on the side surface of the thin film pattern by further performing over-etching, and when the step (d) is completed, the outer peripheral portion of the head of the resist pattern is rounded. A method of manufacturing a semiconductor integrated circuit device, comprising: weakening surface insolubilization of an unexposed portion during development of the positive benzophenone-based novolak resist. 10. The method for manufacturing a semiconductor integrated circuit device according to claim 9, wherein said thin film includes a platinum thin film. 11. The method for manufacturing a semiconductor integrated circuit device according to claim 10, wherein said thin film includes a high dielectric thin film or a ferroelectric thin film. 12. A method of manufacturing a semiconductor integrated circuit device, in which a plurality of thin films are patterned by repeating photolithography processing by reduced projection exposure using a positive or negative photoresist and exposure light having substantially the same wavelength. In some steps of the photolithography process,
Using the positive type or negative type first photoresist, in some other steps or substantially all other steps, the first photoresist and the positive, the negative type is the same And a method of manufacturing a semiconductor integrated circuit device using a second photoresist having a different pattern shape characteristic. 13. The method of manufacturing a semiconductor integrated circuit device according to claim 12, wherein said first photoresist is a positive benzophenone novolak resist, and said second photoresist is a positive non-benzophenone novolak resist. A method for manufacturing a semiconductor integrated circuit device, which is a resist. 14. The method for manufacturing a semiconductor integrated circuit device according to claim 13, wherein a single or a plurality of films including a film which is liable to adhere to a side wall by using a resist pattern made of the first photoresist as a mask. A method for manufacturing a semiconductor integrated circuit device, characterized by patterning a thin film made of: 15. The method for manufacturing a semiconductor integrated circuit device according to claim 13, wherein after patterning the thin film,
A method of manufacturing a semiconductor integrated circuit device, further comprising performing over-etching to remove a sidewall adhesion film remaining on a side surface of the thin film pattern. 16. A method for manufacturing a semiconductor integrated circuit device, comprising the following steps. (A) directly or indirectly forming a first thin film composed of a single film or a plurality of films on a first main surface of a wafer;
(B) directly or indirectly forming a first photoresist film made of a positive non-benzophenone-based novolak resist on the first thin film, and (c) reducing projection exposure of the first photoresist film. Developing the first photoresist film on which the exposure has been completed to form a first resist pattern on the first thin film; and (d) forming the first resist pattern on the first thin film. The first thin film is patterned by dry etching using a mask, and MISF is formed on a first main surface of the wafer.
A step of forming a gate electrode of ET, (e) a first or a plurality of films including a film that easily causes side wall adhesion during dry etching on a first main surface of the wafer on which the gate electrode is formed; A step of directly or indirectly forming a second thin film, (f) a step of directly or indirectly spin coating a second photoresist film made of a positive benzophenone-based novolak resist on the second thin film, (g)
After exposing the second photoresist film by a reduced projection exposure process, developing the exposed second photoresist film to form a second resist pattern on the second thin film. (H) patterning the second thin film by dry etching using the second resist pattern as a mask such that a forward taper reaching the lower end of a side surface of the thin film pattern is formed;
(I) a step of, after forming the thin film pattern, further performing overetching to remove a side wall adhered film remaining on a side surface of the thin film pattern; 17. The method for manufacturing a semiconductor integrated circuit device according to claim 16, wherein said second thin film is a thin film forming a capacitor of a memory cell of a DRAM. Production method. 18. The method for manufacturing a semiconductor integrated circuit device according to claim 16, wherein said second thin film is formed of a ferroelectric material RA.
A method for manufacturing a semiconductor integrated circuit device, comprising: a thin film forming a capacitor of M memory cells. 19. The method for manufacturing a semiconductor integrated circuit device according to claim 18, wherein said second thin film is made of Pt, Ir,
IrO ₂ , Rh, RhO ₂ , Os, OsO ₂ , Ru, R
A method for manufacturing a semiconductor integrated circuit device, comprising one or more metal thin films or conductive metal oxide thin films selected from the group selected from uO ₂ , Re, ReO ₃ , Pd and Au. 20. The method of manufacturing a semiconductor integrated circuit device according to claim 19, wherein said second thin film is made of PZT, PL
One or two members selected from the group consisting of T, PLZT, SBT, PbTiO ₃ , SrTiO ₃ and BaTiO ₃
A method for manufacturing a semiconductor integrated circuit device, comprising at least one kind of ferroelectric thin film. 21. A method for manufacturing a semiconductor integrated circuit device, comprising the following steps. (A) directly or indirectly forming a first thin film composed of a single film or a plurality of films on a first main surface of a wafer;
(B) a step of directly or indirectly forming a positive photoresist film on the first thin film, in which the cross-sectional shape of the upper end portion or upper half of the pattern side surface is perpendicular, and (c) the first photoresist film. Exposing the photoresist film by a reduced projection exposure process, and then developing the exposed first photoresist film to form a first resist pattern on the first thin film; d) patterning the first thin film by dry etching using the first resist pattern as a mask to form a gate electrode of a MISFET on a first main surface of the wafer; (e)
A step of directly or indirectly forming a second thin film composed of a single or a plurality of films on a first main surface of the wafer on which the gate electrode is formed, (f) on the second thin film, A step of directly or indirectly spin-coating a positive-type second photoresist film in which a cross-sectional shape of an upper end portion or an upper half of a pattern side surface is not perpendicular to that of the first photoresist film; After exposing the second photoresist film by a reduced projection exposure process, developing the second photoresist film after the exposure is completed, forming a second resist pattern on the second thin film,
(H) patterning the second thin film by dry etching using the second resist pattern as a mask such that a forward taper reaching the lower end thereof is formed on a side surface of the thin film pattern; (i) the thin film After forming the pattern, performing a further over-etching to remove the sidewall adhesion film remaining on the side surface of the thin film pattern. 22. A method for manufacturing a semiconductor integrated circuit device, comprising the following steps. (A) directly or indirectly forming a first thin film composed of a single film or a plurality of films on a first main surface of a wafer;
(B) a step of directly or indirectly forming a first photoresist film in which a cross-sectional shape of an upper end portion or an upper half of a pattern side surface is perpendicular to the first thin film, (c) the first photoresist Exposing the film by a reduced projection exposure process, and then developing the exposed first photoresist film to form a first resist pattern on the first thin film; The first thin film is patterned by dry etching using the first resist pattern as a mask, and M is formed on the first main surface of the wafer.
Forming a gate electrode of an ISFET; (e) directly or indirectly applying a second thin film including a conductive film composed of a single film or a plurality of films on a first main surface of the wafer on which the gate electrode is formed. (F) directly forming a second photoresist film on the second thin film, wherein the cross-sectional shape of the upper end portion or upper half of the pattern side surface is not perpendicular to that of the first photoresist film. Or indirectly spin coating, (g) after exposing the second photoresist film by a reduced projection exposure process, developing the exposed second photoresist film, Forming a second resist pattern on the thin film, (h)
Patterning the second thin film by dry etching using the second resist pattern as a mask such that a forward taper reaching the lower end thereof is formed on a side surface of the thin film pattern; (i) forming the thin film pattern After that, a step of removing the side wall adhering film remaining on the side surface of the thin film pattern by further performing over-etching. 23. A method for manufacturing a semiconductor integrated circuit device, comprising the following steps. (A) a step of directly or indirectly forming a thin film composed of a single film or a plurality of films including a film that easily causes side wall adhesion on a first main surface of a wafer; and (b) forming at least a lower side on the thin film. A step of directly or indirectly forming a positive resist pattern having a half-side surface substantially vertical and having a rounded portion at the outer periphery of the head; (c) using the resist pattern as a mask, applying the thin film to the side surface of the thin-film pattern Patterning is performed by dry etching so that a forward taper reaching the lower end is formed, and a forward taper reaching the lower end is formed on the side surface of the sidewall adhesion film attached to each side surface of the resist pattern and the thin film pattern. And (d) after forming the thin film pattern, further performing an over-etching to remove a sidewall adhesion film remaining on the side surface of the thin film pattern. The step of. 24. A method for manufacturing a semiconductor integrated circuit device, comprising the following steps. (A) a step of directly or indirectly forming a thin film composed of a single film or a plurality of films including a film that easily causes side wall adhesion on a first main surface of a wafer; A step of directly or indirectly forming a vertical positive resist pattern; (c) a step of forming a forward taper at an outer peripheral portion of a head of the resist pattern by baking the resist pattern; Using the resist pattern as a mask, the thin film is formed on the side surface of the thin film pattern with a forward taper reaching the lower end thereof, and the lower end thereof is formed on the side surface of a sidewall adhering film attached to each side surface of the resist pattern and the thin film pattern. Patterning by dry etching so as to form a forward taper that reaches the thickness of (e). Removing the sidewall deposited film remaining on the side surface of the thin film pattern performed over etching. 25. A step of (a) directly or indirectly forming a thin film composed of a single film or a plurality of films including a film that easily causes side wall adhesion on a first main surface of a wafer; (C) exposing and developing the photoresist to form a predetermined resist pattern, and (d) using the resist pattern as a mask to form the thin film into a thin film. Patterning by dry etching such that a forward taper reaching the lower end of the pattern is formed on the side surface of the pattern; (e) after forming the thin film pattern, performing over-etching to perform a sidewall remaining on the side surface of the thin film pattern Removing the adhered film, and controlling the focus condition of the exposure light during the exposure of the photoresist, whereby the resist is removed. A method for manufacturing a semiconductor integrated circuit device, wherein a forward taper or roundness is formed on an outer peripheral portion of a head of a strike pattern. 26. A method of manufacturing a semiconductor integrated circuit device, comprising the following steps. (A) directly or indirectly forming a first thin film composed of a single film or a plurality of films on a first main surface of a wafer;
(B) a step of directly or indirectly forming a first photoresist film made of a positive chemically amplified photoresist on the first thin film, and (c) exposing and developing the first photoresist film. Forming a first resist pattern on the first thin film, and (d) patterning the first thin film by dry etching using the first resist pattern as a mask to form a first resist pattern on the wafer. Forming a gate electrode of a MISFET on one main surface;
(E) Forming, directly or indirectly, a second thin film composed of a single film or a plurality of films including a film that is liable to adhere to a side wall during dry etching, on a first main surface of the wafer on which the gate electrode is formed. (F) spin-coating directly or indirectly a second photoresist film made of a negative-type chemically amplified photoresist on the second thin film, (g) the second photoresist film Exposing and developing a second resist pattern on the second thin film, the second resist pattern having a rounded outer periphery of the head, and (h) dry etching using the second resist pattern as a mask. Patterning the second thin film. 27. A method for manufacturing a semiconductor integrated circuit device, comprising the following steps. (A) directly or indirectly forming a first thin film composed of a single film or a plurality of films on a first main surface of a wafer;
(B) a step of directly or indirectly forming a first photoresist film made of a positive chemically amplified photoresist on the first thin film, and (c) exposing and developing the first photoresist film. Forming a first resist pattern on the first thin film, and (d) patterning the first thin film by dry etching using the first resist pattern as a mask to form a first resist pattern on the wafer. Forming a gate electrode of a MISFET on one main surface;
(E) Forming, directly or indirectly, a second thin film composed of a single film or a plurality of films including a film that is liable to adhere to a side wall during dry etching, on a first main surface of the wafer on which the gate electrode is formed. (F) a step of directly or indirectly spin-coating a second photoresist film made of a positive chemically amplified photoresist on the second thin film, and (g) the second photoresist film. Exposing and developing to form a second resist pattern on the second thin film, (h) irradiating the second resist pattern with ultraviolet rays to dissolve only the surface thereof, (i)
After spin-coating an acidic polymer on the surface of the second resist pattern in which only the surface is dissolved, by baking the second resist pattern, the second resist pattern having a rounded outer periphery of the head (J) patterning the second thin film by dry etching using the second resist pattern as a mask. 28. A method for manufacturing a semiconductor integrated circuit device, comprising the following steps. (A) directly or indirectly forming a first thin film composed of a single film or a plurality of films on a first main surface of a wafer;
(B) a step of directly or indirectly forming a first photoresist film made of a positive methacrylic acid-based photoresist on the first thin film, and (c) exposing and developing the first photoresist film. Forming a first resist pattern on the first thin film, and (d) patterning the first thin film by dry etching using the first resist pattern as a mask to form a first resist pattern on the wafer. Forming a gate electrode of a MISFET on one main surface; (e) a single or a single film including a film which is likely to cause side wall adhesion during dry etching on a first main surface of the wafer on which the gate electrode is formed; A step of directly or indirectly forming a second thin film comprising a plurality of films, (f) a second photoresist comprising a negative-type methacrylic acid-based photoresist on the second thin film (G) exposing and developing the second photoresist film to directly or indirectly apply a second resist film on the second thin film, the second resist film having a rounded portion at the outer periphery of the head. Forming a pattern,
(H) patterning the second thin film by dry etching using the second resist pattern as a mask. 29. A method for manufacturing a semiconductor integrated circuit device, comprising the following steps. (A) a step of directly or indirectly forming a thin film composed of a single film or a plurality of films including a film which easily causes side wall adhesion on a main surface of a wafer; Or a step of indirectly spin coating, (c)
Exposing and developing the photoresist to form a predetermined resist pattern; and (d) conditions under which only the resist pattern is etched and that abrasion proceeds obliquely from a corner of the head of the resist pattern. Forming a forward taper on the outer peripheral portion of the head of the resist pattern by performing dry etching for a short time in
(E) patterning the thin film by dry etching using the resist pattern as a mask,
(F) a step of, after patterning the thin film, further performing over-etching to remove a sidewall-adhering film remaining on a side surface of the thin film pattern.