JPH1098161A - Semiconductor storage device - Google Patents

Abstract

(57) [Summary] DRAM with self-amplifying function in memory cell
Is realized with a simple structure. A bit line is a polycide wiring including an N-type polysilicon layer, and a P-type diffusion layer formed on an N-type silicon substrate is connected to the bit line through an N-type diffusion layer.
N-type polysilicon layer 11 is connected. Therefore, the bit line 20 is connected to each memory cell via an NPN-type bipolar transistor using the N-type silicon substrate 1 as an emitter, the P-type diffusion layer 4 as a base, and the N-type diffusion layer 17 and the N-type polysilicon layer 11 as collectors. It will be connected to the access transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device such as a DRAM.

[0002]

2. Description of the Related Art A self-amplifying bipolar transistor is provided in series between an access transistor and a bit line.
AM said, "IEDM'91-465 (A Self-Amplifyin
g (SEA) Cell for Future High Density DRAMs). With this proposal, it has become difficult to secure the memory cell capacity with the recent miniaturization of memory cells, and as a measure to secure the capacity, the storage nodes of memory capacitors, such as fin type and crown type, have been complicated. As a different approach to the method of increasing the capacitance area. That is, by giving the memory cell itself a self-amplification function, a small signal at the time of reading can be directly used as a bit line,
Furthermore, since a signal amplified by passing the signal through a bipolar transistor having a high amplification rate, instead of transmitting the signal to a sense amplifier, is transmitted to a bit line and further to a sense amplifier, the memory cell capacity can be apparently increased.
Therefore, there is a merit that the memory cell structure can be simplified as compared with the above-described method of complicating the storage node.

FIG. 7 shows the structure of a DRAM memory cell proposed in the above article.

As shown, an N-type silicon semiconductor substrate 10
An N-type buried diffusion layer 103 is provided in an element formation region defined by one element isolation oxide film 102. A word line 107 made of N-type polycrystalline silicon is formed on the silicon semiconductor substrate 101 in the element formation region via a gate oxide film.
And a pair of P-type diffusion layers 104 and 105 serving as a source / drain are provided in the silicon semiconductor substrate 101 on both sides of the word line 107 to form a P-channel MOSF.
An access transistor made of ET is formed.
A lower electrode (storage node) 106 of a memory capacitor made of P-type polycrystalline silicon is connected to one P-type diffusion layer 105 of the access transistor, and on this lower electrode 106 via a capacitor insulating film 109. , An upper electrode (cell plate) 108 of a memory capacitor made of P-type polycrystalline silicon is provided. Bit line 120
Are the N-type polysilicon layer 111 and the silicide layer 112
And is provided in the other P-type diffusion layer 104 of the access transistor via an N-type polycrystalline silicon layer 116 and a P-type polycrystalline silicon layer 114 which is a high-resistance layer. It is connected to the N-type diffusion layer 117. Here, 115 is the N-type polycrystalline silicon layer 11.
6 and a contact sidewall oxide film for separating the P-type polycrystalline silicon layer 114 from each other. In the figure, 11
Reference numeral 0 denotes a sidewall oxide film of the word line 107.

As can be seen from the above structure, the bit line 120 has the N-type buried diffusion layer 103 as an emitter, the P-type diffusion layer 104 as a base, and the N-type diffusion layer 117 and the N-type polycrystalline silicon layer 116 as collectors. It is connected to an access transistor of each memory cell via an NPN-type bipolar transistor.

Next, a read operation and a write operation of the DRAM will be described with reference to an equivalent circuit diagram of FIG.

First, a write operation will be described with reference to FIG. In the figure, the potentials of a substrate 101, a cell plate 108, a word line 107 and a bit line 120 in a precharged state are 3.3 V (= V _CC ) and 3.3, respectively.
V, (3.3 + α) V and 0V (= V _SS ). Here, α is for canceling the threshold voltage drop (V _th ′) in the access transistor, and is usually set by a booster circuit so that at least α> V _th ′. At this time, the high resistance layer 114 is a diode element for writing to the memory cell without depending on the data (“0” or “1”) at the time of writing, and the initial (non-charge storage state) storage node potential is , N-type buried diffusion layer 1
Since the built-in potential (φ _bi = about 0.5 V) is lower than that of V.03 (fixed to V _CC ), it is in a so-called floating state, and as shown in FIG. The resistance layer 114 is formed of the N
A reverse bias state is established between the gate electrode and the polycrystalline silicon layer 111, and writing to the storage node 106 is performed with a PN junction leak current at the time of the reverse bias. Note that FIG.
(A) shows the diode characteristics of the high resistance layer 114 at the time of writing, and I _{W on} the vertical axis represents the write current [A],
V _{bl-sn on the} horizontal axis represents a potential difference [V] between the bit line 120 and the storage node 106, respectively. Further, “2E-6” in the figure means “2 × 10 ⁻⁶ ” (the same applies to FIG. 9C and the like). At this time, the bit line 120
In the bipolar transistor between the N-type MOS transistor and the access transistor formed of a P-channel MOSFET, the junction between the collector formed of the N-type diffusion layer 117 and the N-type polycrystalline silicon layer 116 and the base formed of the P-type diffusion layer 104 has a reverse bias. Therefore, the storage node potential cannot be sufficiently written to "1".
That is, in the case of "1" writing, this bipolar transistor cannot be used.

Next, a read operation will be described with reference to FIG. In the figure, the potentials of a substrate 101, a cell plate 108, a word line 107 and a bit line 120 in a precharged state are 3.3 V (= V _CC ) and 3.3, respectively.
V, (3.3 + α) V and 0V (= V _SS ). At the time of reading, the selected word line 107 is turned ON (→ 0 V),
The charge stored in the storage node 106 flows and flows into the P-type diffusion layer 104 on the bit contact side. At this time, since the high resistance layer 114 has a high resistance (= about 250 kΩ), even in the forward direction, the resistance is limited by the resistance of the high resistance layer 114 itself, and most of the current due to the accumulated charges is P P of the bit contact portion. It flows into the mold diffusion layer 104. At this stage, the bipolar transistor is turned on, and a weak signal is amplified (the amplification factor h _fe is substantially determined by the performance of the bipolar transistor, and here, h _fe = 20). The potential change of the line 120 becomes faster. Voltage V _b appearing from the storage node 106 to the P-type diffusion layer 104 is a base of the bipolar _{transistor, V b = V cp / (} 1 + C b / C s): is represented by (V _cp cell plate potential), "1" In the state, the N-type buried diffusion layer 10
The potential difference between the emitter made of P.3 and the base made of the P-type diffusion layer 104 is almost equal to 0 V. As a result, when the base current is almost 0, the above potential difference is almost equal to the cell plate in the "0" state. equal to the potential (= 3.3V) (where, C _s = 25fF, and C _b = 3.5fF.), the base current I _b as shown in FIG. 9 (b) is obtained. To this base current I _b, as shown in FIG. 9 (c), by about one order of magnitude or more larger collector current I _c is obtained, faster potential change of the bit line 120, also possible to increase the amplitude Can be. This amplitude is controlled by the layer resistances of the N-type polycrystalline silicon layer 116 and the high-resistance layer 114 corresponding to the collector resistance. The larger these are, the larger the amplitude can be taken and the S / N ratio is improved. , when the collector resistor is too large, causing a decrease in the collector current I _c, in this example is a 250Keiomega.

[0009]

As described above, the conventional DRAM structure in which the memory cell itself has an amplifying function has been described as a countermeasure against the decrease in the S / N ratio due to the decrease in the memory cell capacity.
As described above, in this conventional structure, at the time of writing "1", the junction between the N-type diffusion layer 117 and the N-type polycrystalline silicon layer 116 as the collector of the bipolar transistor and the P-type diffusion layer 104 as the base is formed. Is reverse biased and is not in the ON state, so that the storage node potential cannot be sufficiently written to "1". Therefore, in the case of "1" writing, the bipolar transistor cannot be used. . Therefore, in the above-described conventional structure, the high resistance layer 114 is provided in the bit contact, and the storage node 10
6 is written.

However, since the high resistance layer 114 is provided in the bit contact, the structure becomes complicated, and the insulation between the high resistance layer 114 and the N-type polycrystalline silicon layer 116 in the bit contact is easy. There was also a problem that it was not.

An object of the present invention is to provide, for example, a semiconductor memory device such as a DRAM capable of reading and writing without providing a high resistance layer in a bit contact.

[0012]

According to the present invention, there is provided a semiconductor memory device having a memory cell including a MOSFET and a capacitor, wherein the MOSFET has a first conductivity type semiconductor substrate. A gate electrode formed thereon with a gate insulating film interposed therebetween, and a pair of second conductive type diffusion layers formed in a surface region of the semiconductor substrate on both sides of the gate electrode; A wiring layer connected to one of the conductive type diffusion layers has a second conductive type polycrystalline semiconductor layer, and the first conductive type semiconductor substrate is an emitter; The wiring layer is connected to the MOSFET via a bipolar transistor having the second conductive type diffusion layer as a base and the second conductive type polycrystalline semiconductor layer as a collector.

According to another aspect of the present invention, there is provided a semiconductor memory device having a memory cell having a MOSFET and a capacitor.
A gate electrode formed on a semiconductor substrate of the first conductivity type via a gate insulating film, and a pair of diffusion layers of the second conductivity type formed in a surface region of the semiconductor substrate on both sides of the gate electrode. A buried diffusion layer of a first conductivity type is formed in contact with the pair of second conductivity type diffusion layers in the semiconductor substrate below the pair of second conductivity type diffusion layers; A wiring layer connected to one of the second conductivity type diffusion layers has a second conductivity type polycrystalline semiconductor layer, and the first conductivity type buried diffusion layer is formed as an emitter. The wiring layer is connected to the MOSFET via a bipolar transistor having the one second conductive type diffusion layer as a base and the second conductive type polycrystalline semiconductor layer as a collector;
Connected to

In one embodiment of the present invention, at the time of writing to the memory cell, the first conductive type semiconductor substrate or the first conductive type buried diffusion layer and the one second conductive type are provided for arbitrary write information. The voltage is at least twice as high as the built-in potential between the wiring layer and the wiring layer.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described according to preferred embodiments.

FIG. 1 shows a structure of a DRAM memory cell according to a first embodiment of the present invention.

As shown in the figure, a concentration of 1 × 10 ¹⁷ / cm ^{3 which} functions as an emitter of an NPN type bipolar transistor.
A P-channel MOSFE is formed in an element formation region defined by the element isolation oxide film 2 of the N-type silicon semiconductor substrate 1.
A word line 7 made of N-type polycrystalline silicon serving as a gate electrode of a T access transistor is formed via a gate oxide film. Concentration 1 ×
A pair of P-type diffusion layers 4 and 5 of about 10 ¹⁶ / cm ³ are formed. One P-type diffusion layer 5 of access transistor
Is formed by connecting a lower electrode (storage node) 6 of a memory capacitor made of P-type polycrystalline silicon.
An upper electrode (cell plate) 8 of a memory capacitor also made of P-type polycrystalline silicon is formed on the lower electrode 6 via a capacitance insulating film 9 made of an ONO film.
The bit line 20 is composed of an N-type polycide wiring composed of an N-type polycrystalline silicon layer 11 having a concentration of about 1 × 10 ¹⁸ / cm ³ and a silicide layer 12, and the N-type polycrystalline silicon layer 11 is used for an access transistor. It is directly connected to an N-type diffusion layer 17 provided in the other P-type diffusion layer 4 within a bit contact. Reference numeral 10 denotes a sidewall oxide film of the word line 7.

Next, referring to FIG. 2 and FIG.
The write operation of the DRAM memory cell according to the embodiment will be described. Note that the read operation is substantially the same as the conventional one described above.

First, in FIG. 2 showing an equivalent circuit diagram, a substrate 1, a cell plate 8, and a precharged word line 7 are shown.
And the potential of the bit line 20 is 4.3 V (= V _CC +
β, β = 1.0), 3.3 V (= V _CC ), (3.3+
α ′) V and 0 V (= V _SS ). Where α ′ is
The threshold voltage drop (V
_th ′) to cancel each other.
At least α ′> V _th ′ is set. By increasing the substrate potential _Vsub from 3.3 V to 4.3 V, _Vth 'also becomes larger than in the normal case (when _Vsub = 3.3 V).

[0020] shows the characteristics of the bipolar transistor of the present embodiment in FIG. 3, in FIG. 2, V _eb bit line 20
, And even in the case of “1” writing, the initial (non-charge storage state) storage node potential is the N-type silicon substrate 1 (V _CC + 2φ _bi = 4.
Built-in potential (φ _bi =
Because it is in about 0.5V) dropped _{(V CC + φ bi),} V eb
≒ φ _bi (= about 0.5 V), the bipolar transistor is turned on, and writing from the bit line 20 becomes possible. That is, a bipolar transistor can be used as a switch without depending on write data.

FIG. 4 shows a structure of a DRAM memory cell according to a second embodiment of the present invention. In the second embodiment, parts corresponding to those in the above-described first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

As shown in FIG. 4, in the second embodiment, the element isolation structure is a field shield element isolation structure using a shield plate electrode 13 and the lower part of the P-type diffusion layers 4 and 5 of the access transistor. Is different from the above-described first embodiment in that an N-type buried diffusion layer 3 is provided.

FIG. 5 shows a density profile along the line AA in FIG. 4. In this second embodiment, the NPN
By adopting a retro-grade well structure as the emitter diffusion layer of the p-type transistor, the difference in concentration between the base diffusion layer (P-type diffusion layer 4) and the base diffusion layer is made larger than in the above-described first embodiment, so Has the effect of increasing the emitter injection efficiency and increasing the amplification factor, and further, since the substrate surface concentration can be relatively reduced as compared with the above-described first embodiment, the substrate bias effect in the access transistor portion is weakened. Since it has a function and the boosted voltage of the word line 7 (corresponding to α ′ described above) can be suppressed to a small value,
The precharge time at the time of reading can be reduced, and as a result, the reading time can be further reduced.

FIG. 6 shows the dependence of the threshold voltage V _th of the access transistor on the substrate bias potential V _{bs in} the case of the first embodiment (A) and in the case of the second embodiment (B). Is shown.

[0025]

According to the present invention, a DRAM or the like having a self-amplifying function in a memory cell itself can be realized with a relatively simple structure. In addition, since it is not necessary to use a high-resistance layer for connecting the bit line and the access transistor, particularly,
At the time of writing, the writing time can be reduced.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a structure of a DRAM memory cell according to a first embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of the DRAM memory cell according to the first embodiment of the present invention.

FIG. 3 is a graph showing current-voltage characteristics of the bipolar transistor of the DRAM memory cell according to the first embodiment of the present invention.

FIG. 4 is a sectional view showing a structure of a DRAM memory cell according to a second embodiment of the present invention.

FIG. 5 is a graph showing a concentration profile of a DRAM memory cell according to a second embodiment of the present invention.

FIG. 6 is a graph showing a threshold voltage-substrate bias voltage dependency of an access transistor according to each embodiment of the present invention.

FIG. 7 is a cross-sectional view showing the structure of a conventional DRAM memory cell.

FIG. 8 is an equivalent circuit diagram for explaining a read operation and a write operation of a conventional DRAM memory cell.

FIG. 9 is a graph showing current-voltage characteristics of a bipolar transistor of a conventional DRAM memory cell.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 N-type silicon semiconductor substrate 3 N-type buried diffusion layer 4, 5 P-type diffusion layer 6 capacitance lower electrode (storage node) 7 word line 8 capacitance upper electrode (cell plate) 9 capacitance insulating film 11 N-type polycrystalline silicon layer 12 Silicide layer 17 N-type diffusion layer 20 Bit line

Claims (3)

[Claims] 1. A semiconductor memory device having a memory cell including a MOSFET and a capacitor, wherein the MOSFET is formed on a semiconductor substrate of a first conductivity type via a gate insulating film, and the gate electrode And a pair of second conductive type diffusion layers formed in the surface region of the semiconductor substrate on both sides of the pair of second conductive type diffusion layers. A wiring layer to be connected has a second conductivity type polycrystalline semiconductor layer, wherein the first conductivity type semiconductor substrate is an emitter, the one second conductivity type diffusion layer is a base, and the second conductivity type polycrystalline semiconductor layer is a second conductivity type diffusion layer. A semiconductor memory device, wherein the wiring layer is connected to the MOSFET via a bipolar transistor having a crystalline semiconductor layer as a collector. 2. A semiconductor memory device having a memory cell including a MOSFET and a capacitor, wherein the MOSFET is formed on a semiconductor substrate of a first conductivity type via a gate insulating film, and the gate electrode And a pair of second conductive type diffusion layers formed in the surface region of the semiconductor substrate on both sides of the semiconductor substrate. The pair of second conductive type diffusion layers are formed in the semiconductor substrate below the pair of second conductive type diffusion layers. A first conductivity type buried diffusion layer is formed in contact with the conductivity type diffusion layer, and a wiring layer connected to one of the pair of second conductivity type diffusion layers is a second conductivity type diffusion layer. A first conductivity type buried diffusion layer as an emitter, the one second conductivity type diffusion layer as a base, and the second conductivity type polycrystalline semiconductor layer as a collector; Bipolar Transient Through the data, the semiconductor memory device, wherein the wiring layer is connected to the MOSFET. 3. A method according to claim 1, wherein at the time of writing to said memory cell, for any write information, said first conductivity type semiconductor substrate or said first conductivity type buried diffusion layer and said one second conductivity type diffusion layer 3. The semiconductor memory device according to claim 1, wherein a voltage at least twice the built-in potential is applied to said wiring layer.