JPH1091304A - Equipment with microcomputer - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To remove disturbance to a control signal for access and always perform reliable access. A microcomputer 1 and a peripheral circuit unit 2
Disturbance removing means 5, 6, 7 for removing disturbance to various control signals (/ CS signal, / RD signal, / WR signal) used at the time of access to the bus interface unit 3 in the peripheral circuit unit; The microcomputer controls an access operation while transmitting a control signal to the peripheral circuit unit and checking whether the control signal is output from the disturbance removing unit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a device having a microcomputer such as an electronic watt-hour meter.

[0002]

2. Description of the Related Art In accessing data between a microcomputer (hereinafter also referred to as a microcomputer) and a peripheral device, a peripheral circuit section (hereinafter also referred to as a peripheral device) to be accessed is selected in addition to an address signal and a data signal. Chip select signal (hereinafter referred to as a / CS signal), a read signal used to read data from a selected peripheral device (hereinafter referred to as a / RD signal), and when writing data to the selected peripheral device. This is performed by using a control signal such as a write signal (hereinafter, referred to as a / WR signal).

[0006] Referring to FIG. 6, a description will be given of data access between the microcomputer 101 and the peripheral devices 102 (102 A to 102 N). Each peripheral device 1
02A to 102N have the same configuration, and the bus interface units 103A to 103N and the internal circuit 10A respectively.
4A to 104N.

When reading data from the peripheral device 102A among the peripheral devices 102A to 102N, the microcomputer 101 first outputs a / CS signal for selecting the peripheral device 102A, and then outputs the / CS signal. An address signal is output to the internal circuit 104A via the bus interface unit 103A in the internal circuit (more specifically, a signal indicating an address to be read from a memory (not shown) in the internal circuit 104A is output). Subsequently, a / RD signal is output to the bus interface unit 103A. In response, on the peripheral device 102A side, the contents of the memory specified by the address are transmitted from the internal circuit 104A to the bus interface unit 103A.
And outputs it to the microcomputer 101 as a data signal via the.
Then, the microcomputer 101 reads out the data signal at a predetermined timing and records the data signal in the internal register. Thus, the operation of reading data from the peripheral device 102A is completed.

When writing data to the peripheral device 102A, the microcomputer 101 first outputs a / CSA signal for selecting the peripheral device 102A, and then outputs a bus signal in the selected peripheral device 102A. Internal circuit 104A via interface section 103A
Output an address signal to the internal circuit 1
A signal indicating an address number to be written into a memory (not shown) in the memory 04A is output). Subsequently, the microcomputer 101 converts the contents of the internal register into a data signal through the bus interface unit 103A via the bus interface unit 103A.
Output to In response, the peripheral device 102A writes data to the specified address.
Thereby, the microcomputer 101 sends the peripheral device 102A
The operation of writing data to the memory ends.

[0006]

By the way, in the above-mentioned conventional example, in order to give priority to the speed performance at the time of access, a check code such as a parity is added to n-bit data and the normal operation is performed. In addition to ensuring timing matching at the time of design, there is almost no means for ensuring the reliability of the access itself, and because of its speed performance, it is extremely resistant to disturbances such as noise, radio waves, and static electricity applied to the control signal. It reacts sensitively, and a disturbance may be applied to the control signal at the time of access or at a time other than the access, which may cause a malfunction of the system.

In view of this, as shown in FIG. 7, filters 105 to 107 are arranged in the interface section 103A to remove disturbance added to control signals such as the / CS signal, the / RD signal, and the / WR signal. Can be considered. However, by disposing the filters 105 to 107 in this manner, as shown in FIGS.
/ CS signal, / RD signal, / W input to 5 to 107
In response to the R signal, its output, ie, the internal / CS signal, internal / RD signal, and internal / WR input to the internal circuit 104A
A time delay occurs in the signal (indicated by T1 and T2 in FIGS. 8 and 9), a mismatch in the latch timing of the read data and the write data occurs, and normal access cannot be performed. And the problem of erroneous selection of the target peripheral device.

(Object of the Invention) It is an object of the present invention to provide a device having a microcomputer capable of removing a disturbance with respect to a control signal for access and performing reliable access at all times.

[0009]

In order to achieve the above object, according to the present invention, there is provided a bus interface section of a peripheral circuit section provided with a disturbance removing section for removing disturbance to various control signals used at the time of access. The computer controls the access operation while confirming whether a control signal such as a write signal or a read signal sent to the peripheral circuit section is output from the disturbance elimination means.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on illustrated embodiments.

FIG. 1 is a block diagram showing the configuration of a device having a microcomputer according to an embodiment of the present invention (hereinafter abbreviated as a microcomputer device). 1 is a microcomputer, and 2 is connected to the microcomputer 1. Among the N peripheral devices, one is a peripheral device, 3 is a bus interface unit provided in the peripheral device 2, and 4 is an internal circuit also provided in the peripheral device 2.
Reference numerals 5, 6, and 7 are arranged in the bus interface unit 3, and are supplied with the / CS signal and / RD input from the microcomputer 1.
This is a filter for removing disturbance added to each control signal of the signal and the / WR signal, and each output of the filter is output to the internal circuit 4 and sent back to the microcomputer 1 at the same time. I have.

Next, a description will be given of a case where the microcomputer 1 and the peripheral device 2 access n-bit data in the above configuration.

First, the case where the microcomputer 1 reads data from the internal circuit 4 of the peripheral device 2 will be described with reference to the flowchart of FIG. 2 and the timing chart of FIG.

First, in step # 11 of FIG. 2, the microcomputer 1 outputs a / CS signal for selecting the peripheral device 2 to the bus interface unit 3 (Hi → Low),
In the next step # 12, an address signal is output. Then, in the following step # 13, the filter 5
It is checked whether or not the internal / CS signal has been output (Hi → Low). While the internal / CS signal is not output (Hi
During this step, the process waits at this step, and after confirming that the internal / CS signal has been output (inverted to Low) from the filter 5, it is confirmed that the internal / CS signal has been securely input to the internal circuit 4. ), The process proceeds to step # 14.

In step # 14, a / RD signal is output to the bus interface unit 3 (Hi → Low),
In the following step # 15, it is checked whether or not the internal / RD signal has been output from the filter 6 (Hi → Low).
Until the internal / RD signal is output (while Hi), the process waits at step # 15, and then it is confirmed that the internal / RD signal has been output (inverted to Low) from the filter 6 (internal). (This means that the internal / RD signal has been securely input to the circuit 4).
At the same time as inverting the RD signal from Low to Hi, the read data is latched at this rising edge.

In response to the input of the internal / RD signal (Hi → Low), the internal circuit 4 first stores the contents of the memory specified by the address signal in the bus interface unit 3.
As shown in FIG. 3, the data signal is output from the low / high of the / RD signal to the high signal as shown in FIG.
It is possible to reliably latch read data at the time of rising.

In the next step # 17, the microcomputer 1 stores the latched read data in the internal register.

According to the above configuration, as apparent from FIG. 3, it is confirmed that the internal / CS signal is output to the output side of the filter 5 and the internal / RD signal is output to the output side of the filter 6. After that, the data signal is sent from the peripheral device 2 to the microcomputer 1, so that the desired read data can be reliably latched at the rise of the / RD signal from Low to Hi, and the reliable data Can be read.

In the above embodiment, the latch timing of the read data is changed from the low level of the / RD signal to the high level.
Although it is performed at the rise to i, it is not limited to this, and it goes without saying that it may be at the time of detecting the output of the internal / RD signal (Hi → Low).

Next, the case where the microcomputer 1 writes data to the memory in the internal circuit 4 of the peripheral device 2 will be described with reference to the flowchart of FIG. 4 and the timing chart of FIG.

First, in step # 21 of FIG. 4, the microcomputer 1 outputs a / CS signal for selecting the peripheral device 2 to the bus interface unit 3 (Hi → Low),
In the next step # 22, an address signal is output. Then, in the subsequent step # 23, the filter 5
It is checked whether or not the internal / CS signal has been output (Hi → Low). While the internal / CS signal is not output (Hi
During this step, the process waits at this step, and after confirming that the internal / CS signal has been output (inverted to Low) from the filter 5, it is confirmed that the internal / CS signal has been securely input to the internal circuit 4. ), The process proceeds to step # 24.

In step # 24, the output of the write data to the bus interface unit 3 is started, and in the next step # 25, a predetermined time / WR signal is output (Hi
→ Low). Then, in the next step # 26, the output of the / WR signal is stopped (Low → Hi). In the subsequent step # 27, it is checked whether or not the internal / WR signal has been reliably stopped (Low → Hi) from the filter 7. If it is confirmed that the output of the internal / WR signal has been stopped, the process proceeds to step # 28.

The peripheral device 2 latches write data from the microcomputer 1 when the internal / WR signal rises from low to high. That is, at this time, the output of the write data from the microcomputer 1 is still performed.
Can be reliably latched.

In step # 28, the microcomputer 1 stops outputting the write data to the peripheral device 2.

According to the above configuration, the internal / CS signal is output to the output side of the filter 5, as is apparent from FIG.
Further, after confirming that the internal / WR signal generated on the output side of the filter 7 has been stopped, the output of the write data from the microcomputer 1 to the peripheral device 2 is stopped. , The desired write data can be reliably latched, and the writing of the write data to the peripheral device 2 can be reliably performed.

In the above embodiment, the timing of latching the write data is performed at the rise of the internal / WR signal from low to high. However, the present invention is not limited to this. Needless to say, it may be the time when the / WR signal starts to be output (Hi → Low).

According to the above-described embodiment, a filter for removing a disturbance to a control signal for access is provided in the bus interface unit of the peripheral device.
In addition to preventing the system from malfunctioning due to disturbances such as noise, radio waves, static electricity, etc., the output of the filter is taken into a microcomputer, and access to the peripheral device is performed while checking the state of the peripheral device. Is arranged to prevent a mismatch in the latch timing of the read data and the write data due to the delay of the control signal.

Therefore, reliable access to a desired peripheral device can be performed without being affected by disturbance.

(Modification) In the above embodiment,
Although an example is shown in which a filter is arranged for removing disturbance to a control signal, the filter includes a digital filter. Further, the present invention is not limited to the filter, but may be any means that can remove disturbance.

Although a system that performs both reading and writing is taken as an example, it goes without saying that a system that performs only one of them may be used.

As the peripheral device of the present invention, any electronic device having an electronic watt-hour meter and other microcomputers requiring high reliability can be applied.

[0032]

As described above, according to the present invention,
At the time of access to the peripheral circuit section, the microcomputer controls the access operation while confirming whether the write signal or the read signal has been transmitted to the peripheral circuit section reliably. Thus, reliable access can always be performed without being affected by the delay of the control signal due to the means for performing the access.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a microcomputer device according to an embodiment of the present invention.

FIG. 2 is a flowchart showing an operation when reading data from a peripheral device to the microcomputer of FIG. 1;

FIG. 3 is a timing chart to help explain the operation of FIG. 2;

FIG. 4 is a flowchart showing an operation when data is written from the microcomputer of FIG. 1 to a peripheral device.

FIG. 5 is a timing chart to help explain the operation of FIG. 4;

FIG. 6 is a block diagram showing a configuration of a conventional microcomputer device.

FIG. 7 is a block diagram showing an example of a configuration conceivable for eliminating a defect of the microcomputer device of FIG. 6;

8 is a timing chart for explaining a problem that occurs when reading data in the configuration of the microcomputer device of FIG. 7;

9 is a timing chart for explaining a problem that occurs when writing data to a peripheral device in the configuration of the microcomputer device of FIG. 7;

[Explanation of symbols]

 1 Microcomputer 2 Peripheral device 3 Bus interface unit 4 Internal circuit 5-7 Filter / CS Chip select signal Internal / CS Internal chip select signal / RD Read signal Internal / RD Internal read signal / WR Write signal Internal / WR Internal write signal

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[Procedure amendment]

[Submission date] November 19, 1996

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0004

[Correction method] Change

[Correction contents]

To read data from the peripheral device 102A among the peripheral devices 102A to 102N, the microcomputer 101 first outputs a / CSA signal for selecting the peripheral device 102A, and then outputs the / CSA signal. Bus interface section 1
An address signal is output to the internal circuit 104A via the circuit 03A (more specifically, a signal indicating an address address to be read from a memory (not shown) in the internal circuit 104A is output). Subsequently, the bus interface unit 103
A / RD signal is output to A. In response to this, on the peripheral device 102A side, the contents of the memory specified by the address are transmitted from the internal circuit 104A to the bus interface unit 10A.
The data signal is output to the microcomputer 101 as a data signal via 3A. Then, the microcomputer 101 reads out the data signal at a predetermined timing and records the data signal in the internal register.
Thus, the operation of reading data from the peripheral device 102A is completed.

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] Fig. 4

[Correction method] Change

[Correction contents]

FIG. 4 is a flowchart showing an operation when data is written from the microcomputer of FIG. 1 to a peripheral device.

Claims (1)

[Claims] 1. A bus interface unit in the peripheral circuit unit, wherein a disturbance removing unit that removes disturbance to various control signals used at the time of access between the microcomputer and the peripheral circuit unit is provided.
An apparatus having a microcomputer, wherein a control signal is sent to the peripheral circuit unit, and at the same time, an access operation is controlled while checking whether or not the control signal is output from the disturbance elimination means.