JPH1091255A - Stabilized power source circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the output voltage of a stabilized power source whose output can be turned on and off from overshooting when the output is turned on. SOLUTION: The reference voltage of a reference voltage source circuit 1 is inputted to one input terminal of a differential amplifier circuit consisting of PMOSs P2, P4, and P5 and NMOSs N1 and N2 and the output voltage is fed back to the other input terminal. The output amplified by the differential amplifier circuit is inputted to an amplifier circuit consisting of a PMOS P3 and NMOSs X and N3. In this amplifier circuit, the NMOS X operates as an 0N/OFF switch of the amplifier circuit. Its output is inputted to an output stage consisting of PMOSs P6 and P7, C1, and R1, R2, and R3. Outputs of output terminals 7 to 9 are turned on and off by turning on and off P6 with a signal inputted to a terminal 6. Then X is turned on and off in synchronism with the on/off operation of P6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stabilized power supply circuit, and more particularly to a stabilized power supply circuit composed of CMOS in an IC (integrated circuit) or the like.

[0002]

2. Description of the Related Art Conventionally, a stabilized power supply circuit of this kind, as shown in FIG. 5, includes a voltage of a reference voltage source circuit 1 inputted to a gate terminal 3 of a P-channel MOS transistor P4,
A differential amplifier circuit including P-channel MOS transistors P2, P4, P5 and N-channel MOS transistors N1, N2 operating to equalize the voltage of the gate terminal 4 of the P-channel MOS transistor P5;
S transistor P3, N channel MOS transistor N
3, an output stage including P-channel MOS transistors P6 and P7, resistors R1, R2, R3, and a capacitor C1, and a control including inverters I1 and I2 for controlling on / off of a current flowing through the output stage. And a circuit.

When a control signal input to control signal input terminal 6 is at a high level, a P-channel MOS transistor P
6 turns off, and the outputs of the output terminals 7, 8, and 9 become the GND level. Therefore, P5 and N3 are strongly turned on, and the potential of the output stage input terminal 5 becomes the GND level, so that P7 is turned on. When the control signal of the input terminal 6 is at the low level, the P-channel MOS transistor P6 is turned on, and the output terminals 7, 8, and 9 of the terminal 4 which has become equal to the potential of the terminal 3 output from the reference voltage source circuit 1. The potential is set to the resistance R1,
The voltage divided by the resistors R2 and R3 is output.

[0004]

In the conventional stabilized power supply circuit described above, when the control signal input to the control signal input terminal 6 is at a high level as shown at time t1 in FIG. )], Since the P-channel MOS transistor P6 is turned off, the gate terminal 4 becomes the GND potential and becomes lower than the gate terminal 3, so that the current of the differential circuit mostly flows through the P-channel MOS transistor P5. Therefore, the gate potential of the N-channel MOS transistor N3 rises, the output stage input terminal 5 is pulled to the GND side potential (FIG. 6C), and the P-channel MOS transistor P7 is turned on. In this state, when the control signal input terminal 6 goes low (time t2 in FIG. 6), the P-channel MOS transistor P6 turns on and the output terminal 7 rises to the VDD potential before feedback is applied to the differential amplifier circuit. I will try.
Therefore, the potential of the output terminal 7 has an overshoot rising waveform as shown in FIG.

As a result, for example, when the output voltages of the output terminals 7, 8, and 9 are used as a power supply for driving a liquid crystal panel, undesired phenomena such as an instantaneous darkening of display due to overshoot occur. Therefore, the problem to be solved by the present invention is firstly to reduce the overshoot of the rising waveform of the output of the stabilized power supply circuit, and secondly, to reduce the output so as to be compatible with various load circuits and applications. That is, a rising waveform can be selected.

[0006]

According to the present invention, there is provided a differential amplifier circuit for comparing and stabilizing a reference voltage of a reference voltage source with a feedback voltage from an output. An amplifier circuit for amplifying an output signal of the amplifier circuit, an output stage for outputting an output voltage of the amplifier circuit, and a control circuit for controlling on / off of an output of the output stage by a control signal; A stabilized power supply circuit is provided, wherein a variable impedance means whose resistance value changes between low and high is inserted in the amplifier circuit in synchronization with on / off of an output stage by the control signal. .

[0007]

FIG. 1 is a circuit diagram for explaining an embodiment of the present invention. As shown in FIG. 1, a stabilized power supply circuit according to the present invention compares a reference voltage source circuit 1 for producing a reference voltage of the stabilized power supply circuit with a reference voltage output from the reference voltage source circuit 1 and an output voltage. Differential amplifier circuits (P2, P4, P5, N1, N2) and amplifier circuits (P3, X, N3) for amplifying output signals of the differential amplifier circuits
And an output circuit (P6, P6) that outputs the output voltage of the amplifier circuit.
7, C1, R1, R2, R3) and a control circuit (I1, I2) for controlling on / off of the output of the output circuit.

That is, the reference voltage of the reference voltage source circuit 1 is determined by P-channel MOS transistors P2, P4, P5,
The input voltage is input to one input terminal of a differential amplifier circuit composed of N-channel MOS transistors N1 and N2, and the output voltage is fed back to the other input terminal. The output amplified by the differential amplifier circuit is a P-channel MOS transistor P3,
The signal is input to an amplifier circuit composed of N-channel MOS transistors X and N3. In this amplifier circuit, the N-channel MOS transistor X functions as an on / off switch or a variable impedance element of the amplifier circuit. This output is output to the output stage via the output stage input terminal 5. P-channel MOS transistors P6 and P7 function as a switching element and an amplifying element, respectively.
1, R2 and R3 divide the voltage and output a plurality of potentials, and feed back the output to the differential amplifier circuit. Output terminal 7,
The control circuit for controlling on / off of the voltage of 8, 9 is CMO
A control signal to this control circuit which is constituted by S inverters I1 and I2 is input via a control signal input terminal 6.

This control signal is input to the gate of N-channel MOS transistor X via inverter I1. Here, the size of the N-channel MOS transistor X is selected so that the rising waveform when the voltage of the output terminal shifts from the GND level to the ON level has a desired shape. Now, as shown at time t1 in FIG. 2, assuming that the control signal input to the control signal input terminal 6 is at a high level, the output circuit is in an off state by turning off P6. At this time, the transistor X
Is at low level, the transistor is turned off (high impedance state), the terminal 5 is at high level (almost VDD), and P7 is also off. Time t
When the control signal input to the terminal 6 at 2 turns low (FIG. 2A), the transistor X and the P-channel MOS transistor P6 connected to the power supply line VDD
Turns on. The turning on of the transistor X lowers the potential of the terminal 5 [FIG. 2 (b)], and turns on P7. Output terminal 7 is GN because P6 and P7 are turned on.
The potential becomes equal to or higher than the D potential, and a constant potential is output from the terminals 7, 8, and 9. The potential of the output terminal 7 gradually rises. During this time, feedback is applied by the differential amplifier circuit and the amplifier circuit.
The potential indicated by the reference voltage source circuit 1 can be generated without causing overshoot [FIG.
(C)].

Attention is paid to the potential of the input terminal 5 of the output stage. When the transistor X is turned off, the potential of the input terminal 5 which has been substantially VDD when the transistor X is turned off decreases. Speed is condenser C1
Discharge time. That is, the time constant C mainly determined by C1 and the impedance of the transistor X
Depends on R. Therefore, the size of the transistor X is set to (W
By appropriately selecting / L), the fall of the potential at the terminal 5 can be selected as shown in FIG. That is, a large size (or W /
By forming a transistor having a large L, the falling characteristic can be selected, or by forming a transistor having a small size (or a small W / L), the falling characteristic can be selected. . Since the rise of the potential of the output terminal 7 follows the fall characteristics of the potential of the input terminal 5, by selecting the transistor size as described above,
The potential of the output terminal 7 can also be changed similarly (FIG. 2B), and the overshoot in the conventional example can be prevented.

The circuit of FIG. 1 can be modified as follows. (A) Instead of the N-channel MOS transistor X, a plurality of transistors having different sizes are formed in parallel so that an appropriate transistor can be selected by a decoder circuit according to the purpose of use. (B) Instead of the N-channel MOS transistor X, a plurality of transistors of the same size are formed in parallel so that an appropriate number of transistors can be selected by a decoder circuit according to the purpose of use. (C) P-channel MOS transistors are used in place of the N-channel MOS transistors in the circuit of FIG. 1 and the circuits obtained by modifying the above (a) and (b).

[0012]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 3 is a circuit diagram for explaining the first embodiment of the present invention. In FIG. 3, the same parts as those of the circuit shown in FIG. 1 are denoted by the same reference numerals, and the duplicated description will be omitted.
N channel M instead of N channel MOS transistor X
A parallel circuit of OS transistors A1, A2,... An is provided in the amplifier circuit. These N-channel MOS
The sizes of the transistors A1, A2,... An are different from each other. One of these transistors is selected by the decoder circuit 2 to which the selection signals S1, S2... Sm are input, and the output signal of the inverter I1 is applied to the selected transistor.

Now, assuming that the control signal input to the control signal input terminal 6 is at a high level, the output circuit is off by turning off P6, and the N-channel MOS transistor selected by the decoder circuit 2 The transistor Ak is also off. Therefore, the input terminal 5 is at a high level (almost VDD), and P7 is also off. next,
When the control signal input to the control signal input terminal 6 changes to a low level, the selected N-channel MOS transistor Ak (k = 1, 2,..., N) and the P-channel MOS transistor P6 connected to the power supply line VDD Turns on.
The turning on of the transistor Ak lowers the potential of the terminal 5 and turns on P7. Since the terminals P6 and P7 are turned on, the output terminal 7 becomes higher than the GND potential, and the terminal 7,
A constant potential is output from 8 and 9. Although the potential of the output terminal 7 gradually rises, the differential amplifier circuit and the amplifier circuit feed back during this period, so that the potential indicated by the reference voltage source circuit 1 can be generated without causing overshoot.

Here, the rising characteristic of the output terminal 7 is as follows.
Since it depends on the on-resistance of the selected transistor Ak, the rising curve shown in FIG. 2B can be realized by changing the selected transistor. In the first embodiment described above, only one transistor is selected. However, two or more transistors may be selected. By doing so, it is possible to select the rising characteristics in a wider range without increasing the number of transistors formed.

Next, a second embodiment of the present invention will be described. Also in this embodiment, the circuit is configured as shown in FIG. 3, but the N-channel MOS transistors A1, A2,.
An have the same size, and control signals S1, S2,.
..N-channel MOS transistor A selected by Sm
The number of 1, A2... An is changed. When only A1 is selected, the time constant CR increases, the rising waveform of the output terminal 7 becomes as shown in FIG. 2B, and A1 and A2
.. When all An are selected, the time constant CR becomes small, and the rising waveform of the output terminal 7 becomes as shown in FIG.

FIG. 4 is a circuit diagram for explaining a third embodiment of the present invention. In FIG. 4, the same parts as those of the circuit of the first embodiment shown in FIG. 3 are denoted by the same reference numerals, and the description thereof will not be repeated. In this embodiment, a P-channel MOS transistor is used instead of the N-channel MOS transistors A1, A2,.
The transistors B1, B2,... Bn are used,
As a result, the output signal of the inverter I2 is
Bn is applied to one of the channel MOS transistors B1, B2,... Bn. Also in this embodiment, the size of each transistor is formed differently, and one of the transistors is controlled by the control signals S1 and S1.
2... Sm, thereby realizing a desired rising characteristic of the output voltage. However, the present embodiment can be modified so as to select a plurality of transistors.

Next, a fourth embodiment of the present invention will be described. In the fourth embodiment, a circuit configuration similar to that of the third embodiment shown in FIG. 4 is employed.
The channel MOS transistors B1, B2,... Bn are all configured with the same size, and the control signals S1, S2,.
P-channel MOS transistors B1, B2
.. Change the number of Bn.

[0018]

As described above, in the stabilized power supply circuit according to the present invention, a variable amplifier whose impedance changes by a signal for controlling on / off of an output voltage is provided in an amplifier circuit for amplifying an output of a differential amplifier circuit. Since the impedance element is inserted, feedback can be effectively applied when the output voltage turns on, and overshoot of the output voltage can be prevented. Therefore, when the stabilized power supply circuit according to the present invention is applied to, for example, a power supply for driving a liquid crystal panel or the like, it is possible to prevent inconveniences such as a dark display for a moment. Further, according to the embodiment of the present invention, it is possible to select a rising waveform of an arbitrary output voltage by selecting one or a plurality of transistors from a plurality of MOS transistors controlled in parallel.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating an embodiment of the present invention.

FIG. 2 is a voltage waveform chart for explaining the operation of the circuit of FIG.

FIG. 3 is a circuit diagram for explaining first and second embodiments of the present invention.

FIG. 4 is a circuit diagram for explaining third and fourth embodiments of the present invention.

FIG. 5 is a circuit diagram of a conventional example.

FIG. 6 is a voltage waveform diagram for explaining a problem of the conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Reference voltage source circuit 2 Decoder circuit 3, 4 Gate terminal 5 Output stage input terminal 6 Control signal input terminal 7, 8, 9 Output terminal

Claims (5)

[Claims] 1. A differential amplifier for comparing a reference voltage of a reference voltage source with a feedback voltage from an output, an amplifier for amplifying an output signal of the differential amplifier, and an output voltage of the amplifier. An output stage; and control means for controlling on / off of an output of the output stage by a control signal. The amplification circuit has a resistance value in synchronization with on / off of the output stage by the control signal. Characterized in that variable impedance means that changes between low and high are inserted. 2. The stabilized power supply circuit according to claim 1, wherein said variable impedance means comprises a MOS transistor. 3. A stabilized power supply according to claim 1, wherein said variable impedance means is constituted by one or more MOS transistors selected from a plurality of MOS transistors connected in parallel. circuit. 4. The plurality of MOS transistors connected in parallel are formed in different sizes, and a selected transistor changes a rising waveform of an output voltage when the output stage turns from off to on into a desired shape. 4. The stabilized power supply circuit according to claim 3, wherein the power supply circuit is determined to be operated. 5. The plurality of MOS transistors connected in parallel are formed to have the same size, and the number of selected transistors is determined by adjusting a rising waveform of an output voltage when the output stage changes from off to on. 4. The stabilized power supply circuit according to claim 3, wherein the stabilized power supply circuit is determined to have a shape.