JPH1083168A - Liquid crystal display - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To provide an enlarged display with high image quality even when display data having a resolution lower than that of a liquid crystal panel is input. SOLUTION: In a latch circuit 110, 112 of a liquid crystal driving circuit, a storage element system is provided corresponding to each drain line. Some storage element systems simultaneously display data 101
Take in. Then, the same liquid crystal applied voltage is output from the drain lines 115 corresponding to these storage element systems. An image can be enlarged in the horizontal direction by allowing the storage element systems corresponding to the drain lines adjacent to each other to simultaneously capture display data. The enlargement ratio can be adjusted by changing the number of storage element systems that simultaneously take in display data.
The scanning drive circuit simultaneously selects a plurality of rows, and applies a selection voltage to the pixel units of the simultaneously selected rows during the same period, whereby the image can be enlarged in the vertical direction. Even when rows are selected one by one, enlarged display can be performed by the liquid crystal drive circuit adjusting the output period of the liquid crystal applied voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly to a liquid crystal drive circuit capable of enlarging and displaying a low-resolution video signal on a high-resolution liquid crystal panel.

[0002]

2. Description of the Related Art A conventional liquid crystal display is shown in FIGS.
This will be described with reference to FIG.

FIG. 2 is a block diagram of a conventional liquid crystal driver. FIG. 3 is a timing chart showing the operation of the conventional liquid crystal driver. FIG. 4 is a block diagram of a liquid crystal display using a conventional liquid crystal driver.

In FIG. 2, reference numeral “101” denotes a data bus for transferring display data. Code “1”
02 is the clock CL2 synchronized with the display data 101. Hereinafter, similarly, "103" is a display data capture start signal EI, and "104" is a horizontal synchronization signal generated every one horizontal period. CL1 indicates a reference gray-scale voltage which is a reference of a gray-scale voltage output from the present liquid crystal driver, “201” indicates a shift register circuit, and “202” indicates a shift register circuit. A group of latch signals to be generated, “203” indicates a data latch circuit, “204” indicates a data bus for transferring line data output from the data latch circuit 203, and “205” indicates a line data transferred on the data bus 204. A line data latch circuit that simultaneously takes in the data bus, “206” denotes a data bus for transferring line data output from the line data latch circuit 205, 07 ”denotes a gradation voltage generation circuit that generates a gradation voltage from the data bus 206 and the reference gradation voltage 105, and“ 208 ”denotes a signal line group for transferring the gradation voltage generated by the gradation voltage generation circuit 207 ( (Hereinafter referred to as "drain line group").

[0005] In FIG. 4, reference numeral “401” denotes display data supplied from a system (not shown),
This is a data bus for transferring a synchronization signal. Symbol “402”
A control circuit that generates display data for driving the liquid crystal, a timing signal, and the like based on the display data and the synchronization signal transferred on the data bus 401 is attached. Hereinafter, similarly, “403” indicates the liquid crystal driver, and “404” and “40”
4 ′ ”is a scan driver,“ 405 ”is a power supply circuit,
“406” and “406 ′” indicate liquid crystal panels.
Further, “407” denotes a data bus for transferring liquid crystal display data and timing signals supplied from the control circuit 402 to the liquid crystal driver 403, and “408” denotes a scan driver 404.
"409" indicates a signal line for transferring an AC signal supplied to the power supply circuit 405. “410” indicates a signal line group (hereinafter, also referred to as a “drain line group”) for transferring a gradation voltage generated by the liquid crystal driver 403. “411”
Indicates a signal line group (hereinafter also referred to as a “gate line group”) for transferring a line selection / non-selection voltage generated by the scanning driver 404. “412” is the power supply circuit 405
And a power supply line for transferring the reference voltage of the line selection / non-selection voltage to the scan driver 404 generated in step (1). “4
“13” indicates a power supply line that transfers a voltage that is a reference of a grayscale voltage generated by the liquid crystal driver 403. “41”
"4" indicates a power supply line for supplying a voltage of the counter electrode of the liquid crystal panel 406. "418" indicates an additional capacitor, which is provided to prevent voltage leakage from the liquid crystal 417. "Indicates the additional capacitance 41 of the liquid crystal panel 406.
8 indicates a power supply line for supplying a voltage to the power supply line 8. “416”
Is a thin film transistor (Thi) that performs a switching operation.
n Film Transistor
T ”is abbreviated.)“ 417 ”indicates a liquid crystal, which is equivalently described as a capacitance in the drawing.

The detailed operation of the liquid crystal display shown in FIG. 4A will be described with reference to FIGS. Here, description will be made on the assumption that effective display data for 640 pixels is transferred to the liquid crystal driver.

When the display data fetch start signal 103 becomes valid, the shift register circuit 201
01, the latch signal group 202 is sequentially enabled according to the clock 102 synchronized with the display data to be transferred (see FIG. 3).

The data latch circuit 203 includes a data bus 1
01 is sequentially latched in accordance with the latch signal group 202 to acquire display data. Since the latch signal group 202 is generated in synchronization with the display data transferred through the data bus 101, the display data stored in the data latch circuit 203 appears on the data bus 204 as shown in FIG.

When the horizontal synchronizing signal 104 becomes valid, the line data latch circuit 205
Are simultaneously taken in via the data bus 204. The line data latch circuit 205
The acquired display data is transferred to the gradation voltage generation circuit 207 via the data bus 206. The gradation voltage generation circuit 207 generates a gradation voltage according to the display data, and outputs the generated gradation voltage from the drain line group 208.

When the display data for one horizontal line is stored in the line data latch circuit 205, the shift register circuit 201 and the data latch circuit 203 start the operation of taking in the display data of the next line. During the display, the above operation is sequentially repeated.

Here, referring to FIG. 4A, the manner in which the liquid crystal driver of the prior art performs a display operation will be described together with the description of the other drive circuits.

In FIG. 4A, a control circuit 402
The display data and the synchronization signal transferred from the system bus 401 are converted into display data for driving liquid crystal and various timing signals, and these are transferred to each unit. LCD driver 4
Numeral 03 sequentially displays display data and generates and outputs a gradation voltage corresponding to display data for one horizontal line. In addition,
The liquid crystal driver 403 is as described above with reference to FIGS.

The scanning driver 404 sequentially applies a selection voltage / non-selection voltage to the gate line group 411 in synchronization with the output of the gradation voltage. That is, when the liquid crystal driver 403 outputs a gradation voltage corresponding to the display data of the first line, the scanning driver 411 applies a selection voltage to the gate line connected to the first line. A non-selection voltage is applied to the other gate lines. Then, the TFT 416 in the pixel portion on the first line is in a selected state, and the drain line 410
Is applied to the liquid crystal 417 and the additional capacitance 418 of the pixels on the first line.

Subsequently, when the liquid crystal driver 403 outputs a gradation voltage corresponding to the display data of the second line,
A selection voltage is applied to the gate line connected to the second line. As a result, a gradation voltage is applied to the TFTs of the pixels on the second line in the same manner as for the first line. At this time, a non-selection voltage is applied to the gate lines of the first line and the other lines. As a result, the TFT 416 on the first line is turned off, and the electric charge stored in the liquid crystal 417 and the additional capacitor 418 (that is, the gradation voltage applied to them) is held in each pixel portion.

By repeating the above operation while sequentially changing the line to which the selection voltage is applied, it becomes possible to apply the gradation voltage corresponding to the display data for one screen to all the pixel portions.

The operation of the conventional liquid crystal display shown in FIG. 4B is basically the same as the operation of the liquid crystal display shown in FIG. 4A. However, in the liquid crystal panel 406 'used in the liquid crystal display of FIG.
Since the additional capacitance 417 of the pixel portion whose 416 is turned on is connected to two adjacent gate lines, there is a limitation that a selection voltage cannot be applied to two adjacent gate lines at the same time.

[0017]

In the conventional liquid crystal display, when the resolution of the input effective display data does not match the resolution of the liquid crystal panel, there is a problem that the screen becomes hard to see. This problem will be described in more detail with reference to FIG.

The example shown in FIG. 5 has 640 pixels in the horizontal direction,
This is a case where effective display data for 480 lines in the vertical direction is displayed on a liquid crystal panel having 1024 pixels in the horizontal direction and 768 lines in the vertical direction.

Since only display data of 640 pixels is transferred in the horizontal direction, the shift register circuit 201 (see FIG. 2) of the liquid crystal driver 403 validates only the latch signal group 202 of 640 pixels. Therefore, valid display data is not input to a portion corresponding to the subsequent latch signal group 202 in the data latch circuit 203, the line data latch circuit 205, and the gradation voltage generation circuit 207. For this reason, display becomes defective in a region where the latch signal is not valid.

Since only 480 lines of display data are transferred in the vertical direction, the display data of the next frame is transferred during the operation of selecting the gate line at the bottom of the display screen. I will. Therefore, there is a problem that an image to be displayed at the upper part of the screen in the next frame is displayed at the lower part of the screen in the frame.

An object of the present invention is to provide a liquid crystal display device which realizes good display by enlarging and displaying high-quality images when display data having a resolution lower than that of a liquid crystal panel is input.

[0022]

Means for Solving the Problems The present invention has been made to achieve the above-mentioned object, and the first aspect thereof is as follows.
A liquid crystal panel in which pixel units provided with liquid crystal are arranged in M rows and N columns, display data is input, and a liquid crystal application voltage corresponding to the input display data is generated to generate a voltage corresponding to the corresponding column of the display data A liquid crystal drive circuit to be applied to the pixel portion, and any one of the above rows are sequentially selected, a selection voltage is applied to the pixel portion of the currently selected row, and a pixel portion of the non-selected row is selected at that time. A scanning drive circuit for applying a non-selection voltage, wherein the liquid crystal drive circuit includes a plurality of drain signal lines for outputting the liquid crystal application voltage, and a plurality of storage elements provided for each of the drain signal lines. And each of the storage element systems captures and stores the display data at a timing separately determined for each of the storage element systems,
Storage means for simultaneously outputting the stored display data to each other; and a voltage generation circuit for converting the display data output from the storage means to the liquid crystal applied voltage. There is provided a liquid crystal display device characterized by taking in the display data.

In the storage element system for simultaneously taking in the display data, it is preferable that the corresponding drain lines are adjacent to each other.

It is preferable to have a changing means for changing the number of storage element systems to be taken in simultaneously with the display data.

According to a second aspect of the present invention, there is provided a liquid crystal panel in which pixel units having liquid crystal are arranged in M rows and N columns, a display data is input, and a liquid crystal application voltage corresponding to the input display data is applied. And a liquid crystal drive circuit for applying the same to the pixel section of the corresponding column of the display data, and sequentially selecting any of the above rows, and a selection voltage is applied to the pixel section of the currently selected row. A scan drive circuit that applies a non-selection voltage to a pixel portion of a row that is not selected at that time, the scan drive circuit simultaneously selects a plurality of rows, and selects the plurality of rows simultaneously. A liquid crystal display device characterized in that the selection voltage is applied to the pixel portion during the same period.

It is preferable that the simultaneously selected rows are adjacent to each other.

It is preferable that the scanning drive circuit has a selected row number changing means for changing the number of rows selected simultaneously.

According to a third aspect of the present invention, there is provided a liquid crystal panel in which pixel sections provided with liquid crystal are arranged in M rows and N columns, a display data is inputted, and a liquid crystal application voltage corresponding to the inputted display data is applied. And a liquid crystal drive circuit for applying the same to the pixel section of the corresponding column of the display data, and sequentially selecting any of the above rows, and a selection voltage is applied to the pixel section of the currently selected row. On the other hand, a scanning drive circuit for applying a non-selection voltage to a pixel portion of a row which is not selected at that time is provided, and the liquid crystal drive circuit performs arithmetic processing on display data adjacent in the horizontal direction to perform interpolation processing on the interpolation pixel. There is provided a liquid crystal display device having a first data generation circuit that generates display data and outputs the data after increasing the number of display data in the horizontal direction.

According to a fourth aspect of the present invention, there is provided a liquid crystal panel in which pixel units having liquid crystal are arranged in M rows and N columns, a display data is input, and a liquid crystal application voltage corresponding to the input display data is applied. And a liquid crystal drive circuit for applying the same to the pixel section of the corresponding column of the display data, and one of the above-mentioned rows is sequentially switched to n / m times of one horizontal cycle period (where n < (m, n, and m are integers) for each period, and a scanning drive for applying a selection voltage to a pixel portion of a row selected at that time and applying a non-selection voltage to a pixel portion of a row not selected at that time. The liquid crystal drive circuit generates display data of the interpolated pixel by performing arithmetic processing on n pieces of display data adjacent in the vertical direction, and generates a total of m pieces of display data adjacent in the vertical direction. Having a second data generating circuit for outputting. A liquid crystal display device is provided.

The liquid crystal drive circuit further increases the number of display data in the horizontal direction by performing arithmetic processing on the display data adjacent in the horizontal direction to generate display data of the interpolated pixels, thereby outputting the data. It is preferable to have one data generation circuit.

In the third and fourth aspects, the arithmetic processing multiplies a value of display data of an adjacent pixel by a coefficient predetermined for each pixel, and adds the result. Is preferred.

According to a fifth embodiment of the present invention, there is provided a liquid crystal having a liquid crystal and having a pixel portion arranged in M rows and N columns, and a plurality of row signal lines and column signal lines connected to the pixel portion. A panel, a liquid crystal control circuit that captures a synchronization signal of display data, generates a liquid crystal driving synchronization signal based on the synchronization signal, and sequentially selects one row of the liquid crystal panel according to the liquid crystal driving synchronization signal; All rows are selected at the same cycle as the display data for one screen is sent, a selection voltage is applied to the pixel section of the selected row via the row signal line, and the other pixel sections are A scanning drive circuit for applying a non-selection voltage, and storage means for capturing the display data in accordance with the liquid crystal drive synchronization signal and storing the display data, based on one row of display data stored in the storage means, Represents the display data A liquid crystal driving circuit for generating a liquid crystal application voltage for causing the display to be performed in the pixel portion to which the selection voltage is applied, and applying the liquid crystal application voltage to the pixel portion via the column signal line. The liquid crystal drive circuit applies a liquid crystal application voltage based on display data of the same one row to the pixel portion during a period in which the scanning drive circuit selects a plurality of predetermined adjacent rows. Is provided.

The operation will be described.

The operation of the first and second aspects will be described.

The liquid crystal driving circuit generates a liquid crystal applied voltage according to the input display data. Then, this is applied to the pixel portion of the corresponding column of the display data. That is, each of the storage element systems fetches and stores the display data at a timing separately determined for each. Then, the stored display data are output simultaneously. The voltage generation circuit converts the display data output by the storage means into a liquid crystal application voltage and outputs the same through a drain signal line.

The scanning drive circuit sequentially selects one of the rows. Then, a selection voltage is applied to the pixel portion of the row selected at that time. On the other hand, a non-selection voltage is applied to the pixel portion of the row not selected at that time.

In this case, some of the storage element systems take in the display data simultaneously with each other. Then
The same liquid crystal applied voltage is output from the drain lines corresponding to these storage element systems. An image can be enlarged in the horizontal direction by allowing the storage element systems corresponding to the drain lines adjacent to each other to simultaneously capture display data. The enlargement ratio can be adjusted by changing the number of storage element systems to be taken in simultaneously with the display data by the changing means.

Further, the scanning drive circuit simultaneously selects a plurality of rows, and applies a selection voltage to a pixel portion of the simultaneously selected rows.
Apply during the same period. By simultaneously selecting adjacent rows, the image can be vertically enlarged. If the number of rows to be selected at the same time is changed by the selected row number changing means,
You can adjust the magnification.

The operation of the third and fourth aspects will be described.

The liquid crystal driving circuit generates a liquid crystal applied voltage according to the input display data. Then, this is applied to the pixel portion of the corresponding column of the display data. in this case,
The first data generation circuit of the liquid crystal driving circuit increases the number of display data in the horizontal direction by performing arithmetic processing on display data adjacent in the horizontal direction to generate display data of the interpolated pixel (that is, the number of display data in the horizontal direction is increased). , After expanding in the horizontal direction). Further, the second data generation circuit generates display data of the interpolated pixel by performing arithmetic processing on n pieces of display data adjacent in the vertical direction, and outputs a total of m pieces of display data adjacent in the vertical direction. . As a result, the magnification can be increased by m / n times in the vertical direction. The arithmetic processing may be, for example, multiplying the display data value of an adjacent pixel by a coefficient predetermined for each pixel, and adding the result.

The scan driving circuit converts one of the rows into
Select sequentially and apply the selection voltage. In this case, the period during which one row is selected is multiplied by m / n in the vertical direction, so that one horizontal cycle period is multiplied by n / m (however,
n <m, where n and m are integers). At this time, a non-selection voltage is applied to the pixel portion of the row not selected.

[0042]

FIG. 1 shows a first embodiment of the present invention.
This will be described with reference to FIGS. 6, 7, 8, 9, and 10. FIG. 1 is a block diagram of the liquid crystal driver of the present invention, FIG. 6 is a timing chart showing the operation of the liquid crystal driver of the present invention, and FIG. 7 is a block diagram of the scan driver of the present invention. FIG. 8 is a timing chart showing the operation of the scanning driver of the present invention. FIG. 9 is a display example of the present invention. FIG. 10 is a display example in which the display example of the present invention is enlarged. In the present embodiment, a liquid crystal panel 406 having the configuration shown in FIG.

In the first embodiment, when the resolution of the input display data is smaller than the resolution of the liquid crystal panel,
The image is enlarged horizontally by the LCD driver.
The display is prevented from becoming defective by enlarging the image in the vertical direction by the scanning driver. The enlargement in the horizontal direction and the enlargement in the vertical direction are realized by completely different processes. Therefore, each will be described below.

First, the liquid crystal driver and the enlargement in the horizontal direction by the liquid crystal driver will be described.

In the liquid crystal driver, a shift register circuit 108, which will be described later, simultaneously activates a plurality of latch signal groups 109, thereby increasing the number of display data to be output to the liquid crystal panel and realizing horizontal expansion. ing. Less than,
This will be specifically described.

This liquid crystal driver, as shown in FIG.
Control circuit 106, shift register circuit 108, data latch circuit 110, line data latch circuit 112
And a gradation voltage generation circuit 114. These are connected to each other by a data bus for transferring display data, a signal line, and the like. In this specification, various types of signals may be referred to by attaching reference numerals to signal lines through which the signals are transmitted. For example, display data transmitted through the data bus 101 may be referred to as display data 101.

The control circuit 106 generates and outputs a control signal 107 for controlling the operation of the shift register circuit 108 based on the display data 101 and the horizontal synchronizing signal 104 generated every one horizontal period. . The control circuit 106 transmits the control signal 107 to the shift register circuit 1
08.

The shift register circuit 108 generates and outputs a latch signal group 109. The shift register circuit 108 generates the latch signal group 109 based on a control signal 107, a clock 102 synchronized with the display data 101, and a display data capture start signal (EI) 103. Shift register circuit 108 of the present embodiment
Can enable a plurality of latch signals 109 simultaneously. By simultaneously validating the plurality of latch signals 109, the number of display data to be output to the liquid crystal panel can be increased. That is, when display data having a resolution smaller than the resolution of the liquid crystal panel is input, it is possible to enlarge and display the data in the horizontal direction. The details of the shift register circuit 108 will be described later with reference to FIG.
7 will be described.

The data latch circuit 110 latches the display data 101 in accordance with the latch signal group 109. The data latch circuit 110 transfers the stored display data to the line data latch circuit 112 via the data bus 111. The data latch circuit 110
A plurality of latch circuits provided for each latch signal 109 are provided therein.

The line data latch circuit 112 latches the display data 111 at a timing determined based on the horizontal synchronizing signal 104 and outputs the latched display data 111 to the gradation voltage generation circuit 114 through the data bus 113.

The gradation voltage generation circuit 114 is connected to the data bus 1
A gradation voltage is generated based on the display data transferred through the signal line 13 and is supplied to a signal line group (hereinafter, “drain line group”).
) 115 to the liquid crystal panel. The reference gradation voltage 105 serving as a reference of the gradation voltage is input to the gradation voltage generation circuit 114.

The operation of the liquid crystal driver (see FIG. 1) will be described.

Here, it is assumed that the resolution of the display data 101 is smaller than the resolution of the liquid crystal panel. Specifically, the resolution of the input display data 101 is 640 dots in the horizontal direction and 480 lines in the vertical direction. The resolution of the liquid crystal panel is 1024 dots in the horizontal direction and 768 lines in the vertical direction.

The control circuit 106 outputs a control signal 107. In response, shift register circuit 108
It operates as shown in FIG. In FIG. 6, when the display data capture start signal 103 becomes valid (it is assumed to be valid at the “low” level here), the shift register circuit 108 synchronizes with the clock 102 and latches a group of latch signals 109-1. To 109-1024 are made valid sequentially. Here, the operation that differs from the conventional liquid crystal driver is
The point is that a plurality of latch signals 109 are simultaneously enabled.
That is, when the clock 102 becomes valid, the shift register circuit 108 first makes the latch signal 109-1 and the latch signal 109-2 valid at the same time. Therefore, in the data latch circuit 110, the same display data is stored in the latch circuit corresponding to the latch signal 109-1 and the latch circuit corresponding to the latch signal 109-2. As a result, the same display data is output to the data bus 111-1 and the data bus 111-2 in FIG.

Next time, when the clock 102 becomes valid, the shift register circuit 108 makes the latch signal 109-3 valid. Thus, the display data transferred through the data bus 101 at that time is latched in the latch circuit corresponding to the latch signal 109-3 in the data latch circuit 110. Then, the latched display data is output to the data bus 111-3.

Thereafter, when the shift clock 102 becomes valid again, the latch signal 109-4 and the latch signal 109- are set as in the case of the latch signals 109-1 and 109-2.
5 become effective at the same time. Then, similarly, the same display data is stored in the latch circuit corresponding to the latch signal 109-4 and the latch circuit corresponding to the latch signal 109-5 in the data latch circuit 110. Then, the same display data is output to the data buses 111-4 and 111-5.

During display, the shift register circuit 108 and the data latch circuit 110 sequentially repeat the above operation.

The line data latch circuit 112 simultaneously takes in the display data 111 for one horizontal line and outputs it to the data bus 113. Grayscale voltage generation circuit 114
Converts the display data 113 into a gray scale voltage, and outputs it from the drain line group 115 at the same time.

As described above, the input display data for one pixel can be developed into two pixels arranged in the horizontal direction on the liquid crystal panel. In the present embodiment, the ratio between the number of times that two adjacent latch signals 109 are simultaneously enabled and the number of times that one latch signal 109 is independently enabled is 1: 1. .5 times enlarged display becomes possible. The display data capture start position is determined by the display data capture start signal 10 described above.
3 is controllable.

Next, shift register circuit 108 will be described in more detail with reference to FIG.

For simplicity of explanation, here, five latch signal groups 109 are output. The reference numeral “3101” denotes a flip-flop, in which CK is a clock input,
D represents data input and Q represents data output. Reference numeral “3102” indicates a selector. Selector 310
2 is input to the flip-flop 3101. Note that the output of the flip-flop 3101 is the latch signal 109.

The shift register circuit 108 operates the selector 3 in response to the control signal 107 as described below.
The selection state of 102 changes. Selector 3102-1
Operates to select the display data capture start signal 103. Therefore, the flip-flops 3101-1 and 31-1
The data input to 101-2 is the display data capture start signal 103. As a result, the latch signals 109-1 and 109-2 become valid at the same timing (see FIG. 6).

The selector 3102-2 outputs the latch signal 10
It operates so as to select 9-2. Therefore, the latch signal 1
09-3 is a pulse delayed by one clock from the latch signal 109-2 (see FIG. 6).

The selector 3102-3 and the selector 310
2-4 operates to select the latch signal 109-3. Therefore, the latch signal 109-4 and the latch signal 109
-5 are both delayed by one clock from the latch signal 109-3 and become effective at the same timing as each other (see FIG. 6). As described above, the shift register circuit 10 of the present embodiment
8 controls a signal selected by each selector 3102 to enable a plurality of latch signals 109 at a time. As in the conventional example, the latch signal 109 is made valid sequentially for each clock, and
As shown in FIG. 1, it is also possible to simultaneously enable the adjacent latch signals 109 once every four clocks.

If the resolution of the display data 101 is the same as the resolution of the liquid crystal panel, the shift register circuit 10
8 operates similarly to the conventional example.

Next, the scanning driver and the enlargement in the vertical direction will be described.

In this scan driver, a shift register circuit 705 (see FIG. 7) described later
At the same time, a plurality of gate line groups 710 to be output to the liquid crystal panel are simultaneously selected. As a result, the number of lines of display data is increased to realize vertical enlargement. Hereinafter, a specific description will be given.

As shown in FIG. 7, the scan driver includes a shift register circuit 705, a level shifter circuit 707,
And a voltage selection circuit 709. Also, various signal lines 701, 702, 703, 704 connecting these, a bus 7
06, 708, 710 and the like.

The shift register circuit 705 includes a line scanning start signal 701, a line shift clock 702, and a control signal 70 for determining the operation of the shift register circuit 705.
3 has been entered. The shift register circuit 705 generates and outputs a shift clock group 706 based on these. Details of the shift register circuit 705 will be described later with reference to FIG.

The level shifter circuit 707 converts the voltage level of the shift clock group 706. The level shifter circuit 707 outputs the converted signal as a shift clock group 708.

The voltage selection circuit 709 selects one of the selection voltage / non-selection voltage input through the power supply line 704 for each line based on the shift clock group 708, and outputs the line selection / non-selection voltage to the signal line. The data is output to a liquid crystal panel through a group (hereinafter also referred to as a “gate line group”) 710.

The operation of the scanning driver will be described with reference to FIG.

The shift register circuit 705 controls the control signal 7
03. When the display data input through the data bus 101 in FIG. 1 is smaller than the resolution of the liquid crystal panel, the shift register circuit 705 operates as follows.

When the line scan start signal 701 becomes valid (in this case, it becomes valid at the “high” level), the shift register circuit 705 sequentially activates the shift clock groups 706-1 to 706-768. go.
Here, the operation differs from that of the conventional scanning driver in that a plurality of shift clocks 706 may be simultaneously enabled.

When the line shift clock 702 becomes valid for the first time after the line scan start signal 701 becomes valid, the shift register circuit 705 sets the shift clock 7
06-1 and the shift clock 706-2 are simultaneously enabled.

Next time, when the line shift clock 702 becomes valid, the shift register circuit 705 makes the shift clock 706-3 valid this time. After that, when the line shift clock 702 becomes valid, the shift register circuit 705 simultaneously makes the shift clock 706-4 and the shift clock 706-5 valid. The shift register circuit 705 performs the above operation by the line shift clock 702.
Is sequentially repeated each time becomes effective.

The level shifter circuit 707 converts the voltage level of the shift clock group 706, and
As 08, it is output to the voltage selection circuit 709. The voltage selection circuit 709 outputs a selection / non-selection voltage to the gate line group 710 according to the shift clock group 708. As a result, the selection voltage is simultaneously applied to the gate line 710 corresponding to the shift clock 706 that has been enabled at the same time. As a result, when the selection voltage is applied to the two gate lines 701 at the same time, the drain line 1
The gray scale voltage of the horizontal line transferred through the line 15 is simultaneously applied to the two lines.

In this embodiment, the ratio of the number of times that two gate lines are simultaneously enabled to the number of times that one gate line is independently enabled in the gate line group 701 is 1: 1. Therefore, 1.5 times enlarged display in the vertical direction is possible. The display start line position in the vertical direction can be adjusted by the line scanning start signal 701 described above.

The details of the shift register circuit 705 are shown in FIG.
This will be described with reference to FIG.

Here, for the sake of simplicity, five latch signal groups 706 are output. Symbol “320”
1 indicates a flip-flop, in which CK indicates a clock input, D indicates a data input, and Q indicates a data output. Reference numeral “3202” indicates a selector. An output 3203 of the selector 3202 indicates a flip-flop. Flop 3201
Has been entered. The output of the flip-flop 3201 becomes the above-described latch signal group 710.

The operation of the shift register circuit 705 will be described.

The shift register circuit 705 operates the selector 3 in response to the control signal 703 as described below.
The data selected by 202 changes.

The selector 3202-1 operates so as to select the line scanning start signal 701. Therefore, the flip-flops 3201-1 and 3201
-2 is the line display start signal 701. Therefore, the latch signal 706-1
And the latch signal 706-2 become valid at the same timing (see FIG. 8).

The selector 3202-2 outputs the latch signal 70
It operates to select 6-2. Therefore, the latch signal 7
06-3 is a pulse delayed by one clock from the latch signal 706-2 (see FIG. 8).

Selector 3202-3 and selector 320
2-4 operates to select the latch signal 706-3. Therefore, the latch signals 706-4 and 706
-5 are both delayed by one clock from the latch signal 706-3 and become effective at the same timing as each other (see FIG. 8).

As described above, the shift register circuit 705 of the present embodiment can simultaneously activate a plurality of latch signals 706 by controlling the signal selected by the selector 3202. The shift register circuit 705
Are sequentially latched signals 706 every clock as in the prior art.
, Or the adjacent latch signals 706 can be simultaneously enabled once every four clocks as shown in FIG.

If the resolution of the display data 101 is the same as the resolution of the liquid crystal panel, the shift register circuit 70
5 operates similarly to the conventional example.

FIGS. 9 and 9 show examples in which display data is processed by using both the horizontal enlargement processing (see FIGS. 1 and 6) and the vertical enlargement processing (see FIGS. 7 and 8). As shown in FIG.

The input display data of 640 dots in the horizontal direction and 480 lines in the vertical direction are converted into 960 dots in the horizontal direction (= 640 dots × 1.5 pixels) by the liquid crystal driver (FIG. 1).
Times). Further, 720 lines (= 400 lines × 1.5 lines) in the vertical direction are provided by the scanning driver (FIG. 7).
Times).

In this embodiment, the resolution of the liquid crystal panel is 1024 dots in the horizontal direction and 768 lines in the vertical direction. Therefore, the display data is insufficient even after the enlargement.
However, this can be dealt with by adjusting the display position on the display screen. That is, by displaying an image almost at the center of the liquid crystal panel, unnaturalness can be eliminated. The display position in the horizontal direction can be adjusted by enabling the display data capture start signal 103 during the horizontal blanking period. The display position in the vertical direction can be adjusted by enabling the line scan start signal 701 during the vertical blanking period.

In the display area where there is no display data, display data (generally, black display data) for the horizontal retrace period and the vertical retrace period is displayed.

The original display data before enlarged display is shown in FIG.
FIG. 10A shows the display data after the enlargement, while FIG. FIG. 10 shows an example in which the display data of the font “A” of 16 dots × 16 lines is enlarged. According to the present embodiment, this is expanded to font data of 24 dots × 24 lines.

As described above, according to the first embodiment, any enlarged display is possible.

The second embodiment of the present invention is shown in FIGS.
This will be described with reference to FIGS. 2, 13 and 14 and FIGS. 1 and 7 used in the first embodiment.

FIG. 11 is a timing chart showing the operation of the liquid crystal driver of the present invention, FIG. 12 is a timing chart showing the operation of the scan driver of the present invention, and FIG. 13 is a display example of the present invention. FIG. 14 is an enlarged display example of the display example of the present invention.

The second embodiment is an example in which the image is enlarged 1.25 times in both the horizontal and vertical directions. The enlargement method itself is the same as in the first embodiment, but the ratio at which a plurality of latch signal lines are simultaneously selected differs according to the difference in enlargement magnification. In the present embodiment, corresponding to the enlargement ratio of 1.25, the ratio of the number of times to select two adjacent latch signal lines 109 at the same time to the number of times to select one latch signal line is set. 1: 3.

The operation of the liquid crystal driver, that is, the enlargement in the horizontal direction will be described with reference to FIGS.

Here, a case where the resolution of the display data 101 is smaller than the resolution of the liquid crystal panel will be described. Specifically, it is assumed that the resolution of the display data 101 is 800 dots in the horizontal direction and 600 lines in the vertical direction. The resolution of the liquid crystal panel is 1024 dots in the horizontal direction and 7 in the vertical direction.
Assume that there are 68 lines.

The control circuit 106 includes the shift register circuit 1
08 to output a control signal 107 for controlling the operation. In response, the shift register circuit 108 operates as shown in FIG. In FIG. 11, when the display data capture start signal 103 becomes valid (it is assumed to be valid at the “low” level here), the shift register circuit 10 is activated.
8 is a latch signal group 109 synchronized with the clock 102.
-1 to 109-1024 are sequentially enabled. Here, as in the first embodiment, the shift register circuit 108 operates to simultaneously enable the plurality of latch signals 109. The difference from the first embodiment is that the ratio of the number of times that two latch signals 109 are simultaneously selected to the number of times that one latch signal 109 that is selected alone is selected is 1: 3. That is the point.

When the clock 102 first becomes valid after the display data capture start signal 103 becomes valid, the shift register circuit 108 first makes the latch signals 109-1 and 109-2 simultaneously valid. Therefore,
In the data latch circuit 110, the latch signal 109-1
And the same display data is stored in the latch circuit corresponding to the latch signal 109-2. As a result, the data bus 111 of FIG.
-1 and the data bus 111-2 transfer the same display data to each other.

Next, when the clock 102 becomes valid, the shift register circuit 108 outputs the latch signals 109-3,
09-4 and 109-5 are sequentially made effective one by one.
In response, display data transferred by the data bus 101 is sequentially latched by each latch circuit corresponding to the latch signals 109-3, 109-4, and 109-5 in the data latch circuit 110. Then, the latched display data is transferred to the data buses 111-3, 111-4, 111-5.
Is output to

Thereafter, when the shift clock 102 becomes valid again, the shift register circuit 108 outputs the latch signal 1 similarly to the case of the latch signals 109-1 and 109-2.
09-6 and the latch signal 109-7 are simultaneously enabled. Then, similarly, the latch circuit corresponding to the latch signal 109-6 in the data latch circuit 110 and the latch signal 109
The same display data is stored in the latch circuit corresponding to -7. And the data bus 11
The same display data is transferred to 1-6 and 111-7.

During display, shift register circuit 108 and data latch circuit 110 sequentially repeat the above operation.

The line data latch circuit 112 simultaneously takes in the display data 111 for one horizontal line and outputs it to the data bus 113. The gradation voltage generation circuit 114 takes in the display data 113 and converts it into a gradation voltage.
Then, this gradation voltage is output from the drain line group 115 at the same time.

Next, the operation of the scanning driver, that is, the enlargement in the vertical direction will be described with reference to FIGS.
Here, a case where the display data 101 is smaller than the resolution of the liquid crystal panel will be described.

The shift register circuit 705 controls the control signal 70
According to No. 3, the following operation is performed. When the line scan start signal 701 becomes valid (in this case, it becomes valid at the “high” level), the shift register circuit 7 is activated.
05 is a shift clock group 706-1 to 706-768
Are enabled in order. Here, the shift register circuit 7
05 is similar to the first embodiment in that a plurality of shift clocks 706 may be simultaneously enabled. However, this embodiment is different from the first embodiment in that the ratio of the number of times that two adjacent shift clocks 706 are simultaneously selected and the number of times that one shift clock 706 is independently selected is 1: 3 ( 1: 1 in the first embodiment). When the line clock 102 becomes valid for the first time after the line scan start signal 701 becomes valid, the shift register circuit 705
Are shift clock 706-1 and shift clock 706-
And 2 at the same time. Thereafter, each time the line shift clock 702 becomes valid, the shift register circuit 7
05 is a shift clock 706-3, 706-4, 70
6-5 are made effective sequentially. Further, thereafter, when the line shift clock 702 becomes valid, the shift register circuit 705 simultaneously makes the shift clock 706-6 and the shift clock 706-7 valid. During the display, the shift register circuit 705 sequentially repeats the above operation every time the line shift clock 702 becomes valid.

The level shifter circuit 707 converts the voltage level of the shift clock group 706 and outputs it to the voltage selection circuit 709 via the bus 708. Voltage selection circuit 70
Reference numeral 9 denotes a gate line group 7 according to the shift clock group 708.
A selection / non-selection voltage is output to 10.

FIGS. 13 and 14 show examples in which display data is processed by using both the horizontal enlargement processing (FIG. 11) and the vertical enlargement processing (FIG. 12) in the second embodiment. Was.

The input display data of 800 dots in the horizontal direction and 600 lines in the vertical direction are supplied by the liquid crystal driver (FIG. 1) to 1000 dots in the horizontal direction (= 800 dots × 1.2 dots).
5 times). Further, 750 lines (= 600 lines × 1.2 lines) in the vertical direction by the scanning driver (FIG. 7).
5 times).

In this embodiment, the resolution of the liquid crystal panel is 1024 dots in the horizontal direction and 768 lines in the vertical direction. Therefore, the display data is not enough even after the enlargement, but this can be dealt with by controlling the position where the image is displayed. As in the first embodiment, the display position in the horizontal direction can be adjusted by enabling the display data capture start signal 103 during the horizontal blanking period. The display position in the vertical direction can be adjusted by enabling the line scan start signal 701 during the vertical blanking period.

The original display data before enlarged display is shown in FIG.
FIG. 14A shows the display data after the enlargement, and FIG. FIG. 14 shows an example in which the display data of the font “A” of 16 dots × 16 lines is enlarged. According to the present embodiment, the font data is enlarged to 20 dots × 20 lines of font data.

If the resolution of the display data 101 is the same as the resolution of the liquid crystal panel, the shift register circuit 10
8, 705 operates in the same manner as before.

According to the above-described first and second embodiments, it is possible to display an enlarged image at an arbitrary magnification. The enlargement processing by the method described here can be applied to color display as it is.

In the enlargement processing in the first and second embodiments described above, display data for one pixel is simply enlarged to two pixels for a predetermined pixel. However, as a method of enlargement, there is a method of creating a pixel to be interpolated by adding a weighting process to adjacent pixel data. Examples in which the enlargement processing is performed in such a manner will be described later as third and fourth embodiments.

FIGS. 15, 16 and 1 show the third embodiment.
7, FIG. 18, FIG. 19, and FIG.

The enlargement process in the third embodiment is a method of creating a pixel to be interpolated by applying a weighting process to adjacent pixel data.

FIG. 15 is a block diagram of a liquid crystal driver of the present invention, FIG. 16 is a block diagram of a horizontal operation circuit of the liquid crystal driver of the present invention, and FIG. 17 is a block diagram of the liquid crystal driver of the present invention. FIG. 18 is a block diagram of the vertical direction operation circuit, FIG. 18 is a timing chart showing the operation of the liquid crystal driver of the present invention, FIG. 19 is a timing chart showing the operation of the scan driver of the present invention, and FIG.
Is an enlarged display example of the display example of the present invention. In the present embodiment, the liquid crystal panel 40 having the configuration shown in FIG.
Use 6.

Here, the input display data has a resolution of 640 dots in the horizontal solution direction and 480 lines in the vertical direction. The resolution is magnified 1.5 times and the resolution is 1024 dots in the horizontal direction and 768 lines in the vertical direction. It shall be displayed on the liquid crystal panel.

As shown in FIG. 15, the liquid crystal driver of the present embodiment comprises a control circuit 1102 and a horizontal operation circuit 11.
07, a shift register circuit 1110, a data latch circuit 1112, a line data latch circuit 1114,
A line data latch circuit 1118, a vertical operation circuit 1120, a data latch circuit 1123, a line data latch circuit 1125, and a line data selector 112;
7 and a gradation voltage generation circuit 1129. Further, various signal lines and data buses connecting these are provided.

The control circuit 1102 includes various control signals 110 for controlling other operations of the shift register circuit 1110.
3, 1104, 1105, and 1106. The control circuit 1102 controls the output control signal 110
1, a display data 101, a clock 102, a display data capture start signal 103, and a horizontal synchronization signal 104 are input, and the above-described various control signals are generated based on these signals. The output control signal 1101 is used to control the output timing of the gray scale voltage. Control signal 11
03 is for controlling the operation timing of the shift register circuit 1110. Operation control signal 1104
Is for controlling the arithmetic processing in the vertical direction, and is output to the vertical arithmetic circuit 1120. The output selection signal 1105 is for selecting a gradation voltage to be output, and is output to the line data selector 1127. The arithmetic control signal 1106 is for controlling the arithmetic processing in the horizontal direction, and is output to the horizontal arithmetic circuit 1107. The specific circuit configuration and the like of the control circuit 1102 will be described later with reference to FIG.

The horizontal operation circuit 1107 performs an enlargement process in the horizontal direction. The horizontal operation circuit 11
In the display data 07 after the enlargement processing, odd-numbered pixel data is passed through the odd-numbered pixel data bus 1108, while even-numbered pixel data is passed through the even-numbered pixel data bus 1108.
The output is performed separately through the control unit 109. Note that the odd-numbered pixel data is display data output to an odd-numbered pixel from the left (hereinafter, referred to as an “odd-numbered pixel”) on the liquid crystal panel. The even pixel data is
The display data is output to an even-numbered pixel from the left (hereinafter, referred to as “even-numbered pixel”) on the liquid crystal panel. Details of the horizontal operation circuit 1107 will be described later with reference to FIG.

The vertical operation circuit 1120 generates display data to be newly added at the time of enlargement in the vertical direction by interpolation. The vertical operation circuit 1
Reference numeral 120 denotes a configuration in which display data generated by interpolation is output to the data latch circuit 1123 through the odd-numbered pixel data bus 1121 and the even-numbered pixel data bus 1122. The details of the vertical operation circuit 1120 will be described later with reference to FIG.

The line data selector 1127 selects one of the display data 1119 and the display data 1126. The selection is made according to the output selection signal 1105 generated by the control circuit 1102. The line data selector 1127 uses the selected one via the data bus 1128 to generate the gradation voltage
9 has been transferred.

The operation of the entire liquid crystal driver (FIG. 15) will be described with reference to FIG.

In the present embodiment, for the sake of convenience of description, coefficients for calculating display data appearing on the data bus are not described.

The control circuit 1102 controls the various control signals 110
3, 1104, 1105, and 1106 are generated and output to each unit. Each unit operates as follows based on these control signals.

The horizontal operation circuit 1107 subjects the input display data to enlargement processing in the horizontal direction in accordance with the control signal 1106. Then, of the display data after the enlargement processing, odd-numbered pixel data is passed through the odd-numbered pixel data bus 1108, while even-numbered pixel data is
Latch circuit 111 through even pixel data bus 1109
Output to 2. The details of the horizontal enlargement process will be described later in detail with reference to FIG.

The shift register circuit 1110 outputs a latch signal group 1111 to the data latch circuit 1112 according to the control signal 1103.

Data latch circuit 1112 latches odd-numbered pixel data 1108 and even-numbered pixel data 1109 in accordance with latch signal group 1111. When display data for one horizontal line is stored in the latch circuit 1112, the line data latch circuit 1114 switches to the data bus 1
The display data input through 113 is stored at the same time. The line data latch circuit 1114 transfers the stored display data to the line data latch circuit 1118 via the data bus 1115. Also, the same display data is transferred to the vertical operation circuit 1120 through the odd pixel data bus 1116 and the even pixel data bus 1117.

The vertical operation circuit 1120 generates an interpolated pixel in the vertical direction based on the input display data. The vertical operation circuit 1120 transmits the generated display data of the interpolation pixel to the data buses 1121 and 112.
2 to the data latch circuit 1123 (see FIG. 18).

The data latch circuit 1123 sequentially latches display data according to a latch signal group 1111 generated by the shift register circuit 1110. When the display data for one horizontal line is stored in the data latch circuit 1123, the line data latch circuit 1125 simultaneously stores the display data sent from the data latch circuit 1123 via the data bus 1124. Then, the stored display data is transferred to the line data selector 1127 via the data bus 1126.

The line data selector 1127 has a line data latch circuit 111 via a data bus 1119.
8 has also been transferred. The line data selector 1127 selects one of the display data 1119 and the display data 1126 in accordance with the output selection signal 1105, and selects the selected one from the data bus 11
The data is transferred to the gradation voltage generation circuit 1129 through.

The gray scale voltage generation circuit 1129 generates a gray scale voltage based on the display data transferred through the data bus 1128. Then, the generated gray scale voltage is output to the liquid crystal panel through a signal line group (hereinafter also referred to as “drain line group”) 1130.

The operation of the line data selector 1127 will be described again with reference to FIG.

The line data selector 1127 controls the output period to be divided into three within the two input horizontal periods. The line data selector 1127 selects the display data that first appeared on the data bus 1119. Subsequently, the display data to which the arithmetic processing appearing on the data bus 1126 has been added is selected. Finally, the display data appearing on the data bus 1119 is selected. Line data selector 1127
Transfers the selected display data to the gradation voltage generation circuit 1129 via the data bus 1128.

By the series of operations described above, interpolation pixels are generated in the horizontal and vertical directions, and the enlargement processing of the liquid crystal driver can be realized.

Next, details of the horizontal operation circuit 1107 will be described with reference to FIG.

The horizontal operation circuit 1107 includes latch circuits 1601, 1603, 1611 and 1620, bit shift circuits 1605, 1607, 1614 and 1616,
Adders 1609 and 1618 and data selector 161
3,1622. Further, various signal lines and buses connecting these are provided.

Bit shift circuits 1605, 1607, 1
Reference numerals 614 and 1616 denote 1-bit shift circuits for converting display data input through the data bus into half display data.

In the horizontal operation circuit 1107, a process of generating odd-numbered pixel data and a process of generating even-numbered pixel data are performed in parallel.

First, the process of generating odd-numbered pixel data will be described.

The latch circuit 1601 is connected to the data bus 101
Latches the display data input through. The latch circuit 1601 transmits the latched display data to the data bus 1.
The data is transferred to the latch circuit 1603 and the bit shift circuit 1607 through 602. Further, the latch circuit 1603
Transfers the latched display data to the bit shift circuit 1605 via the data bus 1604. Both the bit shift circuit 1605 and the bit shift circuit 1607 output the input display data to the adder 1609 after bit-shifting the input display data. Adder 1609
Adds the display data input from the bit shift circuit 1605 and the display data input from the bit shift circuit 1607.

In this case, the display data input from latch circuit 1601 directly to bit shift circuit 1607 via data bus 1602 and the display data input to bit shift circuit 1605 via latch circuit 1603 and data bus 1604 take one clock cycle. There is a minute phase difference. Therefore, if the display data input to the bit shift circuit 1605 is X (n) and the display data input to the bit shift circuit 1607 is X (n + 1), the adder 1
The display data calculated and generated by 609 is ・ · X (n)
+ ／ · X (n + 1). That is, the adder 160
9 generates display data in which two horizontally adjacent pixels are weighted by １ ／.

The latch circuit 1611 temporarily stores the display data 1610 output from the adder 1609 and transfers it to the data selector 1613 via the data bus 1612.

Incidentally, the above-described latch circuit 1603
Also outputs the latched display data to the data selector 1613 via the data bus 1604.

The data selector 1613 is connected to the control circuit 11
02 (see FIG. 15), the display data 1604 and the display data 1612
And outputs it through the odd-numbered pixel data bus 1108.

FIG. 18 shows how display data is actually output to the odd-numbered pixel data bus 1108. The numbers described in the signals in FIG. 18 indicate the order of input through the data bus 101. For example, the display data “2” is input following the display data “1”. Also,
The display data “3 + 4” is the display data of the complementary pixel generated based on the display data “3” and the display data “4”. The display data “1” appearing on the display data bus 1108 is derived from the display data via the data bus 1604. The display data “2” is stored in the data bus 16
This is derived from the display data via the display unit 04. The display data “3 + 4” is derived from the display data via the data bus 1612.

The generation processing of the even-numbered pixel data will be described.

The latch circuit 1601 also transfers the latched display data to the bit shift circuit 1614 via the data bus 1602.

The display data transferred through the data bus 101 is directly sent to the bit shift circuit 1616.
Is also entered.

Both the bit shift circuit 1614 and the bit shift circuit 1616 output the input display data to the adder 1618 after bit-shifting the input display data. The adder 1618 includes the bit shift circuit 16
14 and the bit shift circuit 1
616 and the display data input from 616.

In this case, the display data input from the latch circuit 1601 to the bit shift circuit 1614 via the data bus 1602 and the display data input directly to the bit shift circuit 1616 via the data bus 101 have a phase difference of one clock. There is.

Therefore, the display data input to the bit shift circuit 1614 is represented by X (m),
16 is X (m + 1), the display data calculated by the adder 1618 is 1 /
2 · X (m) + ／ · X (m + 1). That is, the adder 1618 generates display data in which two pixels adjacent in the horizontal direction are weighted by 重 み.

The latch circuit 1620 temporarily stores the display data 1619 output from the adder 1618 and transfers the display data 1619 to the data selector 1622 via the data bus 1621.

By the way, the above-described latch circuit 1601
The latched display data is transferred to the data selector 1622 via the data bus 1602. The above-described latch circuit 1603 also transfers the latched display data to the data selector 1622 via the data bus 1604.

The data selector 1622 is connected to the data bus 1
The display data input through 604 and the data bus 1
The display data input through 602 and the data bus 1
621 is selected, and is output through the even-numbered pixel data bus 1109. The selection is made according to the control signal 1106.

FIG. 18 shows how display data is actually output to the even-numbered pixel data bus 1109. The display data “1 + 2” appearing on the display data bus 1109 is derived from the data bus 1621. The display data “4” is derived from the data bus 1604. The display data “3 + 4” is derived from the data bus 1602. The display data “4” is derived from the data bus 1604.

A control signal 1103 for controlling the operation of the shift register circuit 1110 is output according to the display data output to the data buses 1108 and 1109 in such an order and timing. And this control signal 1
According to 103, the shift register circuit 1110 outputs a latch signal group 1111. FIG. 18 also shows the state of the latch signal group 1111. Further, the latch circuit 1112 sequentially stores the display data 1108 and 1109 in accordance with the latch signal group 1111. The operation of the latch circuit 1112 is described in the timing chart of the data bus 1113 in FIG.

Next, details of the vertical operation circuit 1120 will be described with reference to FIG.

The vertical operation circuit 1120 includes bit shift circuits 1701, 1703, 1706, and 1708, and adders 1705 and 1710. Further, various signal lines and data buses are provided to connect these.

Bit shift circuits 1701, 1703, 1
Reference numerals 706 and 1708 denote the input display data by half.
This is a 1-bit shift circuit for converting the display data into a display data.

The operation of the vertical operation circuit 1120 is shown in FIG.
7 will be described.

Display data is input to the vertical operation circuit 1120 through the data buses 1116 and 1117. The display data is also directly input from the horizontal operation circuit 1107 through the data buses 1108 and 1109.

Of the constituent elements described above, generation of odd-numbered pixel data is performed by bit shift circuits 1701 and 1703 and an adder 1705.

The bit shift circuit 1701 performs a one-bit bit shift process on the display data input through the data bus 1108 to reduce the display data to half the display data. The bit shift circuit 1701 outputs the generated display data to the adder 1705 via the data bus 1702. On the other hand, the bit shift circuit 17
03 performs a 1-bit bit shift process on the display data input through the data bus 1116 to reduce the display data to half display data. The bit shift circuit 1703 transfers the generated display data to the data bus 1
The data is output to the adder 1705 through the 704.

In this case, data buses 1116 and 1117
Since the display data input through the data bus once passes through the line data latch circuit 1114, the data bus 11
The display data directly input from the horizontal operation circuit 1107 through 08 and 1109 is delayed by one horizontal line (see FIG. 18). The display data input to the bit shift circuit 1701 is Y (n), and the bit shift circuit 1
Assuming that the display data input to 703 is Y (n + 1), the display data 1121 output from the adder 1705 is
・ · Y (n) + ／ · Y (n + 1). In other words, display data in which two adjacent pixels are subjected to a weighting process of 1/2 is generated. Adder 170
5 is output through the data bus 1121.

On the other hand, the generation of the even-numbered pixel data is performed by the bit shift circuits 1706 and 1708 and the adder 1710. These apply the same processing to the display data sent through the even-numbered pixel data bus 1109 and the display data sent through the data bus 1117, and output through the even-numbered pixel data bus 1122.

The details of the control circuit 1102 will be described with reference to FIG.

The control circuit 1102 includes a register 3301
, A horizontal counter 3303, and a decoding circuit 33.
05, 3306, a vertical counter 3307, a decoder circuit 3309, a vertical counter 3310, and a decoder circuit 3312.

The register 3301 is connected to the display data bus 10.
1 is stored.
The control data can be transferred during a blanking period in which display data is not transferred.

The control data stored in the register 3301 is transferred to the decoder circuits 3305, 3306, 3309, 3312 through the control data bus 3302.

The counter 3303 includes a clock 102, a display data capture start signal 103, and a horizontal synchronization signal 104.
Working according to. The counter 3303 uses the count value as an output signal 3304 as a decoder circuit 33
05, 3306. Decoder circuit 3305
Generates a control signal 1103 based on these. Further, the decode circuit 3306 generates the operation control signal 1106.

The counter 3307 outputs the horizontal synchronization signal 104
It operates according to. Therefore, the counter 3307 operates in synchronization with the line cycle of the input display data. The counter 3307 outputs the count value to the output signal 330.
8 is output to the decoder circuit 3309. The decoder circuit 3309 determines the operation control signal 11 based on these.
04 is generated.

The vertical counter 3310 outputs the output control signal 1
It operates according to 101. Therefore, this counter 331
0 is not synchronized with the line cycle of the input display data,
It operates in synchronization with the line cycle of the output display data.
The counter 3310 outputs the count value to the output signal 33.
11 is output to the decoder circuit 3312. The decoder circuit 3312 outputs the output selection signal 1 based on these signals.
105 is generated.

Next, the scanning driver will be described with reference to FIGS.

As shown in FIG. 19, the scan driver of the present embodiment shifts the shift clock group 706 by dividing the input two horizontal periods into three horizontal periods. Then, the gate line group 710 is sequentially selected by the shifted shift clock group 706. The vertical zoom is
This is realized by cooperation between the above-described liquid crystal driver and the scanning driver.

The display state of the entire screen in this embodiment is the same as the display state of the first embodiment (see FIG. 9). However, a difference appears in a portion where fine characters and the like are displayed. As described above, in the present embodiment, pixel data to be interpolated is generated by adding arithmetic processing to two adjacent pixel data. Therefore, as shown in FIG. 20, in the interpolation of adjacent pixels of black and white, they are displayed as halftone display data. The thin lines do not become thicker or thinner, and the original display contents are accurately preserved (reproduced) even after the enlargement. In the present embodiment, enlargement processing can be easily performed even with low-resolution display data.

FIG. 21, FIG. 22, FIG.
3, and will be described with reference to FIGS.

FIG. 21 is a block diagram of a liquid crystal driver of the present invention, FIG. 22 is a block diagram of a horizontal direction calculating circuit of the liquid crystal driver of the present invention, and FIG. 23 is a block diagram of a vertical direction calculating circuit of the liquid crystal driver of the present invention. FIG. 24 is a timing chart showing the operation of the liquid crystal driver of the present invention, FIG. 25 is a timing chart showing the operation of the scan driver of the present invention, and FIG. 26 is a display example of the present invention. is there.

Here, the input display data (horizontal resolution direction 800 dots, vertical direction 600 lines) is enlarged by 1.25 times, and then 1024 dots in the horizontal direction and 7 in the vertical direction.
The image is displayed on a liquid crystal panel having a display area of 68 lines.

This liquid crystal driver includes a control circuit 2102
, A horizontal operation circuit 2108, a shift register circuit 2111, a data latch circuit 2113, a line data latch circuit 2115, and a vertical operation circuit 2119.
, A data latch circuit 2122, a line data selector 2124, a data latch circuit 2126, a line data latch circuit 2128, and a line data selector 21
30 and a gradation voltage generation circuit 2132. Further, various signal lines and buses connecting these are provided.

The control circuit 2102 controls the display data 101,
Various control signals 2103, 210 for controlling operations of the shift register circuit and the like based on the clock (CL2) 102, the display data capture start signal (EI) 103, the horizontal moving yellow signal (CL1) 104, and the output control signal 2101.
4, data selection signal 2105, output selection signal 2106,
The arithmetic control signal 2107 is generated. The control signal 2103 is output to the shift register circuit 2111. The arithmetic control signal 2104 is for vertical arithmetic processing, and is output to the vertical arithmetic circuit 2119. The data selection signal 2105 is for selecting display data, and is output to the data selector 2124. The output selection signal 2106 is for selecting a gradation voltage output from the liquid crystal driver, and is output to the line data selector 2130. The arithmetic control signal 2107 is for horizontal arithmetic processing, and is output to the horizontal arithmetic circuit 2108. The output control signal 2101 is for controlling the timing of the gradation voltage output from the liquid crystal driver. The control circuit 2
Details of 101 will be described later with reference to FIG.

The horizontal operation circuit 2108 performs an enlargement process in the horizontal direction. The horizontal direction operation circuit 2108 outputs the latch circuit 2113 and the vertical direction operation circuit through the odd pixel data bus 2109 for the odd pixel data and the even pixel data bus 2110 for the even pixel data among the display data after the enlargement processing. 2119. The details of the horizontal operation circuit 2108 will be described later with reference to FIG.
This will be described with reference to FIG.

The vertical operation circuit 2119 generates interpolation pixel data necessary for enlargement in the vertical direction. The vertical direction operation circuit 2119 outputs the generated interpolated pixel data to the latch circuit 2122 through the odd pixel data bus 2120 for an odd pixel and through the even pixel data bus 2121 for the even pixel. It has become. The details of the vertical operation circuit 2119 will be described later with reference to FIG.

FIG. 2 shows an outline of the operation in the fourth embodiment.
This will be described with reference to FIG.

Control circuit 2 of liquid crystal driver (see FIG. 21)
102 is various control signals 2103, 2107, 210
4, 2105, and an output selection signal 2106.

The horizontal operation circuit 2108 subjects the input display data to enlargement processing in the horizontal direction in accordance with the control signal 2107. Then, of the display data after the enlargement processing, the odd-numbered pixel data is passed through the odd-numbered pixel data bus 2109, while the even-numbered pixel data is passed through the even-numbered pixel data bus 2110, and the latch circuit 21.
13 and the vertical direction operation circuit 2119. The details of the horizontal enlargement process will be described later in detail with reference to FIG.

The shift register circuit 2111 outputs a latch signal group 2112 according to the control signal 2103. The data latch circuit 2113 controls the latch signal group 2
In accordance with 112, the display data sent through the data buses 2109 and 2110 are sequentially stored. FIG.
, This situation is described in the timing chart of the data bus 2114.

When the display data for one horizontal line is stored in the latch circuit 2113, the line data latch circuit 21
Reference numeral 15 simultaneously stores the display data transmitted through the data bus 2114. Then, the data bus 2
The data is transferred to the line data selector circuit 2124 via the line 116. Further, among the stored display data,
For odd pixel data, an odd pixel data bus 2117
And for the even-numbered pixel data through the even-numbered pixel data bus 2118,
Also forward to.

The vertical direction operation circuit 2119 stores the display data input through the data buses 2109 and 2110,
Based on the display data input through the data buses 2116 and 2117, an interpolation pixel in the vertical direction is generated. Then, this is connected to the data buses 2120 and 2121.
Through the latch circuit 2122. Regarding the operation of generating the interpolation pixel by the vertical direction operation circuit 2119,
This will be described later in detail with reference to FIG.

The latch circuit 2122 is connected to the data bus 212
0, 2121, are sequentially stored in accordance with the latch signal group 2112, and then stored on the data bus 2.
Output to the line data selector 2124 through 123.

Line data selector 2124 selects one of display data input from latch circuit 2122 and display data input from latch circuit 2115 in accordance with selection signal 2105. Then, the selected display data is transmitted through the data bus 2125.
The data is transferred to the line data latch circuit 2126 and the line data latch circuit 2128. Each of the line data latch circuits 2126 and 2128 transfers the stored display data to the line data selector 2130 through the data buses 2127 and 2129, respectively.

Line data selector 2130 sequentially selects one of display data transmitted through data bus 2127 and display data transmitted through data bus 2129 according to output selection signal 2106. Then, the selected display data is transferred to the data bus 21.
31 to the gradation voltage generation circuit 2132. The gray scale voltage generation circuit 2132 converts display data input through the data bus 2131 into a gray scale voltage, and outputs the gray scale voltage to the liquid crystal panel through the drain line group 2133.

The operation of line data selector 2124 will be described again with reference to FIG.

The display data calculated by the vertical calculation circuit 2119 is sequentially latched by the data latch circuit 2122.

When the display data transferred on the data bus 2116 is the first line data, the line data selector 2124 converts the first line data transferred via the data bus 2116 into the line data latch circuit 21.
26. Therefore, the first line data appears on the data bus 2127.

At this time, the line data selector 21
Reference numeral 24 transfers display data obtained by calculating data of the first line and data of the second line appearing on the data bus 2123 to the line data latch circuit 2128. Therefore, display data (described as “1 + 2”) obtained by calculating the data of the first line and the data of the second line appears on the data bus 2129.

When the display data transferred on the data bus 2116 is the second line data, the line data selector 2124 calculates the display data obtained by calculating the second line data and the third line data appearing on the data bus 2123. To the line data latch circuit 2126. Therefore, display data (described as "2 + 3") obtained by calculating the data of the second line and the data of the third line appears on the data bus 2127.

When the display data transferred on the data bus 2116 is the third line data, the line data selector 2124 calculates the display data obtained by calculating the third line data and the fourth line data appearing on the data bus 2123. To the line data latch circuit 2128. Therefore, the data of the third line and the fourth
Display data (described as “3 + 4”) obtained by calculating the data of the line appears.

When the display data transferred on the data bus 2116 is the fourth line data, the line data selector 2124 transfers the data of the fourth line appearing on the data bus 2116 to the line data latch circuit 2126. Therefore, the data of the fourth line (described as “4”) appears on the data bus 2127. This is sequentially repeated by each circuit.

By the series of operations described above, interpolation pixels in the horizontal and vertical directions are generated, and the enlargement processing of the liquid crystal driver can be realized.

The details of the horizontal operation circuit 2108 are shown in FIG.
This will be described with reference to FIG.

The horizontal direction operation circuit 2108 includes the latch circuits 2201, 203, 2211 and the bit shift circuit 2
205, 2207, 2214, 2216 and the adder 22
09, 2218 and data selectors 2213, 2220
Consists of Further, various signal lines and buses connecting these are provided.

In the horizontal operation circuit 2108, the process of generating odd-numbered pixel data and the process of generating even-numbered pixel data are performed in parallel. In the present embodiment, for the sake of simplicity, the coefficients calculated on the display data appearing on the data buses 2109 and 2110 are not described.

First, the process of generating odd-numbered pixel data will be described.

The latch circuit 2201 is connected to the data bus 101
And latches the display data inputted through the data bus 2202 and outputs it to the bit shift circuit 2205 through the data bus 2202.

The display data input through the data bus 101 is also input directly to the bit shift circuit 2207. Both bit shift circuits 2205 and 2207 perform predetermined bit shift control on the generated pixel data, and then adder 22 through data buses 2206 and 2208.
09 is output. The adder 2209 generates display data by adding the display data input from the bit shift circuit 2205 and the display data input from the bit shift circuit 2207.

In this case, the display data input to the bit shift circuit 2207 via the data bus 101 and the display data input to the bit shift circuit 2205 via the latch circuit 2201 and the data bus 2202 are:
There is a phase difference of one clock. In addition, the bit shift circuits 2205 and 2207 perform predetermined bit shift control on the input display data, thereby generating five pixel data from the four pixel data. Using this, display data of three interpolation pixels is generated. X (n), X (n + 1), X (n + 2), X (n + 3) represent display data sequentially input through the data bus 101.
Then, the display data generated by the adder 2209 is as follows.

1 / 4.X (n) + 3 / 4.X (n +
1) ・ · X (n + 1) + ／ · X (n + 2) 3/4 · X (n + 2) + ／ · X (n + 3) That is, に, 、, 3/4
Will be generated.

The bit shift circuit according to the present embodiment can multiply pixel data by １ ／, ４ and ／. To multiply pixel data by 1/4, 2
What is necessary is just to bit-shift. In order to multiply the pixel data by １ ／, the pixel data may be shifted by one bit. To multiply the pixel data by 3/4, the data shifted by 2 bits and the data shifted by 1 bit may be added. The bit shift circuit in this embodiment refers to a circuit having these functions.

[0211] The adder 2209 outputs the generated display data of the interpolated pixel to the latch circuit 2211. The latch circuit 2211 temporarily stores the display data, and
The data is transferred to the data selector 2213 through 212.

Incidentally, the latch circuit 2201 also outputs the latched display data to the latch circuit 2203 via the data bus 2202. And the latch circuit 2
203 transfers the stored display data to the data selector 2213 via the data bus 2204.

The data selector 2213 is connected to the data bus 2
One of the display data transferred via the lines 204 and 2212 is selected according to the operation control signal 2107 and output to the odd-numbered pixel data bus 2109. The state of the selection by the data selector 2213 is shown in FIG. The display data “1” appearing on the display data bus 2118 is derived from the data bus 2204. Display data "2
“+3” is derived from the display data via the data bus 2212. The display data “4” is from the data bus 220.
4 derived from the display data. The display data “5 + 6” is derived from the display data via the data bus 2212. The display data “7 + 8” is derived from the display data via the data bus 2212.

The processing for the even-numbered pixels will be described.

The latch circuit 2201 is connected to the data bus 101
After latching the display data inputted through the data bus 2202, the data is also transferred to the bit shift circuit 2214 through the data bus 2202. The bit shift circuit 2114 performs predetermined bit shift control on the input display data, and outputs the display data to the adder 2218 through the data bus 2215. The display data input through the data bus 101 is also input directly to the bit shift circuit 2216. The bit shift circuit 2116 performs predetermined bit shift control on the input display data, and outputs the display data to the adder 2218 via the data bus 2217. The adder 2218 includes the display data 2215 and the display data 2217.
, And outputs the result to the data selector 2220 via the data bus 2219.

In this case, the display data directly input to the bit shift circuit 2216 from the data bus 101 and the display data input to the bit shift circuit 2214 via the latch circuit 2211 and the data bus 2202 are equivalent to one clock. There is a phase difference. X (m), X
Assuming that (m + 1), X (m + 2), and X (m + 3), the display data generated and output by the adder 2218 is 以下, ２, ／ of the two adjacent pixels as follows. The weighting process is performed.

1 / 4.X (m) + 3 / 4.X (m +
1) 1 / 2.X (m + 1) + 1 / 2.X (m + 2) 3 / 4.X (m + 2) + ／. X (m + 3) Thus, even-numbered pixel data is 3 in the same manner as odd-numbered pixel data. One interpolated pixel data is generated.

Incidentally, the latch circuit 2201 transfers the stored display data to the data selector 2220 via the data bus 2202.

Data selector 2220 is connected to data bus 2
Any of the display data input through 212, 2202, and 2219 is appropriately selected, and is output to the latch circuit 2113 through the even-numbered pixel data bus 2110. FIG. 24 shows the state of selection by the data selector 2220. Display data “1” appearing on the display data bus 2110
+2 "is derived from the data bus 2212. Display data" 3 + 4 "is derived from the data bus 2219. Display data" 5 "is derived from the data bus 2202. Display data" 6 + 7 " Is derived from the data bus 2219. The display data “8” is derived from the data bus 2202.

Next, details of the vertical direction operation circuit 2119 will be described with reference to FIG.

The display data via the data buses 2109 and 2110 and the display data via the data buses 2117 and 2118 are input to the vertical operation circuit 2119.

Since the display data input through the data buses 2117 and 2118 has once passed through the line data latch circuit 2115 (see FIG. 21), the display data input through the data buses 2109 and 2110 is one horizontal line. Delay by line.

The display data via the data bus 2109 is bit-shifted by the bit shift circuit 2301 and transferred to the adder 2305 via the data bus 2302. Similarly, the display data via the data bus 2117 is bit-shifted by the bit shift circuit 2303 and transferred to the adder 2305 via the data bus 2304. The adder 2305 adds the input display data and outputs the result to the latch circuit 2122 (see FIG. 21) through the data bus 2120. Here, the display data input to the vertical operation circuit 2119 is represented by Y (n), Y (n + 1), Y (n).
+2) and Y (n + 3), the odd-numbered pixel data bus 2
The display data output through 120 is display data obtained by performing weighting processing of 隣接, ２, and ／ on two adjacent pixels as described below.

1 / 4.Y (n) + 3 / 4.Y (n +
1) 1 / 2.Y (n + 1) + 1 / 2.Y (n + 2) 3 / 4.Y (n + 2) + ／. Y (n + 3) Thus, the vertical operation circuit 2119 is similar to the horizontal operation circuit. In addition, three interpolation pixels are generated from the four pixels.

The same processing is performed by the bit shift circuits 2306 and 2308 and the adder 2310 on the data of the even-numbered pixels input through the data buses 2120 and 2118. Then, the vertical interpolation pixel data of the generated even-numbered pixel display data is output to the latch circuit 2120 through the even-numbered pixel data bus 2121.

Details of control circuit 2102 will be described with reference to FIG.

The control circuit 2102 includes a register 3401
, A horizontal counter 3403 and a decoding circuit 34
05, 3406, 3409, 3412, 3413 and vertical counters 3407, 3410.
Further, various signal lines and buses connecting these are provided.

The register 3401 is connected to the display data bus 10
1 is stored. still,
The control data can be transferred during a blanking period in which display data is not transferred. The register 3401 transmits the stored control data through the control data bus 3402.
Decoder circuits 3405, 3406, 3409, 341
2, 3413.

The counter 3403 includes a clock 102, a display data capture start signal 103, and a horizontal synchronization signal 104.
Working according to. The counter 3403 outputs the count value as an output signal 3404 to the decoder circuit 340.
5, 3406. The decoder circuit 3405 generates a control signal 2103 based on these. The decoder circuit 3406 generates a control signal 2107 based on these.

The counter 3407 outputs the horizontal synchronization signal 104
It works according to. Therefore, the counter 3407 operates in synchronization with the line cycle of the input display data. The counter 3407 outputs the count value to the output signal 3408.
Is output to the decoder circuit 3409. The decoder circuit 3409 calculates the operation control signal 2 based on these.
Generate 104.

The counter 3410 outputs the output control signal 2101
It works according to. Therefore, this counter 3410 operates not in synchronization with the line cycle of the input display data, but in synchronization with the line cycle of the output display data. The counter 3410 outputs the count value as an output signal 3411 to the decoder circuits 3412 and 3413. The decoder circuit 3412 generates the data selection signal 2105 based on these. Also, the decoding circuit 341
3 generates an output selection signal 2106.

Next, the scan driver will be described with reference to FIGS.

The basic configuration of the scanning driver is the same as that shown in FIG. However, this scanning driver divides the input four horizontal periods into five horizontal periods, and shifts the shift clock group 706 as shown in FIG. Then, the gate lines 710 are sequentially selected as shown in the figure in accordance with the shift clocks 706. By combining this with the liquid crystal driver of the present embodiment, an enlarged display in the vertical direction can be realized.

The display state of the entire screen in the fourth embodiment is the same as that in the second embodiment (see FIG. 13). However, there is a difference when fine display characters and the like are displayed. Pixel data to be interpolated as described above is
Since the pixel data is generated by performing arithmetic processing on the basis of two adjacent pixel data, it is displayed as halftone display data by interpolation of adjacent pixels of black and white (see FIG. 26). Therefore, the thin line does not become thick or thin. That is, the display data is accurately stored (reproduced) even after the enlargement.

In the third and fourth embodiments described above, arbitrary enlargement processing can be easily performed even with low-resolution display data. The same applies to color display.

In the third and fourth embodiments, adjacent pixel data is operated by the horizontal operation circuit and the vertical operation circuit. However, if the processing of transferring one pixel data without performing the arithmetic processing is performed, the same display result as in the first and second embodiments can be obtained.

Next, a fifth embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIGS.

Also in the fifth embodiment, an enlarged display of 1.5 times is performed as in the first embodiment. However, in the first embodiment, a plurality of gate lines are simultaneously selected to perform vertical enlargement, whereas in the fifth embodiment, the gate lines are selected one by one, and the gradation of the drain line is selected. Vertical expansion is performed by adjusting the timing of the voltage.

FIG. 31 is a configuration diagram of a liquid crystal display according to the fifth embodiment of the present invention.

In FIG. 31, the liquid crystal display includes a control circuit 4902 for generating display data for driving liquid crystal and various timing signals, a liquid crystal panel 4906, a liquid crystal driver 4903 for generating a gray scale voltage, a line selection voltage and A scan driver 4904 for generating a non-selection voltage,
A power supply circuit 4905 for generating a voltage for driving the liquid crystal.

The control circuit 4902 has a data bus 4901
Various kinds of timing signals for driving the liquid crystal are generated based on display data supplied from a system (not shown) via the CPU and a synchronization signal thereof. In the liquid crystal panel 4906, a pixel portion including a thin film transistor (TFT) 4911, a liquid crystal 4912, and an additional capacitor 4913 is arranged. In each pixel portion, when the TFT 4911 is turned on by a selection voltage supplied through the gate line group 4909, a gradation voltage supplied through the drain line group 4908 and a voltage supplied through the power supply line 4910 And liquid crystal 9
12 and the additional capacitor 913, and a gradation display corresponding to the potential difference is performed. In the liquid crystal panel 4906, the additional capacitance 4 of the pixel portion in which the TFT 4911 was turned on.
Since 913 is connected to two adjacent gate lines, the selection voltage cannot be simultaneously applied to two adjacent gate lines. The power supply circuit 4905 generates a voltage used by the liquid crystal driver 4903 and the scan driver 4904 to generate a line selection voltage and a grayscale voltage, and inverts the polarity of the voltage according to the AC signal of the signal line 4907.

FIG. 32 shows a block configuration of the liquid crystal driver 4903.

In FIG. 32, a liquid crystal driver 4903
Is a shift register circuit 4109 that performs timing generation.
And a control circuit 41 for controlling the operation of the shift register circuit.
07, and a data latch circuit 411 that captures, stores, and outputs display data for one line of the liquid crystal panel in pixel units.
1, a line data latch circuit 4113, a line data latch circuit 4115, and a gradation voltage generation circuit 4117.

The liquid crystal driver 4903 receives the display data 4101 and the display data 4 from the control circuit 4902 of FIG.
A clock 4102 for giving a transfer timing 101, a display data capture start signal 4103, a data horizontal synchronization signal 4104 having a cycle of one horizontal period of display data as a cycle, and a scanning horizontal synchronization signal 4106 synchronized with a scanning cycle of a scanning driver (described later). Supplied. Shift register circuit 410
9 generates a latch signal group 4110 for giving the storage position and the storage timing of the display data based on these signals, and outputs it to the data latch circuit 4111. Latch signal group 411
Reference numeral 0 denotes the same number of latch signals as the drain line groups of the liquid crystal panel 4906. A latch circuit for each pixel is arranged in the data latch circuit 4111 corresponding to each latch signal. The data latch circuit 4111 includes a latch signal group 411
0, the display data 4101 to be transferred is sequentially stored, and the stored display data is output to the data bus 4112. The line data latch circuit 4113 is connected to the data bus 4
The data on 112 is fetched and stored all together at the timing of the synchronization signal 4104, and the stored display data is output to the data bus 4114. Line data latch circuit 4115
Transmits the data on the data bus 4114 to the synchronization signal 4105
At the same time, the data is fetched and stored all at once, and the stored display data is output to the data bus 4114. The gradation voltage generation circuit 4117 selects a gradation voltage corresponding to the display data on the data bus 4114 from the reference gradation voltage 4105, and outputs the selected gradation voltage to the drain line group 4118.

The details of the shift register circuit 4109 will be described with reference to FIG. FIG. 33 shows a portion related to generation of five latch signals in the configuration of the shift register circuit 4109, that is, flip-flops (FF) 4701-1 to 4701-5 forming a shift register, and F
Shown are selectors 4702-1 and 4702-4 for switching inputs of F4701-2 and 4701-5. Each FF
Reference numeral 4701 captures and holds data input to the D terminal at the timing of the clock 4102 input to the CK terminal, and outputs the data from the Q terminal. The output of the Q terminal of each FF 701 is output as a latch signal group 4110. In the above configuration, the effective level of the display data capture start signal 4103 is synchronized with the display data clock 4102, first, FF4701-1 and 4701-2, then FF4701-4, and then FF4701-4 and 470.
It is shifted in the order of 1-5. Thereby, the clock 41
In one of the two periods 02, two latch signals are simultaneously at the effective level. Note that the state of the selector 702 is switched by the switching signal 4108, and
The output of the 4701-5 can be sequentially set to an effective level one by one.

FIG. 34 shows the configuration of the scanning driver.

In FIG. 34, the scan driver comprises a shift register circuit 4804 and a level shifter circuit 4806
And a voltage selection circuit 4808. The shift register circuit 4804 has as many shift clock groups 4805 as the number of gate lines 4804 of the liquid crystal panel 4906 as outputs, and when the line scan start signal 4801 becomes an effective level, the shift register circuit 4804 follows the line shift clock 4802.
The shift clock group 4805 is sequentially set to an effective level one by one from the head. This shift clock group 4805 has its voltage level converted by the shift register circuit 4804,
The voltage is supplied to the voltage selection circuit 4808. Voltage selection circuit 48
08 selects a selection voltage or a non-selection voltage corresponding to the voltage level of each shift clock of the supplied shift clock group from the voltage supplied from the power supply line 4803, and outputs the selected voltage to the gate line group 4909. At this time, the voltage selection circuit 4
Reference numeral 808 outputs a selection voltage to a gate line corresponding to a shift clock of an effective level, and outputs a non-selection voltage to other gate lines.

Next, the operation of the liquid crystal display of this embodiment will be described with reference to FIGS. FIGS. 35 and 36 are timing charts showing the operation of the liquid crystal display.

Here, similarly to the first embodiment, the resolution of the liquid crystal panel 4906 is 1024 dots in the horizontal direction and 768 lines in the vertical direction, and the resolution of input display data is 640 dots in the horizontal direction and 480 lines in the vertical direction. .

As shown in FIG. 35, in the liquid crystal driver of FIG. 32, when the display data fetch start signal 4103 becomes a valid level (“low” level), the shift register circuit 109 starts operating. The shift register circuit 109, which has started operation, first synchronizes with the clock 4102,
The latch signals 4110-1 and 4110-2 are made valid at the same time, then the latch signal 4110-3 is made valid, and thereafter, similarly, the latch signal 4110 is made valid sequentially in units of two and then one. Thereby, the data latch circuit 41
11, first, latch signals 4110-1 and 4110-
The same display data is simultaneously stored in the latch circuit corresponding to No. 2 and then the next display data is stored in the latch circuit corresponding to the latch signal 4110-3. Thus, in the data latch circuit 4111, display data in which the display data 4101 is partially duplicated is stored. Data latch circuit 4
The display data 111 is simultaneously captured and stored in the line data latch circuit 4113 by the data horizontal synchronization signal 4104. The display data of the line data latch circuit 4113 is stored in the line data latch circuit 4115 by the synchronization signal 4105. Then, a gray scale voltage based on the display data of the line data latch circuit 4115 is output to the drain line group 4118. The display data capture start position is determined by the display data capture start signal 410.
3 can be changed.

On the other hand, in the scan driver 4904 shown in FIG. 34, as shown in FIG.
When 801 becomes valid, the selection voltage is output to the gate line of the first horizontal line in the gate line group 4809, and the non-selection voltage is output to the other gate lines. Then, the gate line from which the selection voltage is output sequentially shifts from the first gate line to the last gate line in synchronization with the shift clock 4802. Here, the shift clock 48
02 is synchronized with the scanning horizontal synchronizing signal 4106 supplied to the line data latch circuit 4115 of the liquid crystal driver 4903, and every time the gate line to which the selection voltage is output shifts, the gradation voltage output from the liquid crystal driver 4903 is shifted. Is also updated. However, the data horizontal synchronization signal 4104 of the line data latch circuit 4113 has a cycle 1.5 times the cycle of the scanning horizontal synchronization signal 4106 of the line data latch circuit 4115. Therefore, when the frame start synchronization signal 4801 becomes valid, the liquid crystal driver 4903 outputs a gray scale voltage based on the same one line of display data L (1) in the first two cycles of the scanning horizontal synchronization signal 4106. ,
In the next one cycle, a gradation voltage based on the next one line of display data L (2) is output. Accordingly, in the pixel units on the first and second rows, the display data L for the same one line is displayed.
The display based on (1) is performed, and the display based on the next one line of display data L (2) is performed in the pixel unit on the third row. Thereby, 640 dots, 4
The display represented by the display data of 80 lines is enlarged 1.5 times in the horizontal and vertical directions, respectively. This display is the same as the display described with reference to FIGS. 9 and 10 in the first embodiment.

In the liquid crystal display of this embodiment, when the resolution of the image represented by the input display data 4101 is the same as the resolution of the liquid crystal panel 4906,
By switching the state of the selector 4702 of the shift register shown in FIG. 33, normal display at the same magnification can be performed. Further, as the shift register circuit 4108, a shift register circuit capable of arbitrarily switching the input of each FF described with reference to FIGS. 27 and 28 is used, and the timing of the latch signal group 4109 generated by the shift register circuit and the data horizontal By changing the timing of the synchronizing signal 4104 and the scanning horizontal synchronizing signal 4106, enlarged display at an arbitrary magnification becomes possible. Also, in a color display, an enlarged display can be similarly performed.

Next, a sixth embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIGS.

This embodiment performs 1.25-times enlarged display similarly to the second embodiment, and has the same configuration as the fifth embodiment except for a shift register of a liquid crystal driver.

FIG. 37 is a block diagram of a shift register of a liquid crystal driver 4903 according to the sixth embodiment.
This figure shows a configuration related to generation of eight latch signals,
That is, flip-flops (FF) 4701-1 to 4701-8 forming shift registers and FF 4701
Selector 470 for switching the input of −2, 4701-7
2-1 and 4702-6 are shown. The functions of each FF and selector are the same as those described with reference to FIG. FIG.
In the configuration of FIG.
Is first taken into the FFs 4701-1 and 4701-2 in synchronization with the clock 4102 of the display data, and thereafter, the FFs 4701-1 and FF4701-
4, FF4701-5 are sequentially taken in order, and then FF
It is simultaneously incorporated into 4701-6 and 4701-7. As a result, in one cycle of the four cycles of the clock 4102, two latch signals are simultaneously set to the effective level. In this shift register, as in the fifth embodiment, the state of the selector 702 is switched and the FF 4701 is switched.
The outputs of -1 to 4701-8 can be sequentially set to the effective level one by one.

FIGS. 38 and 39 are timing charts showing the operation of the liquid crystal display of this embodiment.

Hereinafter, as in the second embodiment, the resolution of the liquid crystal panel 4906 is 1024 dots in the horizontal direction and 768 lines in the vertical direction, and the resolution of input display data is 800 dots in the horizontal direction and 600 lines in the vertical direction.
The operation of the liquid crystal display will be described.

As shown in FIG. 38, the liquid crystal driver performs the fifth operation except that the same display data is stored in two latch circuits in the data latch circuit 4111 once every four cycles of the clock 4102. Operates similarly to the embodiment (see FIG. 35).

In the data latch circuit 4111, first, the latch signals 4110-1 and 4110-1
The same display data is simultaneously stored in the latch circuits corresponding to 110-2, and thereafter, latch signals 4110-3, 411
Display data is sequentially stored in the latch circuits corresponding to 0-4 and 110-5. By this repetition, the data latch circuit 4111 stores display data obtained by partially duplicating the display data 4101 for one line. The display data of the data latch circuit 4111 includes the data horizontal synchronization signal 41
04, the line data latch circuit 4113 simultaneously captures and stores the data.
Is stored in the line data latch circuit 4115 by the synchronization signal 4105. Then, a gray scale voltage based on the display data of the line data latch circuit 4115 is output to the drain line group 4118.

On the other hand, as shown in FIG. 39, the scanning driver sets the data horizontal synchronizing signal 4104 of the line data latch circuit 4113 to 1.25 times the cycle of the scanning horizontal synchronizing signal 4106 of the line data latch circuit 4115. Except for this, the same operation as in the fifth embodiment (see FIG. 35) is performed.

When the frame start synchronization signal 4801 becomes valid, a selection voltage is output to the first gate line in the gate line group 4809, and a non-selection voltage is output to the other gate lines. Then, the gate line from which the selection voltage is output sequentially shifts from the first gate line to the last gate line in synchronization with the shift clock 4802. Here, the shift clock 4802 is synchronized with the scanning horizontal synchronization signal 4106 supplied to the line data latch circuit 4115 of the liquid crystal driver 4903, and every time the gate line to which the selection voltage is output shifts, The output gradation voltage is also updated. However,
Since the data horizontal synchronization signal 4104 of the line data latch circuit 4113 has a cycle 1.25 times the cycle of the scanning horizontal synchronization signal 4106 of the line data latch circuit 4115, when the frame start synchronization signal 4801 becomes valid, the liquid crystal driver 4903 is a scanning horizontal synchronization signal 410
6 in the first two cycles, the display data L for the same one line
A gray scale voltage based on (1) is output, and display data L (2), L (3), L
A gradation voltage based on (4) is output. As a result, the display represented by the display data of 640 dots and 480 lines is displayed on the liquid crystal panel in the horizontal and vertical directions by 1.2 times respectively.
The display is magnified 5 times. This display is the same as the display described with reference to FIGS. 13 and 14 in the second embodiment.

In the liquid crystal display of this embodiment, if the resolution of the image represented by the input display data 4101 is the same as the resolution of the liquid crystal panel 4906,
By switching the state of the selector 4702 of the shift register shown in FIG. 37, normal display at the same magnification can be performed. Further, similarly to the fifth embodiment, the present invention can be applied to a liquid crystal display that performs enlarged display at an arbitrary magnification or color display.

As described above, in the fifth and sixth embodiments, the image represented by the low-resolution display data can be enlarged and displayed normally. Since gate lines are sequentially selected one by one, a display panel in which a plurality of gate lines cannot be selected at the same time can be used.
Inexpensive conventional scan drivers can also be used.

[0264]

As described above, according to the present invention, even when the resolution of the input display data is lower than the resolution of the liquid crystal panel, a natural display can be realized by enlarging the display data. In this case, by giving a weight when generating the interpolated pixel, a higher quality enlarged display is possible.

Further, since the enlargement processing is performed by the liquid crystal driver and the scanning driver, it is not necessary to change the conventional system for generating display data and the liquid crystal panel. That is, the apparatus of the present invention can be realized at low cost.

Further, according to the present invention, the above-described enlarged display can be performed using a liquid crystal panel in which two adjacent horizontal lines cannot be selected at the same time.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a liquid crystal driver according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a conventional liquid crystal driver.

FIG. 3 is a timing chart showing an operation of a conventional liquid crystal driver.

FIG. 4 is a block diagram of a TFT liquid crystal module using a conventional liquid crystal driver.

FIG. 5 is a diagram showing a conventional display example.

FIG. 6 is a timing chart illustrating an operation of the liquid crystal driver according to the first embodiment of the present invention.

FIG. 7 is a block diagram illustrating a configuration of a scan driver according to the first embodiment.

FIG. 8 is a timing chart illustrating the operation of the scan driver according to the first embodiment.

FIG. 9 is a diagram illustrating a display example according to the first embodiment.

FIG. 10 is a diagram illustrating an enlarged display example according to the first embodiment.

FIG. 11 is a timing chart illustrating an operation of a liquid crystal driver according to a second embodiment of the present invention.

FIG. 12 is a timing chart illustrating an operation of a scan driver according to the second embodiment.

FIG. 13 is a diagram illustrating a display example according to the second embodiment.

FIG. 14 is a diagram showing an enlarged display example according to the second embodiment.

FIG. 15 is a block diagram of a liquid crystal driver according to a third embodiment of the present invention.

FIG. 16 is a block diagram of a horizontal operation circuit 1107.

FIG. 17 is a block diagram of a vertical operation circuit 1120.

FIG. 18 is a timing chart illustrating the operation of the liquid crystal driver according to the third embodiment.

FIG. 19 is a timing chart illustrating an operation of a scan driver according to the third embodiment.

FIG. 20 is a diagram illustrating an enlarged display example according to the third embodiment.

FIG. 21 is a block diagram of a liquid crystal driver according to a fourth embodiment of the present invention.

FIG. 22 is a block diagram of a horizontal operation circuit 2108.

FIG. 23 is a block diagram of a vertical operation circuit 2119.

FIG. 24 is a timing chart illustrating the operation of the liquid crystal driver according to the fourth embodiment.

FIG. 25 is a timing chart illustrating the operation of the scan driver according to the fourth embodiment.

FIG. 26 is a diagram illustrating an enlarged display example according to the fourth embodiment.

FIG. 27 is a block diagram illustrating a shift register circuit according to the first and second embodiments.

FIG. 28 is a block diagram showing a shift register circuit 705 in the first and second embodiments.

FIG. 29 is a block diagram illustrating a control circuit 1102 according to the third embodiment.

FIG. 30 is a block diagram illustrating a control circuit 2102 according to the fourth embodiment.

FIG. 31 is a block diagram of a liquid crystal display according to a fifth embodiment of the present invention.

FIG. 32 is a block diagram of a liquid crystal driver.

FIG. 33 is a block diagram of a shift register circuit in the liquid crystal driver.

FIG. 34 is a block diagram of a scanning driver.

FIG. 35 is a timing chart showing the operation of the liquid crystal driver.

FIG. 36 is a timing chart showing the operation of the scanning driver and the liquid crystal driver.

FIG. 37 is a block diagram of a shift register circuit of a liquid crystal driver according to a sixth embodiment of the present invention.

FIG. 38 is a timing chart showing the operation of the liquid crystal driver.

FIG. 39 is a timing chart showing the operation of the scanning driver and the liquid crystal driver.

[Description of Signs] [FIG. 1] 101: data bus, 102: clock CL
2, 103... Display data capture start signal EI, 104
... horizontal synchronizing signals CL1, 105 ... reference gray scale voltage, 106
... Control circuit, 107 control signal, 108 shift register circuit, 109 latch signal group, 110 data latch circuit, 111 data bus, 112 line data latch circuit, 113 data bus, 114 gray scale voltage generation Circuit 115, signal line group (drain line group) [FIG. 2] 201 shift register circuit, 202 latch signal group, 203 data latch circuit, 204 data bus, 205 line data latch circuit, 206 data bus , 207: gradation voltage generation circuit, 208: signal line group (drain line group) [FIG. 4] 401: data bus, 402: control circuit, 40
3 ... Liquid crystal driver, 404, 404 '... Scan driver,
405: power supply circuit, 406, 406 ': liquid crystal panel, 4
08: data bus, 409: signal line, 410: signal line group (drain line group), 411: signal line group (gate line group),
412: power line, 413: power line, 414: power line, 4
15: power supply line, 416: thin film transistor (Thin
Abbreviated as Film Transistor TFT. ),
417: liquid crystal, 418: additional capacitance [FIG. 7] 701: line scan start signal, 702: line shift clock, 703: control signal, 704: power supply line, 705: shift register circuit, 706: shift clock group, 707: level shifter Circuit, 708: shift clock group, 709: voltage selection circuit, 710: signal line group (gate line group) [FIG. 15] 1101: output control signal, 1102: control circuit, 1103: control signal, 1104: operation control signal, 1
105: output selection signal, 1106: operation control signal, 11
07 ... horizontal operation circuit, 1108 ... odd pixel data bus, 1109 ... even pixel data bus, 1110 ... shift register, 1111 ... latch signal group, 1112 ... data latch circuit 1, 1113 ... data bus, 1114 ... line data latch circuit 1, 1115 ... data bus, 111
6, odd-numbered pixel data bus, 1117, even-numbered pixel data bus, 1118, line data latch circuit 2, 1119
Data bus, 1120... Vertical operation circuit, 1121.
Odd pixel data bus, 1122... Even pixel data bus,
1123 data latch circuits 2, 1124 data bus, 1125 line data latch circuits 3, 1126
Data bus, 1127 ... line data selector, 112
8 data bus, 1129 gradation voltage generation circuit, 113
0: signal line group (drain line group) [FIG. 16] 1601: latch circuit, 1602: data bus, 1603: latch circuit, 1604: data bus, 1
605: bit shift circuit, 1606: data bus, 1
607: bit shift circuit, 1608: data bus, 1
609 adder, 1610 data bus, 1611 latch circuit, 1612 data bus, 1613 data selector, 1614 bit shift circuit, 1615 data bus, 1616 bit shift circuit, 1617 data bus, 1618 addition , 1619 ... data bus, 1
620: latch circuit, 1621: data bus, 1622
... data selector [Fig. 17] 1701 ... bit shift circuit, 1702 ... data bus, 1703 ... bit shift circuit, 1704 ... data bus, 1705 ... adder, 1706 ... bit shift circuit, 1707 ... data bus, 1708 ... bit shift circuit , 1709: data bus, 1710: adder [FIG. 21] 101: data bus, 102: clock CL
2, 103... Display data capture start signal EI, 104
... Horizontal synchronization signal CL1, 105... Reference grayscale voltage, 210
Reference Signs List 1 output control signal, 2102 control circuit, 2103 control signal, 2104 operation control signal, 2105 data selection signal, 2106 output selection signal, 2107 operation control signal, 2108 horizontal operation circuit, 2109 odd number Pixel data bus, 2110 ... Even pixel data bus, 211
1: shift register, 2112: latch signal group, 211
13 data latch circuits 1 and 2114 data bus 2
115: Line data latch circuit 1, 2116: Data bus, 2117: Odd pixel data bus, 2118: Even pixel data bus, 2119: Vertical operation circuit, 212
0: odd pixel data bus, 2121: even pixel data bus, 2122: line data latch circuit 2, 2123 ...
Data bus, 2124... Line data selector, 212
5 Data bus, 2126 Data latch circuits 2, 21
27 data bus, 2128 line data latch circuit 3, 2129 data bus, 2130 line data selector, 2131 data bus, 2132 gradation voltage generation circuit, 2133 signal line group (drain line group) [FIG. 2201 latch circuit, 2202 data bus, 2203 latch circuit, 2204 data bus, 2
205: bit shift circuit, 2206: data bus, 2
207: bit shift circuit, 2208: data bus, 2
209 adder, 2210 data bus, 2211 latch circuit, 2212 data bus, 2213 data selector, 2214 bit shift circuit, 2215 data bus, 2216 bit shift circuit, 2217 data bus, 2218 addition , 2219 ... data bus, 2
220 data selector [FIG. 23] 2301 bit shift circuit, 2302 data bus, 2303 bit shift circuit, 2304 data bus, 2305 adder, 2306 bit shift circuit, 2307 data bus, 2308 bit shift Circuit, 2309 Data bus, 2310 Adder, 23
11 Data bus, 2312 Data selector [FIG. 27] 3101 flip-flop, 3102 selector, 3103 output [FIG. 28] 3201 flip-flop, 3202 selector, 3203 output [FIG. 29] 3301 register 3302 ... data bus, 3303 ... counter, 3304 ... output signal, 330
5 decoder circuit, 3306 decoder circuit, 3307
... Counter, 3308 ... Output signal, 3309 ... Decoder circuit, 3310 ... Counter, 3311 ... Output signal, 33
12: Decoder circuit [FIG. 30] 3401: Register, 3402: Control data bus, 3403: Counter, 3404: Output signal, 3
405 ... decoder circuit, 3406 ... decoder circuit, 34
07 counter, 3408 output signal, 3409 decoder circuit, 3410 counter, 3411 output signal,
3312 Decoder circuit, 3413 Decoder circuit [FIG. 31] 4901 Data bus, 4902 Control circuit, 4903 Liquid crystal driver, 4904 Scan driver, 4905 Power supply circuit, 4906 Liquid crystal panel, 49
07: signal line, 4908: signal line group (drain line group),
4909: signal line group (gate line group), 4910: power supply line, 4911: thin film transistor, 4912: liquid crystal, 4
913: additional capacity [FIG. 32] 4101: display data, 4102: clock, 4103: display data capture start signal, 4104
... data horizontal synchronizing signal, 4105 ... reference gradation voltage, 41
06: scanning horizontal synchronizing signal, 4107: control circuit, 410
8 control signal, 4109 shift register circuit, 411
0: latch signal group, 4111: data latch circuit, 41
12 data bus, 4113 line data latch circuit, 4114 data bus, 4115 line data latch circuit, 4116 data bus, 4117 gradation voltage generation circuit, 4118 signal line group (drain line group) [FIG. 4701: flip-flop circuit, 4702
... Selector circuit [FIG. 34] 4801 ... Line scan start signal, 480
2: Line shift clock, 4803: Power line, 480
4 shift register circuit, 4805 shift clock group, 4806 level shifter circuit, 4807 shift clock group, 4808 voltage selection circuit, 4809 signal line group (gate line group) [FIG. 37] 4701 flip-flop circuit, 4702
... Selector circuit

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Junhisa Oishi 1099 Ozenji Temple, Aso-ku, Kawasaki City, Kanagawa Prefecture Inside System Development Laboratory, Hitachi, Ltd. No. 1 Hitachi, Ltd. Semiconductor Division (72) Inventor Nobutaka Kato 1 Ikegami, Haruoka-cho, Owariasahi-shi, Aichi Prefecture Inside Hitachi Office Co., Ltd. Office Systems Division (72) Inventor 1099 Ozenji-ku, Hitachi, Ltd.System Development Laboratory, Hitachi, Ltd. (72) Inventor Shigehiko Kasai 1099 Ozenji, Aso-ku, Kawasaki-shi, Kanagawa Prefecture, Ltd.System Development Laboratory, Hitachi, Ltd. No. 3300 Inside the Electronic Device Division, Hitachi, Ltd.

Claims (15)

[Claims] 1. A liquid crystal panel in which pixel units having liquid crystal are arranged in M rows and N columns, display data is input, and a liquid crystal application voltage corresponding to the input display data is generated to generate a display voltage. A liquid crystal driving circuit to be applied to the pixel unit in the corresponding column of data; and one of the above rows is sequentially selected, and a selection voltage is applied to the pixel unit in the currently selected row, while the selection voltage is selected. A scan drive circuit that applies a non-selection voltage to the pixel units in the rows that do not have a row, wherein the liquid crystal drive circuit is provided for each of the plurality of drain signal lines that output the liquid crystal application voltage and the drain signal lines. Storage means for storing and storing the display data at timing separately determined for each of the storage element systems, and simultaneously outputting the stored display data to each other. A voltage generation circuit that converts display data output from the storage unit to the liquid crystal application voltage, wherein some of the storage element systems simultaneously fetch the display data from each other. Liquid crystal display. 2. The liquid crystal display device according to claim 1, wherein said storage element system for simultaneously taking in said display data has said corresponding drain lines adjacent to each other. 3. The liquid crystal display device according to claim 1, further comprising changing means for changing the number of storage element systems to be taken simultaneously with the display data. 4. A liquid crystal panel in which pixel units having liquid crystal are arranged in M rows and N columns, display data is input, and a liquid crystal application voltage corresponding to the input display data is generated to display the voltage. A liquid crystal driving circuit to be applied to the pixel unit in the corresponding column of data; and one of the above rows is sequentially selected, and a selection voltage is applied to the pixel unit in the currently selected row, while the selection voltage is selected. A scan drive circuit that applies a non-selection voltage to the pixel units in the non-selected rows.The scan drive circuit simultaneously selects a plurality of rows, and applies the selection voltage to the pixel units in the simultaneously selected rows. The liquid crystal display device is applied during the same period. 5. The liquid crystal display device according to claim 3, wherein said simultaneously selected rows are adjacent to each other. 6. The liquid crystal display device according to claim 4, further comprising selected row number changing means for changing the number of rows simultaneously selected by said scanning drive circuit. 7. A liquid crystal panel in which pixel sections provided with liquid crystal are arranged in M rows and N columns, display data is input, and a liquid crystal application voltage corresponding to the input display data is generated to display the voltage. A liquid crystal driving circuit to be applied to the pixel unit in the corresponding column of data; and one of the above rows is sequentially selected, and a selection voltage is applied to the pixel unit in the currently selected row, while the selection voltage is selected. A scanning drive circuit that applies a non-selection voltage to the pixel portion of the non-row, and the liquid crystal drive circuit performs arithmetic processing on display data adjacent in the horizontal direction to generate display data of the interpolated pixel, A liquid crystal display device comprising: a first data generation circuit that outputs after increasing the number of display data items in the horizontal direction. 8. A liquid crystal panel in which pixel units provided with liquid crystal are arranged in M rows and N columns, display data is input, and a liquid crystal application voltage corresponding to the input display data is generated to display the voltage. A liquid crystal driving circuit to be applied to the pixel unit in a corresponding column of data; and
/ M times (where n <m, where n and m are integers), and the selection voltage is applied to the pixels in the row selected at that time, while the selection is applied to the pixels in the row not selected at that time. A scan driving circuit for applying a non-selection voltage, wherein the liquid crystal driving circuit generates display data of the interpolated pixel by performing arithmetic processing on n pieces of display data adjacent in the vertical direction, A second data generation circuit that outputs a total of m pieces of display data. 9. The liquid crystal driving circuit further increases the number of display data in the horizontal direction by adding arithmetic processing to display data adjacent in the horizontal direction to generate display data of an interpolated pixel. 9. The liquid crystal display device according to claim 8, further comprising a first data generation circuit that performs the following. 10. The arithmetic processing according to claim 7, wherein a value of display data of an adjacent pixel is multiplied by a coefficient predetermined for each pixel, and the result is added. 10. The liquid crystal display device according to 8 or 9. 11. A liquid crystal panel having liquid crystal and having a pixel portion arranged in M rows and N columns, a plurality of row signal lines and column signal lines connected to the pixel portion, and a display signal synchronizing signal. A liquid crystal control circuit that captures and generates a liquid crystal drive synchronization signal based on the synchronization signal; and sequentially selects one row of the liquid crystal panel according to the liquid crystal drive synchronization signal, and transmits the display data for one screen. A scanning drive circuit that selects all rows at the same cycle as the selected cycle, applies a selection voltage to the pixel section of the selected row via the row signal line, and applies a non-selection voltage to other pixel sections. Storage means for fetching the display data in accordance with the liquid crystal drive synchronization signal and storing the display data, and selecting the display represented by the display data based on one row of display data stored in the storage means. Voltage applied A liquid crystal driving circuit that generates a liquid crystal application voltage to be performed in the pixel unit, and applies the liquid crystal application voltage to the pixel unit via the column signal line. While the plurality of rows adjacent to each other are selected by the scan driving circuit,
A liquid crystal display device, wherein a liquid crystal application voltage based on display data for a row is applied to the pixel portion. 12. A liquid crystal drive circuit comprising: a first storage circuit for sequentially storing the fetched display data in pixel units; and a first row of the display data stored in the first storage circuit. A second storage circuit that simultaneously fetches the display data for one row stored in the first storage circuit and stores it for one row at the same cycle as the cycle performed, and switches the row selected by the scan drive circuit. And a third storage circuit for simultaneously taking in the display data stored in the second storage circuit and storing the data for one row, and the liquid crystal drive circuit stores the display data in the third storage circuit. The cycle in which the liquid crystal application voltage is generated based on the display data, and the third storage circuit takes in the display data is longer than the cycle in which the first storage circuit stores one row of the display data. A contract characterized by being short The liquid crystal display device of claim 11, wherein. 13. A ratio a: b (a and b) of a cycle in which one row of the display data is stored in the first storage circuit and a cycle in which the third storage circuit fetches display data.
13. The liquid crystal display device according to claim 12, further comprising means for changing (a is an integer satisfying a ≧ b). 14. The liquid crystal driving circuit according to claim 1, wherein the pixel portions of a plurality of predetermined columns adjacent to each other are provided in a predetermined column of the display data of the one row stored in the storage means. 12. The liquid crystal display device according to claim 11, wherein a liquid crystal application voltage based on display data for one corresponding pixel is applied. 15. The liquid crystal display device according to claim 14, further comprising means for changing the predetermined plurality of adjacent columns and a predetermined column of the display data for one row.