JPH1070097A - Method of planarization of semiconductor substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable monitoring the removed layer thickness without removing particles from a polishing equipment, at the time of chemical/mechanical polishing(CMP) of a semiconductor substrate. SOLUTION: A polishing pad 19 is rotated while polishing slurry at about 10-30 deg.C is supplied on the pad from a resolver 21. A semiconductor substrate 12 held by a carrier 11 is pressed against the polishing pad and rotated, thereby flattening the semiconductor substrate. The temperature at a specific position of the polishing pad or the semiconductor substrate is measured by using an infrared sensor 22, and is stored in a computer memory 25, in accordance with the passage of polish time. The temperature versus the polish time is integrated with time. The thickness of a removed layer is obtained as a function of polishing time, by the calculation using the integrated value and integration coefficients relating to the CMP removed chemical substances and the pattern density on the under side.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus and a method for monitoring the thickness removed from a layer in chemical / mechanical polishing (CMP). More specifically, the present invention provides:
Without the need to remove particles from the polisher,
In-situ monitoring of thickness removed from a layer during an MP.

[0002]

2. Description of the Related Art Chemical / mechanical polishing (CMP) has been developed to provide a smooth topography on a surface deposited on a semiconductor substrate. The formation of metal conductors on the substrate containing the circuitry of the device results in a coarse topography. Metal conductors have the function of interconnecting discrete devices to form integrated circuits. The metal wires are further insulated from the next interconnect level by a thin film of insulating material, and between the continuous conductive interconnect layers through holes formed through the insulating layer. Electrical connections are provided. In such a wiring process, it is desirable for the insulating layer to have a smooth surface topography because, for rough surfaces, it is difficult to image and pattern the layer using lithographic techniques. It is. CMP can also be used to remove different layers of material from the surface of a semiconductor substrate. For example, after forming via holes in a layer of dielectric material and blanket depositing a metallization (metal) layer, CMP is used to create flat (planar) metal studs.

[0003] Briefly, the CMP process spins a thin, flat wafer of semiconductor material under controlled chemical, pressure, and temperature conditions and against a wet polished surface. Including that. A chemical slurry containing an abrasive such as alumina or silica is used as a polishing material. In addition, this chemical slurry
Contains chemicals selected to etch various surfaces of the wafer during processing. By combining mechanical and chemical removal of material during polishing, the polished surface can be very flattened. In this process, it is important to remove a sufficient amount of material to provide a smooth surface without excessive removal of the underlying material. Therefore, it is important to monitor the thickness of material removed during the polishing process, ie, monitor the thickness of material remaining on the substrate during the polishing process.

Conventionally, material removal involves physically interrupting the CMP process, removing the wafer from the polishing apparatus, and physically refining the wafer surface using techniques to verify film thickness and / or surface topography. By inspecting
Has been monitored. Performing this operation requires additional wafer cleaning steps and labor intensive inspection and measurement, which reduces throughput in the polishing apparatus. If the wafer does not meet the specifications, it must be returned to the polishing apparatus again for further polishing. Excessive material removal will result in the wafer not meeting specifications and substandard. This end point and thickness monitoring method is time consuming, unreliable and costly. Accordingly, improvements in endpoint detection and thickness monitoring during CMP have been made, as shown in the following patents.

"Method for Determ" to William J. Cote
ining Planarization Endpoint during Chemical-Mecha
US Patent No. 5,234,869 entitled "Nical Polishing" (patent registered August 10, 1993)
The monitor structure enclosed by t) is described.
Because of this moat, removal by abrasion is more significant in the monitor structure than in areas where the moat is not surrounding.
Go faster. The top of the monitor structure is exposed, resulting in a planarized insulating layer over the metal pattern that is not surrounded by the moat. Visually inspect,
Determine the exposure of the top of the monitor structure. Monitoring is also performed electrically by detecting the electrical connection between the top of the metal monitor structure and the polishing pad. Ch
"Chemical-Mechanical Planarization to ris C. Yu et al.
(CMP) of a Semiconductor Wafer Using Acoustical W
In the invention described in US Pat. No. 5,240,552 entitled “Aves for In-situ End Point Detection” (patent registered on Aug. 31, 1993), a sound wave is emitted to the wafer during CMP and the reflected waveform is analyzed. By doing so, the planarization process is controlled.

[0006] "Endpoint Detect" to William J. Cote et al.
ion Apparatus and Method for Chemical-Mechanical P
olishing ", U.S. Pat. No. 5,309,438 (19)
(Patent registered on March 3, 1994) describes an endpoint detection method by monitoring electric power required to maintain a rotation speed set in a motor that rotates a substrate. The endpoint is detectable because the power required to maintain a preset rotational speed in the motor that rotates the substrate is significantly reduced once the hard-to-polish layer is removed. Naftali E. Lusti
g "In-situ Endpoint Detection Method and A"
pparatus for Chemical-Mechanical Polishing Using L
US Patent No. 53 entitled "ow Amplitude Input Voltage"
No. 37015 (registered August 9, 1994) discloses a method in which an electrode incorporated in a polishing pad, a high-frequency low-voltage signal, and a detecting means measure the thickness of a dielectric layer being polished. In, is used.

"Optical End Po" by Daniel A. Koos et al.
int Detection Methods in Semiconductor Planarizing
US Patent No. 541394 entitled "Polishing Process"
No. 1 (May 9, 1995) describes a method for detecting an end point of polishing by irradiating a substrate to be polished with laser light and measuring reflected light. The intensity of the reflected light is a measure of the flatness of the polished surface. "Method f" by Gurtej S. Sandhu et al.
or Controlling a Semiconductor (CMP) Process by Mea
suring a Surface Temperature and Developing a Ther
US Patent No. 5196 entitled "mal Image of the Wafer"
No. 353 describes the use of infrared radiation detection to measure the surface temperature of a semiconductor wafer during a polishing process. A sudden change in temperature at the wafer surface during the polishing process is used to detect the endpoint. The present invention relates to a novel method and apparatus for in-situ monitoring of the removed thickness of a layer during CMP without removing particles from the polishing apparatus.

[0008]

SUMMARY OF THE INVENTION It is an object of the present invention to provide an improved new apparatus and method for chemical and mechanical planarization (CMP) of the surface of a substrate, wherein the apparatus and method include: The thickness of the removed layer is determined by monitoring the temperature of the polishing process over time and integrating a curve representing the change in polishing temperature with the polishing time on the horizontal axis. It is derived by calculating
Another object of the present invention is to provide chemical and mechanical planarization (CM
P) to provide a new and improved method, wherein the thickness of the removed layer is in situ,
By measuring the temperature of the polishing pad, monitoring the temperature of the polishing pad as the polishing time elapses, and integrating a curve representing the temperature change of the polishing pad with the polishing time taken on the horizontal axis,
Derived from calculating the thickness of the removed layer.

It is yet another object of the present invention to provide a new and improved method for chemical and mechanical planarization (CMP), in which the uniformity of the removal process is increased. By detecting the temperature of the substrate at each location, individually integrating the curves representing the temperature changes at each location with the abscissa representing the polishing time, and deriving the thickness of the layer removed at each location. , Monitored on the fly. In an exemplary embodiment, an apparatus for performing the method of the present invention comprises a wafer carrier and a rotating polishing platen for chemically and mechanically planarizing (CMP) a semiconductor wafer, a rotating polishing pad, Means for controlling the temperature of a polishing slurry and mechanically; means for applying a chemical and mechanical polishing slurry on a polishing pad; an infrared detection device for monitoring the temperature of a rotating polishing pad; and polishing with the passage of polishing time. Means for storing the temperature of the pad in computer memory; means for storing the integral coefficients for the CMP removal chemistry and the underlying pattern density in computer memory;
Means for calculating the thickness of the layer removed over the polishing time by integrating the temperature change data over the stored polishing time and applying the stored integration factor. I have.

In a second embodiment, an apparatus for performing the method of the present invention comprises a wafer carrier and a rotary polishing platen for chemically and mechanically planarizing (CMP) a semiconductor wafer; a rotary polishing pad; Means for controlling the temperature of the chemical and mechanical polishing slurry; means for providing the chemical and mechanical polishing slurry on the polishing pad; and means for measuring the temperature of the semiconductor substrate at a plurality of locations on the semiconductor substrate. Means for storing, in a computer memory, a temperature with the passage of polishing time at each of a plurality of positions on a semiconductor substrate; means for storing, in a computer memory, integral coefficients for a CMP removal chemical and a lower pattern density And integrates the temperature change data with the stored polishing time over time at each location with the polishing time, and applies the stored integration coefficient By Rukoto includes for each plurality of locations on the semiconductor substrate, means for calculating the thickness of the layer removed with the lapse of polishing time, the.

[0011]

DETAILED DESCRIPTION OF THE INVENTION A new and improved CMP apparatus and method for planarizing (to planar) the surface of a semiconductor substrate is disclosed.
This will be described in detail below. The apparatus and method uses chemical and mechanical polishing (CMP), but the in-situ monitoring of the thickness removed from the layer during the CMP without the need for removal of particles from the polishing apparatus. become. This method uses CVD (Chemical Vapor Deposition), L on a semiconductor device and conductor interconnect wiring (wiring) pattern.
Surfaces of insulators such as silicon oxide and silicon nitride deposited by PCVD (Low Pressure Chemical Vapor Deposition) or PE-CVD (Plasma Enhanced Chemical Vapor Deposition) or by spin-on and reflow deposition means An insulating layer made of glass or the like can be used for planarization.

FIGS. 1A and 1B are schematic diagrams of a chemical and mechanical planarization (CMP) apparatus used in accordance with the method of the present invention. FIG. 1A is a schematic cross-sectional view of the CMP apparatus 10. The CMP apparatus 10 includes a semiconductor wafer 12
Is included. The wafer carrier 11 is installed so as to be continuously rotated around an axis A1 in a direction indicated by an arrow 13 by a drive motor 14. Wafer carrier 11 is mounted such that a force acts on semiconductor wafer 12 at arrow 15. The CMP apparatus 10 also includes a polishing platen 16,
This is because the drive motor 18 moves the arrow 1 around the axis A2.
It is installed so as to rotate continuously in the direction indicated by 7. The polishing pad 19 is formed from a material such as blown polyurethane and is mounted on a polishing platen. A polishing slurry contains a polishing fluid in which polishing particles, such as silica or alumina, are suspended in either a basic or acidic solution, from a temperature controlled reservoir 21 through a conduit. : Conduit) 2
0 and is supplied onto the polishing pad 19. An infrared radiation detection device 22 is installed to detect infrared radiation emitted from the region 23 designated by x. The region 23 is formed by the continuous rotation of the polishing pad 19 as shown in FIG.
Trace 4 The position of the region 23 corresponds to the position of the polishing pad 19.
During the rotation of the polishing pad 19, the polishing pad 19 is located inside the portion for polishing the semiconductor wafer 12. Computer memory 25
Stores data regarding the temperature of the polishing pad that varies in relation to the polishing time during the CMP process. Also,
Computer memory 25 stores integral coefficients 26 specific to each CMP chemistry and underlying pattern density.

In a second embodiment of the present invention, the means for measuring the temperature of the semiconductor substrate at a plurality of locations (positions) on the semiconductor substrate is provided as shown schematically in FIGS. 2A and 2B. , Provided. In FIG. 2A, the wafer carrier 30
Has a plurality of temperature sensors 31A, 31A inside itself.
B, 31C, 31D, and 31E are embedded. Although five sensors are shown in this example, the number and location of the sensors can be adjusted according to the needs of the process. A temperature sensor is a thermocouple device or other device that measures temperature, for example, a fulluro optic (fl
(uro-optic) temperature monitor and infrared temperature measurement device. The temperature sensors 31A to 31E are arranged so as to monitor the temperature on the back side of the semiconductor substrate 32 at a plurality of locations. The sectional view of FIG. 2A and the upper view of FIG.
An exemplary array of three temperature sensors is shown schematically. The computer memory 33 stores data relating to the temperature of each location on the semiconductor substrate as the polishing time elapses during the CMP process. The computer memory 33 has an individual CMP on the semiconductor substrate 32.
And an integral factor 34 specific to the underlying chemistry and underlying pattern density. Next, a method for deriving the thickness of the removed layer from the measurement of the temperature change at the polishing interface (interface) will be described in detail. To a first order approximation, the resulting temperature change at the polishing interface is due to heat transfer at the interface, as shown below.

That is, if the heat conduction is much greater than the temperature change, then [the rate of change of the incoming thermal energy]
-[Change rate of outgoing heat energy] + [change rate of heat energy generation] = 0. The temperature change [Delta] T, the heat capacity of h, when the Q and [mechanical heat flow rate (flux)] + [chemical heat flow rate, because it is Q = EtchiderutaT, a Q = Q _M + Q _C. When Q _M = δQ _C, is _{Q = Q M + Q C =} (1 + δ) Q C. Here, if R is the reaction rate between the slurry and the layer and H _C is the latent heat of the chemical reaction, then Q _C = RxH _C. Next, k is a reaction rate constant, and dL is a time dt.
R = chemical reaction rate = k · dL / dt. Therefore, Q = (1 + δ) Q _C = (1 + δ) kdL / dt≡hΔ
T. Therefore, if the proportional constant is written as A, then A · dL
Since / dt≡hΔT, dL / dt≡hΔT / A. By integrating both sides of this equation from 0 to t, the following equation is obtained.

(Equation 1) Thus, the thickness removed is proportional to the integral over time of the temperature change.

The method according to the invention for monitoring the thickness of the material removed in situ will now be described by way of an example in which a complex dielectric layer deposited on a semiconductor substrate is planarized using CMP. Let me explain. 3 and 4 show PE-
FIG. 3 illustrates chemical and mechanical planarization (CMP) of semiconductor wafers, including metallized MOSFET devices having a composite dielectric overlayer of TEOS / SOG / PE-TEOS deposited thereon. ing. P
E-TEOS is a common insulator in the semiconductor industry and represents the plasma enhanced growth of silicon oxide from tetraethylorthosilicate. SOG stands for spin-on-glass, which is also common in the semiconductor industry. A typical NFET (N-type field effect transistor) device comprises, as shown in FIG. 3, a semiconductor wafer 12 of P-type single crystal silicon having a <100> orientation, a thick field oxide region 4.
0 (FOX), polysilicon gate 41, gate oxide 42, source and drain regions 43, sidewall spacers 4
4. L composed of silicon oxide 45 and silicon nitride 46
PCVD (low pressure chemical vapor deposition), interlevel connection plug 47, conductive interconnect pattern 48, first PE-T
EOS layer 49, SOG layer 50, and second PE-T
An EOS layer 51 is included. First PE-TEOS layer 4
9 using a plasma-enhanced vapor deposition method from tetraethylorthosilicate at a temperature between about 200-400 ° C.
Deposited at a thickness between about 2000-5000 Angstroms (Å). The SOG layer 50 consists of providing two to four layers of spin-on-glass, followed by reflow at a temperature between about 250-450 ° C., resulting in a thickness of about 2000-10000 Å. Occurs. The second PE-TEOS layer 51 has a thickness of about 200 to 4
At a temperature between 00 ° C., using plasma enhanced vapor deposition from tetraethyl orthosilicate, about 2000 to 500
Deposited at a thickness between 0 Angstroms (Å). Planarization of the surface topography 52 is performed using chemical and mechanical polishing (CMP) in the apparatus shown in FIG. 3 but schematically shown in FIGS. 1A and 1B,
As a result, a substantially flat dielectric layer surface 53 is obtained as shown in FIG.

Next, a method for measuring the thickness of the removed dielectric layer of the surface topography 52 shown in FIG. 3 in-situ during CMP will be described in detail. Referring to FIGS. 1A and 1B, a polishing slurry comprised of silica and NH 4 OH in H ₂ O contained in the storage device 21 is about 1 μm.
The temperature is controlled in a range of 0 to 30 ° C., and is supplied through a tube 20 and supplied to the polishing pad 19. Infrared radiation detection device 22 measures the temperature of region 23 on polishing pad 19. The semiconductor wafer 12 is placed in the polishing apparatus 10.
The second PE-TEOS layer 51 is placed face down with the surface in contact with the polishing pad 19. The speed of the polishing platen motor 18 is set to about 10 to 70 rpm, and the speed of the wafer carrier driving motor 14 is set to about 10 to 70 rpm.
It is set to rotate at a speed between. The wafer carrier 11 is applied by applying a force 15 to about 1 to 10
It is set to apply psi pressure between the wafer and the polishing pad. During the CMP process, computer memory 25 stores data relating to the temperature of the polishing pad over time. For example, the voltage output from the temperature measurement device is a standard IEEE-48
8 interface and an A / D (analog-to-digital) converter coupled to computer memory. The digital data is converted to temperature using a commercially available database of temperature and voltage correlations. Further, the computer memory 25 stores an integral coefficient 26 specific to the chemical property of the CMP on the semiconductor substrate 12 and the lower pattern density.

FIG. 5 shows a state in which the surface 52 of the semiconductor substrate shown in FIG. 3 is flattened by chemical and mechanical polishing.
The behavior of the infrared detected polishing pad temperature over time is shown. As shown in FIGS. 3 and 5, when the second PE-TEOS layer 51 begins to be polished first, the temperature of the polishing pad increases as shown at 60. This is due to the friction between the pad fibers and the abrasive particles in the polishing slurry and the PE-TEOS layer. During polishing of the PE-TEOS layer, the temperature of the polishing pad remains at a substantially constant level, as indicated at 61. When the polishing pad contacts the SOG layer, which is a more difficult material to polish, the friction between the fibers of the pad and the abrasive particles in the polishing slurry and the surface to be polished increases, as shown at 63. Temperature rises. Finally, the temperature of the polishing pad becomes constant at a higher level, as shown at 64. This is due to the higher friction between the pad fibers and the abrasive particles in the polishing slurry and the SOG layer 50.

In a first step approximation, the thickness of the layer removed over time is obtained by computer integration of the change in polishing pad temperature with respect to polishing time, as shown in FIG. . The shaded area 70 represents the integration of the temperature change of the polishing pad with respect to the polishing time.
In the approximation of the first step, the area 70, that is, the integrated area below the curve representing the temperature change of the polishing pad with the polishing time as the horizontal axis was removed at the polishing time Pr indicated by 71. It is a measured value of the thickness.

FIG. 7 illustrates how the stored integration coefficients for a particular CMP removal chemistry and underlying pattern density can be applied to derive a second step approximation of the removed layer thickness. I have. In region A, indicated by 81, the integrated area A is multiplied by a stored coefficient α ₁ associated with the polish removal chemistry for PE-TEOS. In a region B indicated by 82, the integrated area B is multiplied by the stored coefficients ε and α ₂ .
The stored coefficient ε is related to the pattern density of the underlying structure, and the stored coefficient α ₂ is related to the polishing removal chemistry for SOG. In region C, indicated by 83, the integrated area C is multiplied by a stored coefficient α ₂ associated with the polishing removal chemistry for SOG. The thickness of the removed layer is obtained from the sum of the adapted integral coefficients stored in the integrated area, as shown by equation 80.

The method of the present invention is further described by discussing experimental results in polishing four semiconductor substrates including a composite dielectric layer deposited over an interconnect pattern. Table 1 below lists the parameters of the experiment.

[Table 1]

The stored coefficient α ₁ is related to the polishing chemistry for the slurry and the bottom dielectric layer and the initial topography or smoothness of the substrate. The stored coefficient ε is related to the pattern density and surface topography due to the underlying structure. Stored coefficient α ₂
Is related to the polishing chemistry for the slurry and the second layer of SOG and the initial topography or smoothness of the second layer of SOG. Substrate W19 corresponds to the nominal condition and all coefficients are one. Substrate W23 has less initial topography than the other substrates,
This is because four layers of SOG were provided as second layers. For this reason, it is necessary to reduce the coefficient ε for the substrate 23, and ε = 0.5. The substrates W21 and W20 have a coefficient ε = 1, which is
This is because the substrate W19 and the initial topography are the same. The substrate W21 uses the same polishing slurry SC112 as the substrate W19, and the initial topography of the substrate W21 is the same as that of the substrate W19.
The coefficients are α ₁ = 1 and α ₂ = 1. But slurry SS
-12 is a slurry SC112 for silicon oxide.
CMP polishing rate is higher than that of CMP. Therefore, the α coefficient for the substrates W20 and W23 must reflect this fact as well as the effect of the initial topography on the CMP polishing rate. Substrate W20 has the same initial topography as substrate W19, corresponding to a higher CMP polishing rate for silicon oxide in slurry SS-12 and α ₁
= 1.43 and α coefficient = α ₂ = 1.50. As a result of adjusting the α coefficient for the smaller initial topography of the substrate W23 compared to the substrate W19,
The α coefficient for 23 is α ₁ = 0.71, α ₂ = 0.71
It is.

FIG. 8 shows the removed dielectric layer thickness for each of the four substrates in this experiment.
This was obtained by integrating the temperature change of the polishing pad with respect to the polishing time and applying the integration factor for the specific CMP removal chemistry and the underlying pattern density for each of the four substrates. Although the present invention has been shown and described with reference to specific embodiments, various changes may be made in form and detail by those skilled in the art without departing from the spirit and scope of the invention. It should be understood that it is possible.

[Brief description of the drawings]

FIG. 1A is a schematic diagram of a cross section of a polishing apparatus used in accordance with the method of the present invention. B is a view of the device illustrated in A viewed from above.

FIG. 2A is a schematic diagram of a wafer carrier having a plurality of temperature measurement devices embedded therein. B is a view from above of the wafer carrier illustrated in A.

FIG. 3 is a schematic cross-sectional view showing the planarization of the surface of a composite dielectric layer on a semiconductor substrate.

FIG. 4 is a schematic cross-sectional view showing a planarization of a surface of a composite dielectric layer on a semiconductor substrate, similarly to FIG. 3;

FIG. 5 is a diagram showing the temperature behavior of a polishing pad detected by infrared rays over time when the surface of a composite dielectric layer of a semiconductor substrate is planarized using chemical and mechanical polishing. It is.

FIG. 6 is a diagram showing a polishing pad temperature curve with the polishing time as the horizontal axis, and a change in the polishing pad temperature integrated with respect to the polishing time in order to determine the area under the curve.

FIG. 7 illustrates the application of stored integral coefficients for specific CMP removal chemistries and underlying pattern densities, and derivation of removed thickness.

FIG. 8 shows an example of the thickness removed and the specific CMP derived by integrating the change in polishing pad temperature with respect to polishing time.
FIG. 4 shows the application of integral coefficients for removal chemicals and lower pattern density.

Claims (29)

[Claims] 1. A method of chemical / mechanical planarization (CMP) of a semiconductor substrate, comprising: holding a semiconductor substrate on a rotating platen opposite a rotating polishing pad on which a polishing slurry is present, wherein the semiconductor substrate is Flattening; controlling the temperature of the polishing slurry within a temperature range of about 10 to 30 ° C .; placing the temperature-controlled polishing slurry on a rotary polishing pad; Measuring the temperature of the rotary polishing pad at a predetermined position of the rotary polishing pad being polished using infrared detection means; and storing the temperature of the polishing pad in a computer memory in relation to the elapse of the polishing time. Storing the integral coefficient of the CMP removal chemical and the lower pattern density in a computer memory; Calculating the thickness of the removed layer related to the polishing time by integrating the stored temperature change with respect to time over time and applying the stored integration factor. A method comprising: 2. The method according to claim 1, wherein the polishing slurry comprises silica and NH ₄ OH in H ₂ O. 3. The method of claim 1, wherein the temperature of the rotating polishing pad is measured at a temperature in the range of about 10-80 ° C. 4. A method for chemical / mechanical planarization (CMP) of a semiconductor substrate, comprising: holding the semiconductor substrate on a rotating platen opposite a rotating polishing pad on which a polishing slurry is present. Flattening; controlling the temperature of the polishing slurry within a temperature range of about 10 to 30 ° C .; placing the temperature-controlled polishing slurry on a rotary polishing pad; Measuring the temperature of the semiconductor substrate at a location; storing temperature data at a plurality of locations on the semiconductor substrate in a computer memory, each associated with a polishing time; and a CMP removal chemical and a lower pattern. Storing the integral coefficient with respect to the density in a computer memory; and storing the temperature change stored in relation to the polishing time. Calculating the thickness of the removed layer associated with the polishing time data at each of the plurality of locations on the semiconductor substrate by integrating the data of FIG. 3 with respect to time and applying the stored integration factor. A method characterized by being. 5. The method according to claim 4, wherein the polishing slurry comprises silica and NH ₄ OH in H ₂ O. 6. The method of claim 4, wherein the temperature of the semiconductor substrate is measured at at least one location on the semiconductor substrate. 7. The method according to claim 4, wherein the temperature of the semiconductor substrate is measured at a temperature in a range of about 10-80 ° C. 8. A method of manufacturing a planarized layer of a dielectric material on a semiconductor substrate including a structure, the method comprising: providing a structure on a semiconductor substrate; Applying a layer of a dielectric material; and planarizing the layer of a dielectric material,
Flattening the semiconductor substrate by holding the semiconductor substrate on a rotating platen opposite the rotating polishing pad on which the polishing slurry is present and applying pressure between the platen and the polishing pad; Controlling the temperature within a temperature range of -30 ° C .; placing a temperature-controlled polishing slurry on the rotary polishing pad; and controlling the temperature of the rotary polishing pad polishing the surface of the layer made of a dielectric material. Measuring at a location on the polishing pad using infrared detection means; storing the temperature of the polishing pad in a computer memory in relation to the elapse of the polishing time; Storing the integral coefficient in relation to the pattern density in computer memory; and storing the temperature change data stored in relation to the polishing time. How integrated, and by applying the stored integration coefficient, the thickness of the removed layer, characterized by comprising the steps of calculating in relation to the course of polishing time with respect. 9. The method according to claim 8, wherein the structure is an active device. 10. The method of claim 8, wherein the structure is an interconnect pattern of a conductive material. 11. The method of claim 8, wherein the structure includes both an active device and an interconnect pattern of a conductive material. 12. The method according to claim 9, wherein the active device is an N-type or P-type MOSFET device. 13. The method of claim 10, wherein the interconnect pattern of conductive material is between about 4000 and 10.
A method characterized by being aluminum having a thickness between 000 Angstroms (Å). 14. The method of claim 8, wherein the layer of dielectric material is about 200 to 40 using PECVD.
A method characterized in that it is silicon oxide deposited at a temperature of 0 ° C. and with a thickness of about 2000-5000 Å. 15. The method of claim 8, the polishing slurry was controlled to a temperature range of about 10 to 30 ° C., H ₂
A method comprising silica and NH ₄ OH in O. 16. The method of claim 8, wherein the rotating polishing pad rotates in a range from about 10 to 70 rpm. 17. The method of claim 8, wherein the rotating platen rotates in a range from about 10 to 70 rpm. 18. The method of claim 8, wherein the pressure applied between the platen and the polishing pad is between about 1-10.
psi range. 19. A method of manufacturing a planarized layer of a dielectric material on a semiconductor substrate including a structure, the method comprising: providing a structure on a semiconductor substrate; Depositing a layer of a dielectric material, and planarizing the layer of a dielectric material,
Holding the semiconductor substrate on a rotating platen opposite the rotating polishing pad on which the polishing slurry resides, and planarizing by applying pressure between the rotating platen and the rotating pad; Controlling the temperature to a temperature range of -30 ° C., placing the temperature-controlled polishing slurry on a rotating polishing pad, measuring the temperature of the semiconductor substrate at a plurality of positions on the semiconductor substrate, Storing temperature data at each of the plurality of locations on the semiconductor substrate in a computer memory in relation to the elapsing of the polishing time; and calculating an integral coefficient relating to the CMP removal chemical and the lower pattern density. Storing in a memory the thickness of the removed layer at each of a plurality of locations on the semiconductor substrate; By data of the temperature change which is stored associated to polish time and integrated over time for each location, and applying the stored integral coefficient,
Calculating in relation to the polishing time. 20. The method of claim 19, wherein the structure is an active device. 21. The method of claim 19, wherein the structure is an interconnect pattern of a conductive material. 22. The method of claim 19, wherein the structure includes both an active device and an interconnect pattern of a conductive material. 23. The method of claim 20, wherein the active device is an N-type or P-type MOSFET device. 24. The method according to claim 21, wherein the interconnect pattern of conductive material is between about 4000-10.
A method characterized by being aluminum having a thickness of 000 angstroms. 25. The method according to claim 19, wherein the layer of dielectric material is formed using PECVD by about 200-4.
A method characterized in that it is a silicon oxide deposited at a temperature of 00C and a thickness of about 2000-5000 Angstroms. 26. The method according to claim 19, wherein the polishing slurry is H ₂ controlled to a temperature in the range of about 10-30 ° C.
A process comprising silica in NH and NH ₄ OH. 27. The method of claim 19, wherein the rotating polishing pad rotates in a range from about 10 to 70 rpm. 28. The method of claim 19, wherein the rotating platen rotates in a range from about 10 to 70 rpm. 29. The method of claim 19, wherein the pressure applied between the rotating platen and the polishing pad is about 1
A method in the range of 10 to 10 psi.