JPH1069793A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a non-selected memory cell from being erroneously written due to that electric charges are accumulated in a digit line of a memory cell selected afterwards before electric charges accumulated in a word line of a memory cell previously selected are discharged when an address is switched at the writing mode. SOLUTION: A pulse generation circuit 2 generating a pulse ϕA for discharge is provided, based on an address latch signal CLKA taking address information ADD0-ADD3, an X decoder 1 driving word lines W1-W3 is controlled by the pulse ϕA. At this point, before address selecting signals X0, X1 reach the X decoder 1, the pulse ϕA is supplied to the X decoder 1, electric charges of word lines of selected memory cells M11-M33 are quickly discharged.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device for preventing erroneous writing to an unselected memory cell when writing to a semiconductor memory cell.

[0002]

2. Description of the Related Art Conventionally, such a semiconductor memory device has
The semiconductor memory cells arranged in a matrix are accessed using an X decoder that specifies a word line based on an address signal, a Y selector that specifies a digit line, or the like.

FIG. 6 is a circuit diagram of a semiconductor memory device showing an example of such a prior art. As shown in FIG. 6, this semiconductor memory device shows a nonvolatile memory cell array including memory cells M11 to M33, and uses address signals ADD0 to ADD3 as address peripheral signals as address peripheral signals.
The address latch circuit 3 which captures and holds the data by the LKA and outputs the lower address signals A0 and A1 and the upper address signals A2 and A3, and Y which designates the digit lines D1 to D3 by the lower address signals A0 and A1.
It has a selector 4 and an X decoder 1a for specifying word lines W1 to W3 by upper address signals A2 and A3. Note that the X decoder 1a usually has a built-in predecoder.

When the address latch signal CLKA is at the H level (substantially VDD), the address latch circuit 3 is open. When the address latch signal CLKA becomes L level (substantially GND), the latch circuit 3 is closed and the address signal is held. . In the X decoder 1a, one of the word lines W1 to W3 is selected based on the upper address signals A2 and A3. Further, the Y selector 4 selects one of the digit lines D1 to D3 by the lower address signals A0 and A1.

On the other hand, a nonvolatile memory composed of memory cells M11 to M33 has a power supply voltage VDD (5 V) for normal operation as a power supply voltage and a high power supply voltage V
Three of PP (10V) and GND are used. In the write mode, for example, when the memory cell M11 is selected, the high power supply voltage VPP is applied to the word line W1 connected to the control gate of the memory cell M11, and the digit connected to the drain of the memory cell M11 is A voltage of about 6 V is applied to the line D1. When the memory cell M11 is deselected, the word line W1
Either goes low (approximately GND) or the digit line D1 is open.

FIGS. 7A and 7B are a circuit diagram of a predecoder and a circuit diagram of an X decoder in the X decoder in FIG. 6, respectively. First, as shown in FIG.
The predecoder 20 in the conventional semiconductor memory device is
Inverter 2 for inverting upper address signals A2 and A3
1 and 22, and has a function of generating address selection signals X0 and X1 to be supplied to each of the NAND circuits 5a to be described below by a combination of upper address signals A2 and A3 and a signal obtained by inverting them. .

Next, as shown in FIG. 7B, an X decoder 1a as a word line driving circuit for outputting the voltage of the word line Wi includes a plurality of NANDs which take NAND logic of the address selection signals X0 and X1. A gate 5a, an inverter 6 for inverting its output, an nMOS 7, and pMOSs 8 and 9
It is composed of

The X decoder 1a as the word line driving circuit sets the potential of the word line Wi to the high power supply voltage VPP or GND according to the address selection signals X0 and X1 converted from the address signals ADD0 to ADD3. Therefore, in the X decoder 1a, there are two voltage supply paths that are switched by the address selection signals X0 and X1, namely, a path for supplying the high power supply voltage VPP to the word line Wi and a path for supplying GND.

First, a path for supplying the high power supply voltage VPP to the word line Wi is a path passing through the pMOS 8 via the pMOS 9, while a path for supplying GND is connected to the inverter 6.
Through the nMOS 7. At this time, the pMOS 9 forming the path for supplying VPP to the word line Wi
The source is supplied with the high power supply voltage VPP, and the gate thereof is supplied with a voltage enough to turn on the pMOS 9 sufficiently, for example, a voltage of about 8.5V. The drain of the pMOS 9 is connected to the source of the pMOS 8 and the gate thereof is supplied with the output Ki (i = 1, 2, 3,...) Of the NAND gate 5a. The gate input terminal X of the NAND gate 5a
Address selection signals determined by the upper address signals A2 and A3 are supplied to 0 and X1.

Then, in the path for supplying GND to the word line Wi, there is an inverter 6 for supplying GND, and the output Ki (i = 1, 2, 3,...) Of the NAND gate 5a is provided at the gate input terminal. ) Is supplied, and the output is supplied to the source of the nMOS 7. In addition, a voltage that turns off when the output of the inverter 6 is at the H level (almost VDD), for example, a voltage of about 4.5 V, is supplied to the gate of the nMOS 7.

Next, a specific circuit operation of the X decoder will be described. First, in the selected state in the write mode, all of the inputs X0 and X1 of the NAND gate 5a go to the H level (almost VDD). Accordingly, NA
The output Ki (i = 1, 2, 3,...) Of the ND gate 5a goes low (approximately GND), and the output of the inverter 6 goes high (approximately VDD). Thereby, the nMOS
7 is off. Since the pMOS 9 is on and then the pMOS 8 is on, the word line Wi is supplied with the high power supply voltage VPP. At this time, the word line W
6V is applied to the digit line Di of the memory cell connected to i.
Is supplied, a write current flows between the source and the drain of the memory cell to generate hot electrons and write is performed.

On the other hand, in the write mode, when it is not selected, at least one of the inputs X0 and X1 of the NAND gate 5a is at L level (substantially GND). Accordingly, the output Ki of the NAND gate 5a (i = 1, 2, 3,.
..) attains an H level (almost VDD), and the transconductance Gm of the pMOS 8 decreases. Therefore, the output of the inverter 6 becomes L level (almost GND), and nMO
S7 is turned on. Therefore, the transconductance Gm of the nMOS 7 is much larger than the transconductance Gm of the pMOS 8, so that the word line Wi is almost GN.
A voltage close to D is supplied. At this time, 6 is added to the digit line Di of the memory cell connected to the word line Wi.
Even if V is supplied, no write current flows through the memory cell, and no write is performed.

FIG. 8 is a timing chart for explaining the circuit operation in FIG. As shown in FIG. 8, for example, in the write mode, the memory cell M11 is followed by the memory cell M11.
When 22 is selected, first, an address signal A11 for selecting the memory cell M11 is input, and the address signal is taken into the address latch circuit 3 by the address latch signal CLKA. After a predetermined delay time when the address signal A11 propagates through the address latch circuit 3, that is, after a predetermined delay time, the input signals of the NAND gate 5a are all at H level, and the output K1 of the NAND gate 5a is changed from H level to L level. Becomes As a result, charges are accumulated in the word line W1, and the high power supply voltage VPP
Becomes

Next, an address signal A22 for selecting the memory cell M22 is inputted, and an address latch signal C22 is inputted.
The data is taken into the address latch circuit 3 by LKA. Similarly, after a delay time for passing through address latch circuit 3, at least one of the input signals of NAND gate 5a is output.
One goes to the L level, and the output K1 of the NAND gate 5a goes from the L level to the H level. Along with that, the electric charge stored in the word line W1 is discharged, and becomes the GND level.

On the other hand, for word line W2, NAND
All the input signals of the gate 5a become H level, and NAN
The output K2 of the D gate 5a changes from H level to L level. Along with that, charges are accumulated on the word line W2,
It becomes high power supply voltage VPP. At this time, charges are also accumulated in the digit line D2, and a voltage of 6 V is applied to write data to the memory cell M22.

[0016]

However, in the above-mentioned conventional semiconductor memory device, the word line W1 is actually set to G after the address signals ADD0 to ADD3 are input.
Until the ND level is reached, a delay time passing through the address latch circuit 3 and the X decoder 1a and a time for discharging the charges accumulated in the word line W1 are required. Therefore, in the period T1 from the time when the charge starts to be accumulated in the word line W2 and the digit line D2 to the time when the charge accumulated in the word line W1 is discharged, the word lines W1 and W1 are discharged.
There is a problem that erroneous writing is performed on the memory cell M12 using the digit line D2 as a control gate and a drain, respectively.

An object of the present invention is to discharge the electric charge of the word line of the selected memory cell before the electric charge is stored in the digit line of the memory cell to be selected next in the write mode, and to perform the non-selection. An object of the present invention is to provide a semiconductor memory device capable of preventing erroneous writing to a memory cell and improving reliability.

[0018]

A semiconductor memory device according to the present invention generates an X decoder for selecting one from a plurality of word lines connected to a memory cell and a pulse in synchronization with a switching timing of address selection. A pulse generation circuit, and sending an output of the pulse generation circuit to the X decoder before the address selection signal reaches the X decoder, thereby charging the word line of the selected memory cell. It is configured to discharge.

Further, the X decoder in the semiconductor memory device of the present invention is formed with a NAND gate which takes NAND logic of the address selection signal and the output of the pulse generation circuit.

Further, the pulse generation circuit in the semiconductor memory device according to the present invention may be configured such that the pulse generation circuit generates the pulse based on an address latch signal and a write enable signal.
It is formed with a gate.

In the semiconductor memory device of the present invention, the tip of the word line connected to the X decoder is
Each is connected to a discharging MOS element, and is formed so as to invert and supply an address latch signal to the gate of the discharging MOS element.

[0022]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a semiconductor memory device for explaining an embodiment of the present invention. As shown in FIG. 1, the semiconductor memory device according to the present embodiment shows a nonvolatile memory cell array including memory cells M11 to M33, and address signals ADD0 to ADD0 as peripheral circuits.
ADD3 is captured and held by the address latch signal CLKA, and the lower address signals A0, A1 are stored.
And an address latch circuit 3 for outputting upper address signals A2 and A3, a Y selector 4 for specifying digit lines D1 to D3 by lower address signals A0 and A1, and an address latch signal CLKA and a write enable WE. A pulse generation circuit 2 for generating a discharge pulse φA in synchronization with the selection switching timing
And an X decoder 1 for designating word lines W1 to W3 by upper address signals A2 and A3 and a pulse φA from pulse generation circuit 2. Note that the X decoder 1
As in the above-described conventional example, a predecoder is incorporated.

In such a semiconductor memory device, before the address selection signals X0 and X1 reach the X decoder 1, the output φA of the pulse generation circuit 2 is output to the X decoder 1.
To one of the word lines W1 to W3 connected to one of the selected memory cells M11 to M33.
To discharge two charges.

Here, the pulse generator 2 and the X decoder 1
Since the circuit configuration other than the above, that is, the address latch circuit 3 and the Y selector 4 have the same configuration as the above-described conventional example,
Detailed description is omitted.

FIG. 2 is a circuit diagram of the X decoder and the pulse generation circuit in FIG. As shown in FIG. 2, the X decoder 1 of the semiconductor memory device includes an address selection signal X0,
X1 and pulse φA are input to take NAND logic.
An AND gate 5 and an inverter 6, nMOS 7, pMOS 8 and 9 similar to the above-described conventional example.
In addition, the pulse generation circuit 2 outputs the address latch signal CLKA
, And inverts it, and writes only when the odd number of inverters 10 to 12 connected in series to create a predetermined delay time, the output of the final-stage inverter 12, the address latch signal CLKA and the H level (almost VDD). And a NAND gate 13 for inputting three signals of a write enable signal WE to be enabled and outputting the pulse φA as an output. In particular, the pulse generation circuit 2 switches the address latch signal CLKA so that the inverter 10
A pulse φA having a pulse width corresponding to the delay time of twelve three gates is generated.

FIG. 3 is a timing chart for explaining the circuit operation in FIGS. 1 and 2. As shown in FIG. 3, the write enable signal WE is at the H level (VDD = 5
V), it is assumed that the address A11 is input first, that is, the memory cell M11 is selected. At this time,
The word line W1 accumulates electric charge and has a voltage of 10V, and the digit line D1 has a voltage of 6V.

Next, when the address A22 is input, that is, when the memory cell M22 is to be selected, the address A22 is supplied to the address latch circuit 3 at the rise of the address latch signal CLKA. At this time, the pulse generation circuit 2 generates the pulse φ by the address latch signal CLKA.
A is generated, and this pulse φA is output to the NAND gate 5 of the X decoder 1 as a word line driving circuit that is generating the potential of the word line W1 as soon as possible. As a result, before the address selection signals X0 and X1 reach the input terminals X0 and X1 of the NAND gate 5, discharge of the charges stored in the word line W1 is started. Thereafter, at the time when the address selection signals X0 and X1 reach the NAND gate 5, that is, at the time t0 when the charge starts to be accumulated on the digit line D2, the charge on the word line W1 can be discharged. Therefore, erroneous writing to memory cell M12 is prevented by the pre-discharge based on pulse φA.

In short, in this embodiment, when memory cells having different word lines are sequentially selected, the charge of the word line of the previously selected memory cell is transferred to the digit line of the next memory cell. An erroneous write is prevented by discharging quickly before the charge is accumulated.

FIG. 4 is a circuit diagram of a semiconductor memory device for explaining another embodiment of the present invention. As shown in FIG. 4, the semiconductor memory device according to the present embodiment has, in addition to the memory device of FIG. 1 described above, nMOSs 15 and 1 at the tips of word lines W1 to W3 farthest from X decoder 1.
6 and 17, respectively, and these nMOSs 15 to 17 are connected.
Are connected to GND, and these nMOSs 15 to 1 are connected.
7 is provided with an inverter 14 for inverting and supplying the pulse φA from the pulse generation circuit 2 to each gate. The rest is the same as the circuit of FIG.

By adding the nMOSs 15 to 17 and the inverter 14, the discharge time is shortened as compared with the case where only the X decoder 1 discharges the charges stored in the word lines. For example, when discharging the electric charge stored in the word line W1, in addition to the X decoder 1, the number of paths that can be discharged via the nMOS 15 increases, and the discharge time can be further reduced.

FIG. 5 is a timing chart for explaining the circuit operation in FIG. As shown in FIG. 5, the fall of the word line W1 is steeper than the fall of the word line W1 of FIG. 3, that is, the speed at which the charges stored in the word line W1 are discharged is faster, and the digit line W1 is discharged. D2
Since the margin T2 with respect to the time when the accumulation of electric charges into the memory cell M12 can be increased, it is possible to reliably prevent erroneous writing to the memory cell M12.

In the above-described two embodiments, the example in which the inverters 10 to 12 are used as means for generating the pulse φA using the address latch signal CLKA has been described. However, other delay circuits, for example, a CR integration circuit and the like are used. Can also be realized. Further, although a pulse generated based on the address latch signal CLKA is taken as an example of a signal for discharging the charge of the word line, another signal synchronized with the address latch signal CLKA, for example, a precharge signal may be used. It can be realized similarly.

[0034]

As described above, the semiconductor memory device of the present invention is provided with the pulse generation circuit for generating the discharge pulse generated in synchronization with the address selection switching timing, and controls the X decoder by the pulse. Thus, before the charge is accumulated in the digit line of the memory cell selected next, the charge of the word line of the memory cell can be discharged, so that erroneous writing to the memory cell can be prevented. There is an effect that can be.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a semiconductor memory device for describing an embodiment of the present invention.

FIG. 2 is a diagram illustrating an X decoder and a pulse generation circuit in FIG.

FIG. 3 is a timing chart for explaining the circuit operation in FIGS. 1 and 2;

FIG. 4 is a circuit diagram of a semiconductor memory device for explaining another embodiment of the present invention.

FIG. 5 is a timing chart for explaining a circuit operation in FIG. 4;

FIG. 6 is a circuit diagram of a semiconductor memory device showing an example of the related art.

FIG. 7 is a diagram showing a predecoder circuit and an X decoder circuit inside the X decoder in FIG. 6;

FIG. 8 is a timing chart for explaining a circuit operation in FIG. 6;

[Explanation of symbols]

 Reference Signs List 1 X decoder 2 pulse generation circuit 3 address latch circuit 4 Y selector 5, 13 NAND gate 6, 10 to 12, 14 inverter 7 nMOS 8, 9 pMOS 15 to 17 nMOS M11 to M33 memory cell W1 to W3 word line D1 to D3 Digit wire

Claims (4)

[Claims] 1. An X decoder for selecting one of a plurality of word lines connected to a memory cell, and a pulse generating circuit for generating a pulse in synchronization with a switching timing of address selection, wherein an address selection signal is generated. A semiconductor memory device, wherein an output of the pulse generation circuit is sent to the X decoder before reaching the X decoder, thereby discharging a word line of a selected memory cell. 2. The X decoder according to claim 1, wherein said address selection signal and NAND of an output of said pulse generation circuit are NAND.
2. The semiconductor memory device according to claim 1, further comprising an AND gate. 3. The semiconductor memory device according to claim 1, wherein said pulse generation circuit includes a NAND gate which generates said pulse based on an address latch signal and a write enable signal. 4. A method according to claim 1, wherein each of the leading ends of the word lines connected to the X decoder is connected to a discharging MOS element, and an inverted address latch signal is supplied to the gate of the discharging MOS element. Item 2. The semiconductor memory device according to item 1.