JPH1069398A - Microcomputer for software debugging - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the microcomputer for software debugging which prevents an application system from malfunctioning or becoming abnormal in IE mode by varying the interruption priority level of SVI(interruption used exclusively to make a shift from user mode to IE mode) and then enabling multiple interruption control. SOLUTION: An interruption circuit control circuit 11 in an object microcomputer is provided with an interruption switching circuit 13, a break control circuit 12, and a multiple interruption circuit 14 to control priority-level interruption, and the multiple interruption circuit 14 and the break control circuit 12 which controls the shift to evaluation mode performs a multiple interruption request process in the evaluation mode. In the IE mode, a user's interruption request is accepted according to the priority to perform a user interruption process, so that a user program can be executed in real time. Further, a shift to the evaluation mode can be made even during the user program execution, real-time evaluation can be performed, and a secure return from an interruption destination can be made.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a microcomputer applicable as a software evaluation device, and more particularly to a microcomputer for software debugging.

[0002]

2. Description of the Related Art In-circuit emulators (hereinafter referred to as "in-circuit emulators")
"IE") is used when debugging an application system using a microcomputer. The IE is connected to the application system, and the software created by the user (referred to as a “user program”) is executed.
Called. During this user mode, an interrupt process dedicated to the IE is performed, and a transition is made to a program dedicated to the evaluation of the IE (hereinafter, this state is referred to as the “IE mode”), thereby confirming the software execution state and the hardware state. . The dedicated interrupt used when shifting from the user mode to the IE mode is called “SVI”.

[0003] IE executes SVI during execution of a user program.
When the error occurs, a monitor program, which is an SVI routine for controlling the IE evaluation function, is started, thereby performing a debugging operation. Also, SVI is a special interrupt process that is generated for performing an evaluation such as confirming an operation state of an application system. Therefore, the SVI is an interrupt that must be accepted at a time intended by a user during execution of a user program. is there. Thus, SVI is
Since the priority of the interrupt is the highest, no interrupt service other than the SVI is performed during the IE mode. Here, the user mode and the IE mode usually have different memory spaces for executing respective programs. This means that if the same memory space is used for the user memory and the IE mode, the memory area used in the IE mode must be determined in advance, and the memory area available for the user mode in the user mode is limited. It is because it will be.

An example of an actual system will be described with reference to FIG. FIG. 15 is a block diagram showing a part of a system for controlling a DC motor. A port output of the microcomputer is connected to an input of the motor control circuit, and an output of the motor control circuit is used as a power supply for the DC motor. In this system, an interrupt request is generated at regular intervals using a timer, and the output of the port is changed in the interrupt processing routine. In the debugging of this system, all the user interrupts are disabled after the transition to the IE mode, so that the port output of the microcomputer does not change while maintaining the state before the transition to the IE mode. If a DC motor overvoltage is applied depending on the state of the port being held, it is considered that the DC motor coil may be burned out. In order to protect such a system and prevent the system from being destroyed, it is necessary to accept an interrupt process for protecting the circuit even during the IE mode.

[0005]

As described in the above example, depending on the specifications of the applied system, a fatal abnormality may occur in the system unless an interrupt response is made at regular intervals. Further, in the IE mode, the user interrupt including the non-maskable interrupt is not serviced but is held, so that there is a problem that the cancellation of the interrupt response cannot be guaranteed. Also,
Simply lowering the SVI interrupt priority level will result in a user interrupt having a higher priority than SVI.
The transition to the IE mode at the timing at which evaluation is desired cannot be performed.

Accordingly, it is an object of the present invention to
An object of the present invention is to provide a microcomputer for software debugging that enables multiple interrupt control by changing the interrupt priority level of I and prevents malfunction or abnormality of an application system in the IE mode.

[0007]

In order to achieve the above object, a microcomputer according to the present invention has a user-undisclosed interrupt function,
It is characterized in that the priority of user interrupts including non-maskable interrupts can be arbitrarily changed. That is, SVI
Priority control means for setting interrupts to arbitrary priorities, comparing the priority of input interrupt signals and determining whether multiple interrupts are performed, and counting when interrupts are accepted Up,
It has a counter that counts down when returning from the interrupt routine, and a register for saving the PC (program counter) and PSW (program status word) when an SVI interrupt occurs. Also, as a save area for saving a PC value and a PSW value during interrupt processing, a separate storage area is provided for a user interrupt and an interrupt that is not disclosed to the user.

[0008]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a schematic configuration of a microcomputer according to an embodiment of the present invention. Here, one of several user interrupts is used as both a user interrupt terminal and an SVI terminal. Normally, this dual-purpose terminal is used as a user interrupt terminal. However, when evaluation is performed, if multiple interrupts with priorities are set to be performed in the IE mode, the terminal is switched to a terminal dedicated to the SVI signal generated in the microcomputer. , SVI as one of the interrupt signals, the priority of the SVI can be switched.

As a configuration for realizing this function, as shown in FIG. 1, in this embodiment, the microcomputer comprises an interrupt control circuit 11 (see FIG. 2)
A break control circuit 12 for controlling the transition between the IE mode and the user mode, an interrupt switching circuit 13 for controlling the interrupt and the priority of the interrupt (see FIG. 3), and processing of the IE mode from the user mode and the user interrupt request from the IE mode. A multiple interrupt circuit 14 (see FIG. 4) for surely performing a multiple interrupt process of executing a CPU core 15, three AND circuits, one OR circuit, and one NO
And a T circuit. Further, the IE has two memory spaces, and in the user mode and the IE mode,
The same address is shown, and the content differs depending on the mode. Therefore, when a general interrupt occurs during the user mode, the general stack 151 that saves the PC / PSW is saved.
And a dedicated save register 152 for saving the PC / PSW when returning to the IE mode from the user interrupt when processing a user interrupt received during the transition to the IE mode or during the IE mode.

The configuration and outline of each block will be described. First, when the CPU core 15 permits SVI,
When the SVIAK signal and the user interrupt request are permitted, two kinds of interrupt permission signals of the INTAK signal are output as "one pulse" to the interrupt switching circuit and the multiple interrupt circuit, and the PC and PSW used at the time of return are saved in the stack. After that, interrupt processing is started. When returning from the IE mode, the RETSVI signal is supplied to the interrupt switching circuit 13 and the multiple interrupt circuit 14 by "1 pulse" when returning from the user interrupt.
The output and saved PC and PSW values are read and a restoration process is performed.

The dedicated save register (hereinafter, referred to as an “SV register”) 152 includes a PC and a PSW of a user program at the time of starting an interrupt to the IE mode, and a monitor program at the time of starting an interrupt process for accepting the IE mode. PC and PSW values are saved. The general stack 151 is a register for saving the values of PC and PSW at the time of a user interrupt other than the above.

When an NMI (Non-Maskable Interrupt) is used as the SVI, a flag NMIS indicating this is used.
When the EL signal is “1” and the signal (SVMODE signal) indicating whether the current mode is the IE mode is “1”, the NMIBK becomes “1” and is output to the break control circuit. NMIS
When EL is "0", the external NMI is left
Output to Q.

The interrupt control circuit 11 will be described with reference to FIG. The interrupt control circuit 11 includes an interrupt signal selector (SEL1, SEL2) and an interrupt circuit 21. The interrupt circuit 21 is a commonly used interrupt circuit (for example, equivalent to μPD71059). A user interrupt request signal (hereinafter, an INT signal) is input thereto. The input of SEL1 is an INT6 signal and a signal indicating the satisfaction of the IE mode interrupt condition (hereinafter, a BRKCOND signal), and the output is connected to the INT6 terminal of the interrupt circuit 21. The control of SEL1 is a signal indicating that multiple interrupts having priority are performed.
This is performed using the L signal. When the INTSEL signal is “1”, it indicates that multiple interrupts having priority are performed, and SEL1
Outputs the BRKCOND signal to the INT6 terminal. That is, when performing multiple interrupts having priority, INT6
Is a terminal dedicated to interrupting the IE mode.

The output destination of the interrupt request signal (INTORG signal) from the interrupt circuit 21 is determined using a signal (SVMODE signal) indicating whether or not the IE mode is in the IE mode. If the SVMODE signal is "1", the signal is a user interrupt request signal (INTRQ signal).
Break control circuit 12 via OR circuit as TBK signal
Output to

The break control circuit 12 has an INTBK
Check the signal and other break conditions that occur, and
An interrupt signal (SVI signal) to the mode is output. S
The VI signal is “BRKCOND” when INTSEL = 1.
Output as a signal.

The interrupt switching circuit 13 will be described with reference to FIG. It comprises a personal computer I / F unit 31, an SVI permission circuit 32, an interrupt priority clear circuit 33, and an OR circuit. The personal computer I / F unit 31 plays a role of a user interface. PC I / F 3
1 has several registers for holding the set values for controlling the evaluation microcomputer. One of these registers contains I
There is a register that controls the NTSEL signal. By setting this register to “1” or “0”,
Determines whether to perform priority multiple interrupts. Further, one of the registers includes a register for controlling the NMISEL signal. By setting "1" or "0" in this register, it is determined whether or not the NMI is used as the SVI. INTSEL and NMISEL
Are exclusive.

The SVI permission circuit 32 receives the SVIAK signal from the CPU core 15 indicating that the SVI is permitted, and outputs an SVIINT signal, which is an SVI interrupt permission signal, to the interrupt circuit 21. The interrupt priority clear circuit 33 generates the SVCLRIP signal indicating that the interrupt processing requested by the currently processed INTn has been completed. This signal corresponds to the interrupt control circuit 1 of FIG.
In the interrupt circuit 21 (hereinafter referred to as INTC) 21, a register (for example, μPD710) indicating which interrupt terminal is currently performing the interrupt processing requested from which interrupt terminal is being executed.
59 ISR registers). This register
There are several bits corresponding to the INTn terminal, and this bit becomes “1” when the interrupt processing requested for the corresponding INT terminal is started. The SVCLRIP signal is
The bit indicating the end of the SVI of the aforementioned register is cleared. When the bit is cleared, processing of the interrupt having the next priority starts.

Referring to FIG. 4, the multiple interrupt circuit 14 has two types of counters, an SVI interrupt counter 41 and an INT interrupt counter 42. SVI
Upon transition to the IE mode, the interrupt counter 41 sets “+”
The counter counts up by "1", returns to the user mode from the IE mode, and decrements by "-1" .The output of this counter is SVCNT [1: 0] .The INT interrupt counter 42 has priority over SVI used during the IE mode. A user interrupt having a higher priority than the priority is generated. When the user interrupt is accepted and the interrupt process is executed (user mode 2 in FIG. 6), the count is incremented from “0” to “1”. Thereafter, each time a user interrupt occurs, the count is incremented by "+1". Also, every time it returns by the interrupt processing, it counts down by “−1”, and finally becomes “0” when it returns to the original IE mode. The output of this counter is INTCNT [n: 0].

The SVI flag 43 controls an SVINEST signal. The SVINEST signal is SVCNT
This signal is valid when [1: 0] is “2”. When this signal is valid, even if a new SVI signal is generated, it is ignored and ignored. The value of SVCNT [1: 0] is reset to “1” and the value of INTCNT [n: 0] is reset to “1”. In the SVMODE control circuit 44, the SVMO
Controls the DE signal. The control of this signal is as follows. When the SVIAK signal is "1" or RE
Valid when TI is “1”, INTCNT [n: 0] is “1” and SVCNT [1: 0] is “0” (“1”)
When RETSVI is "1" or INTAK is "1", it becomes invalid ("0"). When this signal is valid, it indicates that the mode is the IE mode.

Next, the operation will be described with reference to FIGS. FIG. 5 shows an outline of the operation of the prior art.
When an interrupt request SVI to the IE mode occurs during the user mode, the state transits to the IE mode in any case during the user mode. This is because SVI is the highest priority interrupt. 6 to 9 and 10
FIG. 14 is a transition diagram and a flowchart showing the basic operation of the present invention.

FIG. 10 shows an outline of the interrupt processing from the user mode to the IE mode. By setting a priority to each interrupt terminal (INTn) from the user's host machine (personal computer) through the personal computer I / F of the microcomputer and designating that a multiple interrupt with a priority is performed, the INT6 can execute the IE mode interrupt. Dedicated terminal. Here, when the SVI is generated, first, the state of the SVMODE signal is checked. At this time, if SVMODE = 1, this request is ignored.
If "0", SVMODE is set to "1", and the SVI request is accepted and the process is started.

Next, the value of SVCNT [1: 0] is checked in order to select the PC / PSW save destination. If this value is "1", it indicates that the interrupt processing to the IE mode has already been performed once, so that the save destination of the PC / PSW is SV2 of the SV register, and if "0", SV2 is selected. The PC and PSW at that time are saved in the register SV1. After that, the start address of the monitor program for controlling the IE mode is set and executed in the PC, thereby starting the SVI processing.

FIG. 11 shows an outline when a user interrupt request occurs during the IE mode. SV
User interrupt INT during I processing (IE mode)
When 1 occurs, the priority is compared with the priority of INT6 used for the SVI interrupt. At this time, if the priority of INT1 is lower than INT6, this request is ignored, and if it is higher, it is accepted and the next processing is performed. When the interrupt is accepted, the value of the counter INTCNT indicating how many times the user interrupt is processed during the IE mode is set to “+”.
1 ".

Next, the state of SVMODE is checked in order to select a PC and PSW save destination. If SVMODE is "1", it means that the mode is the IE mode. From here, the SV of the SV register is set to execute the user interrupt processing.
2, the PC and PSW are saved, and SVMODE is set to "0". When SVMODE is "0", it indicates that the user mode is being executed.
And save the PSW. After evacuation of PC and PSW, PC
Is set to the start address of the user interrupt, and this is executed.

There are three types of return processing. A return from the normal interrupt processing, a return from the IE mode to the user mode, and a return from the user mode (the user mode 2 in FIG. 6) generated during the IE mode to the IE mode. FIG. 12 shows the return from the IE mode to the user mode. First, RETSVI which is a command to return to the user mode
Occurs, the state of SVMODE is checked. SVM
If ODE is "1", this command is accepted and SVMO
Set “0” to DE. Next, SVCNT [1: 0]
Check the value of. If this is "1", the SV register S
Set the value of V1 to PC / PSW, and if "2", set S
Set the value of V2. PC and PSW set
The user program is executed from the state.

FIG. 13 shows a normal interrupt return instruction (R
(ETI) is schematically shown. When RETI occurs, the state of SVMODE is confirmed, and if "0", it is accepted. Next, the value of SVCNT [1: 0] is confirmed. If this value is "2", all interrupts in this state are ignored, and the return instruction is also ignored. If “0”, this instruction is accepted since no interrupt to the IE mode has ever occurred, and if “1”, INTCNT [n:
0]. Therefore, INTCNT [n: 0]
If = 1, since it is a return to the IE mode from the user interrupt processed during the IE mode, the SV register S
Set the value of V2 to PC / PSW. If the value is other than "1", the value of the general stack is set in the PC / PSW as a return process from the normal interrupt. After setting, PC /
Execute according to the value of PSW.

The above operation is shown in a transition diagram in FIGS.
FIG. 6 and 7 show transition and return from the user mode to the IE mode and from the IE mode to the user mode 2. FIG. For example, when INT6 has a certain priority and an interrupt request to the IE mode is generated by the SVI signal, the PC and PSW values of the user mode at that time are stored in the SV1 of the SV register, and the interrupt process is performed.
At this time, the SVMODE signal is “1” and SVCNT [1:
0] becomes “1” and transits to the IE mode. In the IE mode, when an INT1 user interrupt request signal having a higher priority than INT6 is generated, the INT1 user interrupt request is accepted, and the PC and PSW values of the IE mode control program at that time are stored in the SV register SV.
After saving to user mode 2, user interrupt processing is performed, and a transition is made to user mode 2. At this time, the counter value of INTCNT [n: 0] is incremented to “1”. Also, as shown in FIG. 7, when there is a request for INT2 having a lower priority than INT6, this request is ignored.

RE indicating a return instruction from user mode 2
When the TI signal is generated by the CPU core, the SV register SV2
Read the PC and PSW values inside and return to IE mode. At this time, INTCNT [n: 0] = 0. IE
RETS indicating return instruction to user mode during mode
When the VI signal is generated, the PC in SV1 of the SV register
And read the PSW value and return to the user mode (Fig. 1
3). At this time, SVCNT [1: 0] = 0, and one pulse of the SVCLRIP signal is output.

Further, during the IE mode, the user interrupt IN
When a user interrupt of INT2 lower in priority than T6 is requested, the interrupt priority of INT2 is changed to INT6.
Since it is lower, the interrupt request from INT2 is ignored. After that, IN6 with higher priority than INT6
When T1 is requested, it is accepted and interrupt processing and return processing are performed as described above.

FIG. 8 shows the operation when the user interrupt INT instruction occurs during the user mode 2. During the user mode 2, the interrupt request INT3 (INT
When 2 <INT3) occurs, the PC and PSW values on the user program at that time are saved to a general stack used by the user at the time of interrupt processing, then user interrupt processing is performed, and a transition is made to user mode 3. At this time, INT
CNT [n: 0] is incremented to 2. Also,
During user mode 3, the interrupt request INTm (IN
When T3 <INTm) occurs, the PC and PSW values in the user program at that time are saved in the general stack, and the user interrupt processing is performed and the mode transits to the user mode 4 as described above. At this time, INTCNT [n: 0] is incremented to 3.

As described above, the user mode 2 is in a state in which the user program is being executed, so that a normal user interrupt generated here can be accepted and interrupt processing can be performed. Each time the user interrupt process is performed, the value of INTCNT [n: 0] is incremented by "1". The depth of a user interrupt that can be interrupted during the IE mode (the count value of INTCNT [n: 0]) can be interrupted by the number of interrupt terminals excluding one occupied by SVI among the maximum number of interrupt terminals. it can.

In the return processing, when a return instruction RETI signal is generated from the CPU core in the user mode 4, the latest PC and PSW values in the general stack are read, a normal return processing is performed, and a transition to the user mode 3 is made. , INTCNT
[N: 0] = 2 is decremented. Further, in the user mode 3, when a return instruction is issued as described above, a return process such as reading the contents of the general stack is performed, and the process returns to the user mode 2. At this time, INTCNT
The value of [n: 0] is “1”. In this way, upon return, the value of INTCNT [n: 0] is decremented by "1" each time the normal return instruction is executed, and INTCNT is decremented.
Until the value of [n: 0] becomes "1", the same processing as that of normal user interrupt return is performed. The return process from the user mode 2 is as follows.
The value of SV2 of the V register is read, and a return process is performed.
Return to the IE mode. At this time, INTCNT [n:
0] is “0”.

FIG. 14 shows the flow of an exception return instruction when returning from the user mode to the IE mode in the RETI instruction. In this state, the mode directly returns to the first user mode without returning to the IE mode. This will be described with reference to FIG. A special case in which an SVI occurs during the user mode 3 is shown. This is a compulsory SVI interruption due to an abnormality of the user's application system, and is not intentionally performed by the user. Since the SVMODE signal is "0" even in the user mode 3, SVI can be accepted. At this time, the PC and PSW values in the user mode 3 are the urgent (forced) I
Since this is an interrupt instruction to the E mode, both SV1 and SV2 of the SV register are used, but they overwrite the latest contents of SV2. After storing the PC and PSW, S
VI processing is performed, and IE mode 2 is set. At the same time, S
The VMODE signal and the SVINEST signal become “1”, and the SVCNT [1: 0] value is incremented to “2”. As shown in the above state, SVINEST
When signal = 1 and SVCNT [n: 0] ≧ 2, all interrupts occurring thereafter are ignored.

To return from this state, RETSVI, which is a command to return to the user mode during the IE mode 2, is issued by the CPU.
When a core is generated, the SV of PC and PSW of SV2 in the SV register
The value is read, a return process is performed, and the process returns to the user mode 3. Further, the normal user interrupt return processing is performed until the user mode 2 in which the value of the INTCNT [n: 0] becomes “1”. In the user mode 2, the return instruction RETI
Occurs, since the value of SV2 in the SV register has already been used, the value of SV1 is read, and the mode does not return to the IE mode, but directly returns to the first user mode in which the SV1 is written. SVINEST is SV
It is cleared ("0") when the values of CNT [1: 0] and INTCNT [n: 0] become "1".

[0035]

As described above, the present invention provides an SVI
Priority control means for setting an interrupt to an arbitrary priority including an NMI is provided, the priority of input interrupt signals is compared, it is determined whether or not multiple interrupts are performed, and the interrupt is accepted. And a counter that counts down when returning from the interrupt routine, and PC and P at the time of the SVI interrupt.
By providing a register for saving the SW,
Even during the E mode, the user can respond to a user interrupt, and the user can arbitrarily change the interrupt priority level in the IE mode. In addition, during the user interrupt process accepted during the IE mode, the mode can be further shifted to the IE mode, and the mode can be accurately restored. Since it is possible to immediately respond to a user's interrupt request during the IE mode, real-time operation can be confirmed. In addition, when there are several types of program modules, the priority is determined for each module so that real-time operation can be individually performed. Execution and evaluation can also be performed.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a microcomputer according to an embodiment of the present invention.

FIG. 2 is a block diagram of an interrupt control circuit.

FIG. 3 is a block diagram of an interrupt switching circuit.

FIG. 4 is a block diagram of a multiple interrupt circuit.

FIG. 5 is a diagram showing a transition operation in the IE mode.

FIG. 6 is a first transition diagram illustrating an outline of a basic operation of the present invention.

FIG. 7 is a second transition diagram showing the outline of the basic operation of the present invention.

FIG. 8 is a first transition diagram illustrating an overview of multiple interrupts.

FIG. 9 is a second transition diagram illustrating an outline of multiple interrupts.

FIG. 10 is a flowchart illustrating a procedure of an SVI operation.

FIG. 11 is a flowchart showing a user interrupt processing procedure during the IE mode.

FIG. 12 is a flowchart illustrating a return process in a RETSVI instruction.

FIG. 13 is a flowchart showing a return process in a RETI instruction.

FIG. 14 is a flowchart of exception return.

FIG. 15 is a circuit configuration diagram of an example of a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Interrupt control circuit 12 Break control circuit 13 Interrupt switching circuit 14 Multiple interrupt circuit 15 CPU core 21 Interrupt circuit 31 Personal computer I / F 32 SVI enable circuit 33 Interrupt priority clear circuit 41 SVI interrupt counter 42 INT interrupt counter 43 CVI flag 44 CVMODE control circuit

Claims (3)

[Claims] 1. A microcomputer for software debugging having an interrupt function that is not disclosed by a user and wherein the priority of the interrupt that is not disclosed by the user and the priority of the user interrupt can be arbitrarily changed. 2. An apparatus according to claim 1, further comprising: priority control means for setting an SVI interrupt used when shifting from a user mode to an IE (in-circuit emulator) mode to an arbitrary priority including a non-maskable interrupt. A functional unit that compares the priority of interrupt signals and determines whether or not multiple interrupts are performed; a counter that counts up when an interrupt is accepted and counts down when returning from an interrupt routine; and a PC (program) for SVI interrupts 2. The microcomputer for software debugging according to claim 1, further comprising: a register for saving a counter and a PSW (program status word). 3. The software debugging microcomputer according to claim 2, wherein a separate storage area is provided for a user interrupt and a user private interrupt as a save area for a PC value and a PSW value during interrupt processing. .