JPH1065105A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH1065105A JPH1065105A JP8217440A JP21744096A JPH1065105A JP H1065105 A JPH1065105 A JP H1065105A JP 8217440 A JP8217440 A JP 8217440A JP 21744096 A JP21744096 A JP 21744096A JP H1065105 A JPH1065105 A JP H1065105A
- Authority
- JP
- Japan
- Prior art keywords
- digital circuit
- section
- circuit section
- dedicated
- bonding pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 239000003990 capacitor Substances 0.000 claims abstract description 32
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 8
- 239000000758 substrate Substances 0.000 abstract description 9
- 230000001052 transient effect Effects 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
(57)【要約】
【課題】 ディジタル回路部のパッド・リードワイヤ・
リードフレームを増やすことなく、ディジタル回路部に
発生したノイズを小さくでき、チップの基板等を通じて
アナログ部へ伝わるノイズ信号を小さくできる半導体集
積回路を得る。
【解決手段】 ディジタル回路部ＤＢとアナログ回路部
ＡＢが混在する半導体集積回路において、ディジタル回
路部ＤＢの内部配線Ｍ１に接続され電流が流通するボン
ディングパッドＢ１と、前記ディジタル回路部ＤＢの内
部配線Ｍ１に前記ボンディングパッドＢ１が接続される
配線とは別の配線で接続されたバイパスコンデンサＣ１
を付けるための専用のボンディングパッドＢ２とを設
け、前記専用のボンディングパッドＢ２によりバイパス
コンデンサＣ１を付けるためのパスを構成するようにし
た。
(57) [Summary] [Problem] Pads, lead wires, and the like for digital circuits
A semiconductor integrated circuit capable of reducing noise generated in a digital circuit portion without increasing the number of lead frames and reducing a noise signal transmitted to an analog portion through a chip substrate or the like. SOLUTION: In a semiconductor integrated circuit in which a digital circuit part DB and an analog circuit part AB are mixed, a bonding pad B1 connected to an internal wiring M1 of the digital circuit part DB and through which a current flows, and an internal wiring M1 of the digital circuit part DB Is connected to a bypass capacitor C1 connected to a wire different from the wire to which the bonding pad B1 is connected.
And a dedicated bonding pad B2 for attaching a bypass capacitor C1 is provided by the dedicated bonding pad B2.
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、アナログ回路部
とディジタル回路部が混在する半導体集積回路に関する
ものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit in which an analog circuit section and a digital circuit section are mixed.
【０００２】[0002]
【従来の技術】図２に、従来の技術を示す。図におい
て、Ｂ１〜Ｂ８はボンディングパッド、Ｗ１〜Ｗ８はリ
ードワイヤ、Ｆ１〜Ｆ８はリードフレームである。2. Description of the Related Art FIG. In the figure, B1 to B8 are bonding pads, W1 to W8 are lead wires, and F1 to F8 are lead frames.
【０００３】次に、従来の技術について説明する。ディ
ジタル回路部ＤＢで発生したノイズがアナログ回路部Ａ
Ｂに与える影響を少なくするには、ディジタル回路部Ｄ
Ｂからアナログ回路部ＡＢへのノイズの伝達を小さくす
る方策と、ディジタル回路部ＤＢで発生するノイズその
ものを小さくする方策がある。Next, a conventional technique will be described. Noise generated in the digital circuit section DB is analog circuit section A
To reduce the effect on B, the digital circuit D
There are measures to reduce the transmission of noise from B to the analog circuit part AB and measures to reduce the noise itself generated in the digital circuit part DB.
【０００４】前者には、ディジタル回路部ＤＢの電源と
アナログ回路部ＡＢの電源、ディジタル回路部ＤＢの接
地部（以下、ＧＮＤという）とアナログ回路部ＡＢのＧ
ＮＤを分ける手段があり、後者では、ディジタル回路部
ＤＢで発生したノイズを小さくする手段として、ディジ
タル部ＤＢ専用ＧＮＤラインのインピーダンスを小さく
することが挙げられる。The former includes a power supply for the digital circuit section DB and a power supply for the analog circuit section AB, a ground section (hereinafter referred to as GND) for the digital circuit section DB, and a power supply for the analog circuit section AB.
There is a means for dividing the ND. In the latter, as a means for reducing the noise generated in the digital circuit section DB, there is a method of reducing the impedance of the GND line dedicated to the digital section DB.
【０００５】そのために、パッド（Ｂ１・Ｂ２・Ｂ３・
Ｂ４）の数を増やし、リードワイヤ（Ｗ１・Ｗ２・Ｗ３
・Ｗ４）・リードフレーム（Ｆ１・Ｆ２・Ｆ３・Ｆ４）
の本数を増やすという対策が採られていた。For this purpose, pads (B1, B2, B3,
B4) to increase the number of lead wires (W1, W2, W3).
・ W4) ・ Lead frame (F1, F2, F3, F4)
Measures were taken to increase the number.
【０００６】[0006]
【発明が解決しようとする課題】従来のディジタルノイ
ズ軽減対策回路では、以上のように構成されているの
で、ディジタル回路部ＤＢで発生する過渡電流（ディジ
タル回路を構成するＡＮＤ回路・ＯＲ回路・ＩＮＶ回路
などがｏｎ・ｏｆｆスイッチするときに流れる瞬間的な
電流）が内部配線Ｍ１、ボンディングパッドＢ１・Ｂ２
・Ｂ３・Ｂ４、リードワイヤＷ１・Ｗ２・Ｗ３・Ｗ４、
フレームＦ１・Ｆ２・Ｆ３・Ｆ４を通り外部のディジタ
ル回路部ＤＢの専用ＧＮＤ：ＤＧＮＤに流れる。Since the conventional digital noise reduction circuit is constructed as described above, the transient current generated in the digital circuit section DB (AND circuit / OR circuit / INV constituting the digital circuit) Instantaneous current flowing when a circuit or the like is turned on / off) is applied to the internal wiring M1 and the bonding pads B1 and B2.
· B3 · B4, lead wires W1 · W2 · W3 · W4,
It flows through the frames F1, F2, F3, and F4 to the dedicated GND: DGND of the external digital circuit section DB.
【０００７】リードワイヤ・フレームの抵抗成分やイン
ダクタンス成分のためチップのディジタル回路部専用Ｇ
ＮＤにノイズが発生する。このノイズは、次式に示す通
り、ボンディングパッド・リードワイヤ・フレームのイ
ンピーダンスＺＭ・ＺＷ・ＺＬの和（ＺＭ＋ＺＷ＋Ｚ
Ｌ）と過渡電流との積に比例する。 ノイズ＝過渡電流×（ＺＭ＋ＺＷ＋ＺＬ）[0007] Due to the resistance component and the inductance component of the lead wire frame, a dedicated G for the digital circuit part of the chip
Noise occurs in the ND. This noise is, as shown in the following equation, the sum of the impedances ZM, ZW, ZL of the bonding pad, the lead wire, and the frame (ZM + ZW + Z
L) is proportional to the product of the transient current. Noise = transient current x (ZM + ZW + ZL)
【０００８】そこで、ディジタル回路部ＤＢ専用ＧＮＤ
で発生したノイズを小さくするためには、ボンディング
パッド・リードワイヤ・フレームの数を増やさなければ
ならないという欠点があった。Therefore, the GND dedicated to the digital circuit DB is used.
There is a disadvantage that the number of bonding pads, lead wires and frames must be increased in order to reduce the noise generated in the above.
【０００９】この発明は、ディジタル回路部のパッド・
リードワイヤ・リードフレームを増やすことなく、ディ
ジタル回路部に発生したノイズを小さくでき、チップの
基板等を通じてアナログ部へ伝わるノイズ信号を小さく
できて、このような欠点を除去することができる半導体
集積回路を得ようとするものである。According to the present invention, there is provided a pad for a digital circuit section.
A semiconductor integrated circuit that can reduce the noise generated in the digital circuit section without increasing the number of lead wires and lead frames, can reduce the noise signal transmitted to the analog section through the chip substrate, etc., and can eliminate such defects. It is trying to get.
【００１０】第１の発明は、ディジタル回路部にバイパ
スコンデンサを付けるための専用ボンディングパッドを
設けることにより、ディジタル回路部のパッド・リード
ワイヤ・リードフレームを増やすことなく、ディジタル
回路部に発生したノイズを小さくでき、チップの基板等
を通じてアナログ部へ伝わるノイズ信号を小さくできる
半導体集積回路を得ようとするものである。According to a first aspect of the present invention, by providing a dedicated bonding pad for attaching a bypass capacitor to the digital circuit section, the noise generated in the digital circuit section can be increased without increasing the number of pads, lead wires and lead frames in the digital circuit section. It is an object of the present invention to obtain a semiconductor integrated circuit that can reduce the noise signal transmitted to the analog section through a chip substrate or the like.
【００１１】第２の発明は、ディジタル回路部の専用Ｇ
ＮＤにバイパスコンデンサを付けるためのパスを設け、
外部ディジタル回路部専用ＧＮＤとは別のＧＮＤとの間
にバイパスコンデンサを付けることにより、ディジタル
回路部専用ＧＮＤのパッド・リードワイヤ・リードフレ
ームを増やすことなく、ディジタル部ディジタル回路部
に発生したノイズを小さくでき、チップの基板等を通じ
てアナログ回路部へ伝わるノイズ信号を小さくできる半
導体集積回路を得ようとするものである。The second invention is a digital circuit section dedicated G
Provide a path for attaching a bypass capacitor to ND,
By attaching a bypass capacitor between the GND for the external digital circuit and another GND, the noise generated in the digital circuit for the digital section can be reduced without increasing the number of pads, lead wires and lead frames of the GND for the digital circuit. An object of the present invention is to provide a semiconductor integrated circuit that can be made smaller and can reduce a noise signal transmitted to an analog circuit section through a chip substrate or the like.
【００１２】第３の発明は、バイパスコンデンサを付け
るためのパスを電源ラインに設けることにより、ディジ
タル回路部のパッド・リードワイヤ・リードフレームを
増やすことなく、ディジタル回路部に発生したノイズを
小さくでき、チップの基板等を通じてアナログ部へ伝わ
るノイズ信号を小さくできる半導体集積回路を得ようと
するものである。According to a third aspect of the present invention, by providing a path for attaching a bypass capacitor to the power supply line, noise generated in the digital circuit section can be reduced without increasing the number of pads, lead wires, and lead frames in the digital circuit section. Another object of the present invention is to provide a semiconductor integrated circuit that can reduce a noise signal transmitted to an analog unit through a chip substrate or the like.
【００１３】[0013]
【課題を解決するための手段】第１の発明の半導体集積
回路においては、ディジタル回路部とアナログ回路部が
混在する半導体集積回路において、ディジタル回路部の
内部配線に接続され電流が流通するボンディングパッド
と、前記ディジタル回路部の内部配線に前記ボンディン
グパッドが接続される配線とは別の配線で接続されたバ
イパスコンデンサを付けるための専用のボンディングパ
ッドとを設け、前記専用のボンディングパッドによりバ
イパスコンデンサを付けるためのパスを構成するように
したことを特徴とする。According to a first aspect of the present invention, in a semiconductor integrated circuit in which a digital circuit section and an analog circuit section are mixed, a bonding pad connected to an internal wiring of the digital circuit section and through which a current flows. And a dedicated bonding pad for attaching a bypass capacitor connected to the internal wiring of the digital circuit unit by a wiring different from the wiring to which the bonding pad is connected, and a bypass capacitor is provided by the dedicated bonding pad. A feature is to form a path for attaching.
【００１４】第２の発明の半導体集積回路においては、
ディジタル回路部とアナログ回路部が混在する半導体集
積回路において、ディジタル回路部の専用接地部と、こ
のデジタル回路部の専用接地部に接続されディジタル回
路部の電流が流れ出る接地部ボンディングパッドと、デ
ィジタル回路部の専用接地部とディジタル回路部の電流
が流れ出る接地部ボンディングパッドが接続される配線
とは別の配線でディジタル回路部の専用接地部に接続さ
れたバイアスコンデンサを付けるための専用のボンディ
ングパッドとを備え、ディジタル回路部の電流が流れ出
る接地部ボンディングパッドがリードワイヤ・リードフ
レームを通って接続される外部との間にバイパスコンデ
ンサを付けることを特徴とする。In the semiconductor integrated circuit of the second invention,
In a semiconductor integrated circuit in which a digital circuit section and an analog circuit section are mixed, a dedicated ground section of a digital circuit section, a ground section bonding pad connected to the dedicated ground section of the digital circuit section and through which current of the digital circuit section flows, A dedicated bonding pad for attaching a bias capacitor connected to the dedicated grounding section of the digital circuit section with a wiring different from the wiring to which the dedicated grounding section of the section and the grounding section bonding pad from which the current of the digital circuit section flows out And a bypass capacitor is provided between the ground bonding pad from which the current of the digital circuit flows and the outside connected through the lead wire / lead frame.
【００１５】第３の発明の半導体集積回路においては、
バイパスコンデンサを付けるためのパスを電源ラインに
設けることを特徴とする。In a semiconductor integrated circuit according to a third aspect of the present invention,
A path for attaching a bypass capacitor is provided in the power supply line.
【００１６】この発明の実施の形態におけるディジタル
ノイズ軽減対策回路の特徴は、チップのディジタル回路
部専用ＧＮＤ上にバイパスコンデンサＣ１を付けるため
の専用ボンディングパッドＢ２を設け、ディジタル回路
部の電流が流れ出る外部ディジタル専用ＧＮＤとは別の
ＧＮＤとの間にバイパスコンデンサＣ１を付けることで
ある。A feature of the digital noise reduction countermeasure circuit according to the embodiment of the present invention is that an exclusive bonding pad B2 for attaching a bypass capacitor C1 is provided on a GND dedicated to a digital circuit portion of a chip, and an external current from which a current of the digital circuit portion flows. That is, a bypass capacitor C1 is provided between the digital dedicated GND and another GND.
【００１７】この発明においては、次のような作用を有
する。この発明におけるディジタルノイズ軽減対策回路
は、今までディジタル回路部と混載が難しいとされてき
た微小信号を扱う回路や高利得の増幅器などのアナログ
回路の混載を可能とする。The present invention has the following operation. The digital noise reduction countermeasure circuit according to the present invention enables the integration of analog circuits such as circuits for handling small signals and high-gain amplifiers, which have been considered difficult to mount together with digital circuit units.
【００１８】[0018]
実施の形態１．以下、この発明の実施の一形態を図に基
づいて説明する。図１は、この発明の実施の一形態によ
るディジタルノイズ軽減対策を示す。図１において、Ｄ
Ｂはデジタル回路部、ＡＢはアナログ回路部、Ｍ１はデ
ジタル回路部ＤＢの内部配線、Ｂ１〜Ｂ８はボンディン
グパッド、Ｗ１〜Ｗ８はリードワイヤ、Ｆ１〜Ｆ８はリ
ードフレーム、ＤＧＮＤはデジタル回路部ＤＢ専用ＧＮ
Ｄ、ＤＧＮＤ［ＯＵＴ］は外部デジタル回路部ＤＢ専用
ＧＮＤ、ＡＧＮＤはアナログ回路部ＡＢ専用ＧＮＤであ
る。Embodiment 1 FIG. Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a measure for reducing digital noise according to an embodiment of the present invention. In FIG. 1, D
B is a digital circuit portion, AB is an analog circuit portion, M1 is an internal wiring of the digital circuit portion DB, B1 to B8 are bonding pads, W1 to W8 are lead wires, F1 to F8 are lead frames, and DGND is a digital circuit portion DB. GN
D and DGND [OUT] are GNDs dedicated to the external digital circuit section DB, and AGND is a GND dedicated to the analog circuit section AB.
【００１９】この実施の形態と従来例との相違点は、Ｉ
Ｃチップ上のディジタル回路部専用ＧＮＤ：ＤＧＮＤラ
イン上にバイパスコンデンサＣ１を付けるためのボンデ
ィングパッドＢ２を設け、ディジタル回路部ＤＢの電流
が流れ出る外部ディジタル回路専用ＧＮＤとは別のＧＮ
Ｄとの間にバイパスコンデンサＣ１を付けている点であ
る。The difference between this embodiment and the conventional example is that
Digital circuit section dedicated GND on C chip: bonding pad B2 for attaching bypass capacitor C1 is provided on the DGND line, and GND different from external digital circuit dedicated GND through which current of digital circuit section DB flows.
D is a point that a bypass capacitor C1 is provided between D and D.
【００２０】次に、動作について説明する。なお、ディ
ジタル回路部の動作としては従来回路と同じである。図
１において、ディジタル回路部ＤＢが通常の動作をして
いるものとする。このとき、ディジタル回路部ＤＢの過
渡電流がディジタル回路部ＤＢの専用ＧＮＤ：ＤＧＮＤ
の内部配線Ｍ１・ボンディングパッドＢ１・リードワイ
ヤＷ１・フレームＦ１を通って外部ディジタル回路部専
用ＧＮＤ：ＤＧＮＤ［ＯＵＴ］に流れる。Next, the operation will be described. The operation of the digital circuit is the same as that of the conventional circuit. In FIG. 1, it is assumed that the digital circuit section DB is operating normally. At this time, the transient current of the digital circuit unit DB is changed to the dedicated GND: DGND of the digital circuit unit DB.
Through the internal wiring M1, the bonding pad B1, the lead wire W1, and the frame F1 to the external digital circuit section dedicated GND: DGND [OUT].
【００２１】リードワイヤＷ１・リードフレームＦ１の
抵抗成分・インダクタンス成分と過渡電流により、チッ
プディジタル回路部専用ＧＮＤ：ＤＧＮＤにノイズ信号
が現われる。このディジタル回路部ＤＢ専用ＧＮＤ：Ｄ
ＧＮＤに現れたノイズ信号がＩＣチップの基板を通りア
ナログ部ＡＢ専用ＧＮＤ：ＡＧＮＤに現れる。このアナ
ログ部ＡＢ専用ＧＮＤ：ＡＧＮＤに乗ったノイズ信号が
アナログ回路部ＡＢの定電流回路や増幅器などで増幅さ
れ、大きなノイズとなってアナログ信号出力に出てく
る。Due to the resistance component / inductance component of the lead wire W1, the lead frame F1, and the transient current, a noise signal appears in the GND: DGND dedicated to the chip digital circuit unit. This digital circuit section DB dedicated GND: D
The noise signal appearing on GND passes through the substrate of the IC chip and appears on the GND dedicated to the analog section AB: AGND. The noise signal on the analog section AB dedicated GND: AGND is amplified by a constant current circuit, an amplifier, or the like of the analog circuit section AB, and appears as analog noise at the analog signal output.
【００２２】そこで、ディジタル回路部ＤＢの専用ＧＮ
Ｄ：ＤＧＮＤに発生したノイズ信号をボンディングパッ
ドＢ２・リードワイヤＷ２・フレームＦ２を通して付け
られたバイパスコンデンサＣ１で小さくする。発生した
ノイズ信号を小さくすることで、アナログ回路部ＡＢに
伝わるノイズ信号も小さくすることができ、アナログ信
号出力のノイズ信号を軽減することができる。Therefore, the dedicated GN of the digital circuit section DB
D: The noise signal generated in DGND is reduced by the bypass capacitor C1 attached through the bonding pad B2, the lead wire W2, and the frame F2. By reducing the generated noise signal, the noise signal transmitted to the analog circuit portion AB can also be reduced, and the noise signal of the analog signal output can be reduced.
【００２３】ここで重要なことは、バイパスコンデンサ
Ｃ１のつながるＧＮＤ：ＡＧＮＤが、外部ディジタル回
路部専用ＧＮＤ：ＤＧＮＤ［ＯＵＴ］とは別のＧＮＤで
あることである。What is important here is that GND: AGND connected to the bypass capacitor C1 is different from GND dedicated to the external digital circuit section: DGND [OUT].
【００２４】実施の形態２．また、上記実施の形態１で
はディジタル回路部ＤＢ専用ＧＮＤライン上にバイパス
コンデンサを付けるためのパスを設ける例を示したが、
このバイパスコンデンサを付けるためのパスを電源ライ
ンに設けてもよい。Embodiment 2 FIG. Also, in the first embodiment, an example is shown in which a path for attaching a bypass capacitor is provided on the GND line dedicated to the digital circuit unit DB.
A path for attaching the bypass capacitor may be provided in the power supply line.
【００２５】以上のように、この発明の実施の形態によ
れば、ディジタル回路部の専用ＧＮＤにバイパスコンデ
ンサを付けるためのパスを設け、外部ディジタル回路部
専用ＧＮＤとは別のＧＮＤとの間にバイパスコンデンサ
を付けることにより、ディジタル回路部専用ＧＮＤのパ
ッド・リードワイヤ・リードフレームを増やすことな
く、ディジタル部ディジタル回路部に発生したノイズを
小さくすることができ、チップの基板等を通じてアナロ
グ回路部へ伝わるノイズ信号を小さくすることができ
る。As described above, according to the embodiment of the present invention, a path for attaching a bypass capacitor is provided to the dedicated GND of the digital circuit section, and the path is provided between the GND dedicated to the external digital circuit section and another GND. By attaching a bypass capacitor, noise generated in the digital circuit section of the digital section can be reduced without increasing the number of pads, lead wires, and lead frames of the GND dedicated to the digital circuit section. The transmitted noise signal can be reduced.
【００２６】[0026]
【発明の効果】第１の発明によれば、ディジタル回路部
にバイパスコンデンサを付けるための専用ボンディング
パッドを設けることにより、ディジタル回路部のパッド
・リードワイヤ・リードフレームを増やすことなく、デ
ィジタル回路部に発生したノイズを小さくでき、チップ
の基板等を通じてアナログ部へ伝わるノイズ信号を小さ
くできる半導体集積回路を得ることができる。According to the first aspect of the present invention, by providing a dedicated bonding pad for attaching a bypass capacitor to the digital circuit section, the digital circuit section can be provided without increasing the number of pads, lead wires, and lead frames in the digital circuit section. In this case, it is possible to obtain a semiconductor integrated circuit capable of reducing noise generated in the analog section and reducing a noise signal transmitted to the analog section through a chip substrate or the like.
【００２７】第２の発明によれば、ディジタル回路部の
専用ＧＮＤにバイパスコンデンサを付けるためのパスを
設け、外部ディジタル回路部専用ＧＮＤとは別のＧＮＤ
との間にバイパスコンデンサを付けることにより、ディ
ジタル回路部専用ＧＮＤのパッド・リードワイヤ・リー
ドフレームを増やすことなく、ディジタル回路部に発生
したノイズを小さくでき、チップの基板等を通じてアナ
ログ回路部へ伝わるノイズ信号を小さくできる半導体集
積回路を得ることができる。According to the second aspect of the present invention, a path for attaching a bypass capacitor is provided to the dedicated GND of the digital circuit section, and a GND different from the GND dedicated to the external digital circuit section is provided.
By adding a bypass capacitor between the two, the noise generated in the digital circuit part can be reduced without increasing the number of pads, lead wires, and lead frames of the GND dedicated to the digital circuit part, and transmitted to the analog circuit part through a chip substrate or the like. A semiconductor integrated circuit that can reduce a noise signal can be obtained.
【００２８】第３の発明によれば、バイパスコンデンサ
を付けるためのパスを電源ラインに設けることにより、
ディジタル回路部のパッド・リードワイヤ・リードフレ
ームを増やすことなく、ディジタル回路部に発生したノ
イズを小さくでき、チップの基板等を通じてアナログ部
へ伝わるノイズ信号を小さくできる半導体集積回路を得
ることができる。According to the third aspect, by providing a path for attaching a bypass capacitor to the power supply line,
It is possible to obtain a semiconductor integrated circuit that can reduce noise generated in the digital circuit section without increasing the number of pads, lead wires, and lead frames in the digital circuit section, and that can reduce a noise signal transmitted to the analog section through a chip substrate or the like.
【図１】 この発明の実施の一形態を示す構成図であ
る。FIG. 1 is a configuration diagram showing an embodiment of the present invention.
【図２】 従来の技術を示す構成図である。FIG. 2 is a configuration diagram showing a conventional technique.
ＤＧＮＤ ディジタル回路部専用接地部、ＤＧＮＤ［Ｏ
ＵＴ］ 外部ディジタル回路部専用接地部、ＡＧＮＤ
アナログ回路部専用接地部、Ｍ１ デジタル回路部ＤＢ
の内部配線、Ｂ１〜８ ボンディングパッド、Ｗ１〜８
リードワイヤ、Ｆ１〜７ リードフレーム、Ｃ１ バ
イパスコンデンサ。DGND Digital circuit section dedicated grounding section, DGND [O
UT] External digital circuit section dedicated grounding section, AGND
Grounding section for analog circuit section, M1 digital circuit section DB
Internal wiring, B1-8 bonding pads, W1-8
Lead wire, F1-7 lead frame, C1 bypass capacitor.
Claims (3)
在する半導体集積回路において、ディジタル回路部の内
部配線に接続され電流が流通するボンディングパッド
と、前記ディジタル回路部の内部配線に前記ボンディン
グパッドが接続される配線とは別の配線で接続されたバ
イパスコンデンサを付けるための専用のボンディングパ
ッドとを設け、前記専用のボンディングパッドによりバ
イパスコンデンサを付けるためのパスを構成するように
したことを特徴とする半導体集積回路。In a semiconductor integrated circuit in which a digital circuit section and an analog circuit section are mixed, a bonding pad connected to an internal wiring of the digital circuit section and through which a current flows, and the bonding pad connected to an internal wiring of the digital circuit section. A dedicated bonding pad for attaching a bypass capacitor connected by a separate wire from the wiring to be provided, and a path for attaching a bypass capacitor is formed by the dedicated bonding pad. Semiconductor integrated circuit.
在する半導体集積回路において、ディジタル回路部の専
用接地部と、このディジタル回路部の専用接地部に接続
されディジタル回路部の電流が流れ出る接地部ボンディ
ングパッドと、ディジタル回路部の専用接地部とディジ
タル回路部の電流が流れ出る接地部ボンディングパッド
が接続される配線とは別の配線でディジタル回路部の専
用接地部に接続されたバイアスコンデンサを付けるため
の専用のボンディングパッドとを備え、ディジタル回路
部の電流が流れ出る接地部ボンディングパッドがリード
ワイヤ・リードフレームを通って接続される外部ディジ
タル接地とは別の外部接地との間にバイパスコンデンサ
を付けることを特徴とする半導体集積回路。2. In a semiconductor integrated circuit in which a digital circuit section and an analog circuit section are mixed, a dedicated ground section of a digital circuit section and a ground section connected to the dedicated ground section of the digital circuit section and through which current of the digital circuit section flows. A pad, a dedicated ground for the digital circuit section, and a grounding section from which a current of the digital circuit section flows out.A wiring separate from the wiring to which the bonding pad is connected is used to attach a bias capacitor connected to the dedicated ground section of the digital circuit section. A dedicated bonding pad is provided, and a ground capacitor from which the current of the digital circuit section flows is connected by a bypass capacitor between the external digital ground and another external ground connected through the lead wire / lead frame. Characteristic semiconductor integrated circuit.
を電源ラインに設けることを特徴とする請求項１に記載
の半導体集積回路。3. The semiconductor integrated circuit according to claim 1, wherein a path for attaching a bypass capacitor is provided in the power supply line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8217440A JPH1065105A (en) | 1996-08-19 | 1996-08-19 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8217440A JPH1065105A (en) | 1996-08-19 | 1996-08-19 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1065105A true JPH1065105A (en) | 1998-03-06 |
Family
ID=16704271
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8217440A Pending JPH1065105A (en) | 1996-08-19 | 1996-08-19 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1065105A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1293633C (en) * | 2002-12-06 | 2007-01-03 | 松下电器产业株式会社 | Semiconductor integrated circuit apparatus and method for producing semiconductor integrated circuit apparatus |
| JP2013110314A (en) * | 2011-11-22 | 2013-06-06 | Elpida Memory Inc | Semiconductor device |
| US20160020379A1 (en) * | 2014-07-18 | 2016-01-21 | Seiko Epson Corporation | Circuit device, electronic apparatus and moving object |
| US9484857B2 (en) | 2013-11-07 | 2016-11-01 | Seiko Epson Corporation | Semiconductor circuit device, electronic device, electronic apparatus, and moving object |
-
1996
- 1996-08-19 JP JP8217440A patent/JPH1065105A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1293633C (en) * | 2002-12-06 | 2007-01-03 | 松下电器产业株式会社 | Semiconductor integrated circuit apparatus and method for producing semiconductor integrated circuit apparatus |
| JP2013110314A (en) * | 2011-11-22 | 2013-06-06 | Elpida Memory Inc | Semiconductor device |
| US9484857B2 (en) | 2013-11-07 | 2016-11-01 | Seiko Epson Corporation | Semiconductor circuit device, electronic device, electronic apparatus, and moving object |
| US20160020379A1 (en) * | 2014-07-18 | 2016-01-21 | Seiko Epson Corporation | Circuit device, electronic apparatus and moving object |
| US9984991B2 (en) * | 2014-07-18 | 2018-05-29 | Seiko Epson Corporation | Circuit device, electronic apparatus and moving object |
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