JPH1064296A - Semiconductor memory device - Google Patents

Abstract

(57) Abstract: In a semiconductor memory device, a data topology is simplified, and an intended memory test can be correctly performed even when a part of a normal memory cell is replaced with a redundant memory cell. SOLUTION: This DRAM has a data topology, 1
A / 4 pitch bit line contact method and a redundant circuit are employed. In this DRAM, among a plurality of blocks A, B, C, and D divided by a twist portion TW of a normal memory cell array, each basic unit KA
, KB, KC, and KD, the pattern of the arrangement distribution of the inverting memory cell ● / non-inverting memory cell ○ is independent or different from each other, and the basic units KA, KB, KC, KD
A relationship is established that the data topologies within are the same.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0010]

The present invention relates to a semiconductor memory device, and more particularly, to a memory cell array structure of a random access memory (RAM).

[0020]

2. Description of the Related Art Generally, a dynamic RAM (DRA)
In the memory cell array of M), a plurality of word lines and a plurality of bit line pairs intersect in a matrix, and each of the word lines and one of the bit lines of each of the bit line pairs or the bit complementary line. The memory cells are arranged (connected) at the intersection positions.

[0030] For example, in the example shown in FIG. 20, each odd-numbered word lines WL1, WL3, WL5, ... and the bits of each bit line pair Hosen BLi _- and odd columns in the vicinity of intersections of the memory cell MCi, 1 , MCi, 3, MCi, 5… arranged (connected)
And the even-numbered word lines WL0, WL2, WL4,.
Are arranged (connected) in the vicinity of the intersection of the bit lines BLi of each bit line pair with the memory cells MCi, 0, MCi, 2, MCi, 4,.

Each bit line pair BLi / BLi- is connected to one differential sense amplifier S provided for each row (or each column).
Ai. Each memory cell MCi, j is composed of one transistor Qi, j and one capacitor Ci, j. When the word line WLj connected to the memory cell MCi, j is activated, the transistor Qi, j turns on, and at the time of writing, the bit line BL is supplied from the sense amplifier SAi.
i or the capacitor Ci, j via the bit supplementary line BLi-
Potential information is written to the capacitor, and at the time of reading, the capacitor Ci,
The potential information (storage information) of j is input to the sense amplifier SAi via the bit line BLi or the bit auxiliary line BLi-.

Here, each memory cell MCi + (the memory cell MCi, 2n in the even column in FIG. 20) connected to the bit line BLi side has the same logical value as the input / output data as viewed from outside the DRAM. Data is stored.

That is, as schematically shown in FIG. 21A, data of a logical value "1" input from outside the DRAM is stored in an arbitrary memory cell MCi + connected to the bit line BLi. In this case, the same logic value "1" (Vcc level) potential information is written to the memory cell MCi +. Then, the storage information of the logical value “1” read from the memory cell MCi + is directly output as read data of the logical value “1” to the outside of the DRAM. Further, data of a logical value “0” input from the outside is stored in the memory cell M
When stored in Ci +, the same logical value "0" (Vss level) potential information is written in the memory cell MCi +.
Then, the storage information of the logical value “0” read from the memory cell MCi + is directly output to the outside as read data of the logical value “0”.

On the other hand, each memory cell MCi- (the memory cell MCi, 2n + 1 in the odd column in FIG. 20) connected to the bit auxiliary line BLi- side has input / output data as viewed from outside the DRAM. Is stored as an inverted (inverted) logical value.

That is, as schematically shown in FIG. 21B, externally input data of logical value "1" is transferred to an arbitrary memory cell MC connected to the bit auxiliary line BLi-.
When the data is stored in i-, the memory cell MCi- inverts the logical value "1" of the input data to the logical value "0" (Vss level).
Is written. In this case, the memory cell M
The storage information of the logical value "0" read from Ci- is DRA
After returning to the logical value "1" in M, it is output to the outside as read data of the logical value "1". Similarly, when the input / output data of the logical value “0” is stored in the memory cell MCi− from the outside, the inverted logical value “1” is stored inside the DRAM.
Is written to the memory cell MCi-.

As described above, in the DRAM, from another viewpoint, depending on whether the memory cell MC is connected to the bit line BLi or the bit auxiliary line BLi-, the individual memory address of each memory address is different. Depending on the value, the logical value of the input / output data and the logical value of the data stored in the internal memory cell MC may be the same or opposite (inverted). The mechanism in which the non-inverting property / inverting property of data is determined according to the value of the memory address is called data topology or data scrambling.

By the way, in a recent DRAM, as shown in FIG. 22, as a bit line arrangement structure for increasing the degree of integration of a memory cell array, a bit line BLi and a bit auxiliary line BLi- forming each bit line pair are arranged as shown in FIG. Either one of the bit line and the bit supplementary line (for example, BLi + 1) constituting the adjacent bit line pair is arranged at a substantially intermediate position, and as shown in FIG. Line contact locations (eg BCi, c and BCi, c + 1)
Is P, the positions of bit line contacts (for example, BCi, c + 1 and BCi + 1, c + 1) adjacent in the bit line and bit complementary line arrangement direction (Y direction) are bit line or bit complementary. A so-called 1/4 pitch bit line contact method is known in which a shift is made by P / 4 in a direction parallel to the line. The bit line arrangement structure of this system has an advantage that wiring can be performed at a higher density than the normal 1/2 pitch bit line contact system. FIG.
, MAi, c, MAi, c + 1,... Are element regions,
MCi, j-2, MCi, j... Are memory cells.

However, in a memory cell array of a DRAM, bit lines adjacent to each other, bit auxiliary lines, or bit lines and bit auxiliary lines are coupled to each other via a parasitic capacitance. For this reason, during the sensing of the bit line or the bit supplementary line, if it is affected by a potential change on another neighboring bit line or the bit supplementary line via the parasitic capacitance, a sense failure (erroneous read) may occur. is there.

Therefore, in the above-described 1/4 pitch bit line contact method, as shown in FIG. 22, bit lines (for example, odd-numbered or even-numbered (even-numbered in FIG. 22)) constituting each bit line pair (for example, as shown in FIG. 22). It is customary to adopt a twist structure in which the bit line BL0) and the bit supplementary line (for example, BL0-) are twisted once at a substantially middle position in the length direction of the line to change their positions. According to this twisted structure, the spacing between other bit lines or bit supplementary lines in the vicinity is symmetrical on an arbitrary bit line pair (bit line / bit supplementary line) on both sides of the twisted portion TW, so that the parasitic capacitance Are balanced. Therefore, when the potential changes on another bit line or bit supplementary line in the vicinity, the effects on the bit line and the bit supplementary line of the bit line pair via the parasitic capacitance are equal to each other and canceled.

In most DRAMs, several redundant rows or columns (redundant memory cell arrays) are added to a normal memory cell array to include defective (defective) memory cells or defective word lines in the normal memory cell array. A redundant circuit for replacing a unit row or column with a redundant memory cell array is provided.

FIG. 24 shows a configuration of a main part of a conventional DRAM employing the above data topology, 1/4 pitch bit line contact system and redundant circuit.

In this DRAM, a large number of sense amplifiers SA0, SA1, SA2,...
Are arranged in a line in the Y direction, and memory cell arrays are developed on both sides thereof.

Each sense amplifier SAi (i = 0, 1, 2, 2)
...), a pair of bit lines BLi /
BLi- is extended. And a large number (512 in this example)
) Are connected to each bit line pair BLi.
/ BLi- and intersect orthogonally, and each word line WLj (j =
511) and a memory cell MCi, j is arranged (connected) near the intersection of each bit line pair BLi / BLi- with either the bit line BLi or the bit auxiliary line BLi-.

In the memory cell array area on the left side of the sense amplifier bank, each even-numbered bit line pair BL0 / BL
0-, BL2 / BL2-, ..., bit lines BL0, BL
,... And the bit supplementary lines BL0-, BL2-,... Are twisted at the twisted point TW set near the bit line intermediate part to change their positions. The memory cell layout is divided into two blocks A and B.

Similarly, in the memory cell array area on the right side of the sense amplifier bank, bit lines BL0, BL2,... And bit auxiliary lines BL0 in even-numbered bit line pairs BL0 / BL0-, BL2 / BL2-,. , BL2-,... Are twisted at a twisted portion TW set near the bit line intermediate portion to exchange positions with each other.
The right normal memory array section is divided into two blocks C and D with respect to the layout of the memory cell arrangement.

The odd-numbered bit line pairs BL1 / B
In L1-, BL3 / BL3-, ..., bit lines BL1, B
L3,... And bit supplementary lines BL1-, BL3-,... Are twisted at twist locations TW set inside corresponding sense amplifiers SA1, SA3,. Also,
Even-numbered bit line pairs BL0 / BL0-, BL2 / BL
, And the next odd-numbered bit line pairs BL1 / BL1-, BL3 / BL3.
Among the corresponding sense amplifiers (SA0, SA1), (SA2, SA3),
And twist positions TW set between the inner blocks B and C to change the positions.

As described above, in this DRAM, the normal memory array is divided into four blocks A, B, C, and D. A block R of the redundant memory cell array is provided next to (on an extension of) the right end block D.

In the normal memory cell array, in the block A, the basic unit of the memory cell arrangement as shown by the square frame KA is repeatedly arranged in the X and Y directions (squares). Similarly, in the other blocks B, C, and D, the basic units of the memory cell arrangement as shown by the square frames KB, KC, and KD are repeatedly arranged in the X and Y directions (squares). In the block R of the redundant memory cell array, the basic unit of the memory cell arrangement as shown by a square frame KR is repeatedly arranged in the Y direction.

In FIG. 24, .largecircle. Indicates a non-inverted memory cell corresponding to the memory cell MCi + in FIG.
● is an inverted memory cell corresponding to the memory cell MCi- in FIG. 10B.

FIGS. 25 to 29 show the respective blocks A, B, C,
Basic units KA, KB,
The distribution of the memory cells in KC, KD and KR is shown. As shown, blocks A, B,
Between C and D, basic units KA, KB,
The patterns or layouts of the memory cell arrangement distributions in KC and KD are different. The basic unit KR of the memory cell arrangement of the redundant block R has the same pattern as the basic unit KD of the memory cell arrangement of the block D.

FIG. 30 shows the data topology of the inversion condition in all blocks. In this DRAM, the location (memory address) where each inversion type memory cell (●) is located is the most significant two bits (X8, X7) of the X address signal for identifying each of the blocks A, B, C, D. And the least significant two bits (X1, X0) of the X address signal for identifying each (order) of the four word lines WL in the basic unit K of each memory cell arrangement, and in the basic unit K of each memory cell arrangement. Is defined or specified by the least significant bit (Y0) of the Y address signal for identifying the even-numbered bit line pair BL2n / BL2n- and the odd-numbered bit line pair BL2n + 1 / BL (2n + 1)-. . That is, the inversion condition is expressed by the following equation (1).

[0250] inversion conditions = [(X1 ◆ X7) ◆ X8] - ※ Y0 - + [(X0 ◆ X1) - ◆ X8] ※ Y0 ......... (1) where, _- is negative (inverted), + is Logical sum, * is logical product,
◆ represents exclusive OR.

When write / read access is performed for an arbitrary memory cell in the memory cell array, it is determined whether the memory cell is a non-inverted memory cell or an inverted memory cell by referring to the data topology. However, control of data characteristics (non-inversion / inversion) as shown in FIG. 21 can be performed.

When a defective cell or word line exists in an arbitrary block in the normal memory cell array, for example, block A, and a region corresponding to four word lines including the defective portion is replaced by block R in the redundant memory cell array. But
The data property (non-inverted / inverted) as shown in FIG. 21 can be controlled by referring to the data topology every time the redundant block R is accessed.

[0280]

However, in the conventional DRAM as described above, the data topology differs between the blocks A, B, C, and D in the normal memory cell array, and the inversion condition (1) is complicated. Accordingly, the scale of the circuit for controlling the data characteristics also increases.

Further, when the redundant block R is replaced with a partial area of the block A, B or C having a different data topology from that of the redundant block R, a useful memory test cannot be performed effectively.

That is, in a certain memory test, in order to inspect the physical characteristics of each memory cell, not only the non-inverted memory cells but also the inverted memory cells have the same physical and logical values. May be stored.
In this case, the test apparatus (memory tester) accesses each memory cell with reference to the data topology as described above, and performs data property control on the inverted memory cell, which is opposite to the normal memory access. . That is, when, for example, data having a logical value “1” is stored in an inversion type memory cell from the outside, data having a logical value “0” is written.

However, when a partial area of block A is replaced with redundant block R, for example, the test apparatus does not know that. Therefore, even when a memory cell in the area of the block A is accessed, the data property control for the test as described above is performed with reference to the data topology for the block A. However, since the data is actually replaced with a redundant block R having a different data topology, erroneous data property control is performed. Therefore, the intended memory test cannot be performed.

The present invention has been made in view of the above-mentioned problems, and simplifies the data topology, and enables a desired memory test to be correctly performed even when a part of normal memory cells is replaced with a redundant memory cell. It is an object of the present invention to provide a semiconductor memory device according to the above.

[0330]

According to a first aspect of the present invention, there is provided a semiconductor memory device comprising: a plurality of word lines and a plurality of bit line pairs intersecting in a matrix; A memory cell is arranged near the intersection of the word line and either the bit line or the bit complement of each of the bit line pairs, and a first cell connected to the bit line is provided.
Type memory cells store data with a first logic, and second type memory cells connected to the bit complements store data with a second logic opposite to the first logic. The bit lines and bit auxiliary lines of all or some of the bit line pairs are twisted at predetermined twist locations to change positions with each other, and in the basic unit of the memory cell arrangement, the bit line and the bit auxiliary line are viewed from the address order of each of the word lines. The configuration has a memory cell array in which the arrangement distribution of the type 1 and type 2 memory cells is the same among a plurality of blocks divided at the twist location.

According to the second semiconductor memory device of the present invention, a plurality of normal word lines and a plurality of bit line pairs intersect in a matrix, and each of the normal word lines and the bit of each of the bit line pairs. A memory cell is arranged near an intersection with either a line or a bit auxiliary line, data is stored in a first type of memory cell connected to the bit line with a first logic, and connected to the bit auxiliary line. In the memory cell of the second type, data is stored in a second logic opposite to the first logic, and all or a part of the bit line pair and the bit complementary line have a predetermined twist. A plurality of locations where the layout distribution of the first and second type memory cells as viewed from the address order of each of the normal word lines in the basic unit of memory cell layout is divided by the twist location. of A normal memory cell array that is the same between locks, a plurality of redundant word lines and the plurality of bit line pairs intersect in a matrix, and each of the redundant word lines and the bit line of each of the bit line pairs or One redundant memory cell is connected near the intersection with any of the bit complement lines, and data of the first logic is stored in the first type of redundant memory cell connected to the bit line. Data is stored in the second type of redundant memory cell connected to the line by the second logic, and the first type and the second type are viewed from the address order of each of the redundant word lines in the basic unit of the memory cell arrangement. Memory cell array in which the arrangement distribution of redundant memory cells of the same type is the same as the arrangement relationship of the memory cells in the basic unit of the memory cell arrangement of each block of the normal memory cell array. It was configured to have and stomach.

The third semiconductor memory device of the present invention is the first or second device, wherein the arrangement order of each word line in the basic unit of the memory cell arrangement is the plurality of word lines as viewed from the address order of the word lines. The first block in the basic unit of the memory cell arrangement
The arrangement distribution of the type and the second type of memory cells is independent among the plurality of blocks.

In a fourth semiconductor memory device according to the present invention, in the first or second device, the arrangement distribution of the first-type and second-type memory cells in a basic unit of the memory cell arrangement is the plurality of memory cells. The configuration is the same between the blocks, and the arrangement order of the word lines in the basic unit of the memory cell arrangement is independent among the plurality of blocks as viewed from the address order of the word lines.

In the fifth semiconductor memory device of the present invention, a plurality of word lines and a plurality of bit line pairs intersect in a matrix, and each of the word lines and the bit line of each of the bit line pairs. One memory cell is arranged near an intersection with any of the bit auxiliary lines, data is stored in a first type of memory cell connected to the bit line by a first logic, and connected to the bit auxiliary line. In the second type memory cell, data is stored in a second logic opposite to the first logic, and the arrangement distribution of the first type memory cell and the second type memory cell is the same. A memory array in which a plurality of memory cell arrangement basic units are repeatedly arranged, and the arrangement order of each word line in each memory cell arrangement basic unit is the same as viewed from the address order of the word lines. age .

[0380]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

First, a first embodiment of the present invention will be described with reference to FIGS.

FIGS. 1 to 7 show D according to an embodiment of the present invention.
2 shows a configuration of a RAM. FIG. 1 shows an entire configuration of a main part of the DRAM. FIG. 2 shows the memory cell arrangement distribution of the left half of the normal memory cell array in FIG. 1 in detail, and FIG.
The memory cell arrangement distribution in the right half of the normal memory cell array in the middle is shown in detail. 4 to 7 show layouts of memorial cell arrangement in each block in a normal memory cell.
In the figure, ○ indicates a non-inverted memory cell (MC +), and ● indicates an inverted memory cell (MC-).

The DRAM of this embodiment employs a data topology, a 1/4 pitch bit line contact system, and a redundant circuit. In this DRAM, sense amplifiers SA0, SA1, SA2,...
.. And the word lines (normal word lines WL0 to WL511, redundant word lines RW0 to RW3) are arranged in the above-described conventional DRAM (FIG. 24), and the arrangement of L0 / BL0-, BL1 / BL1-, BL2 / BL2-,. And in common. Bit line pair BL0 / BL0-, BL1 / BL1-, BL2 / BL2
-,... Are the same as those of the conventional DRAM (FIG. 24).

At the time of memory access, X address decoder 10 operates as follows for 512 word lines WL0 to WL0.
One of WL511 is selected. The upper decoder section XDH in the X address decoder 10 receives the lower predecode signal XFH0-15 corresponding to the upper 7 bits X2-8 of the X address signal X0-8 and outputs the lower decoder section XDH.
A word line drive signal is applied to one of DL0, XDL1,... XDL127. This word line drive signal is applied to one of the four AND gates (G0, G1, G2, G3) included in the selected lower decoder section XDLn, that is, the X address signal X0-8. It is supplied to the word line WLj via any one AND gate (for example, G1) which is enabled by the 4-bit lower pre-decode signal XFL0-3 corresponding to the lower 2 bits X0-1.

However, when a defective cell or word line exists in an arbitrary block in the normal memory cell array, for example, block A, and a region corresponding to four word lines including the defective portion is replaced by block R in the redundant memory cell array. When the memory address specifies the area to be replaced in the block A, an address decoder (not shown) of the redundant circuit
When the match signal DS is generated, the upper decoder unit XDH stops outputting the word line drive signal. Instead, the word line drive signal RED from the redundancy circuit is supplied to the lower order block XDR for the redundancy block, and one of the four redundancy word lines RW0 to RW3 is selected.

Each sense amplifier SA0, SA1, SA2,
Are connected to a Y address decoder (not shown) via a Y select line (not shown) which is wired in parallel with the bit line pair via an interlayer insulating film.

In this DRAM, the operation of writing / reading data to / from individual memory cells is performed in a usual manner.

The feature of this DRAM is the pattern of the memory cell arrangement distribution in the basic units KA, KB, KC, KD, and KR in each of the blocks A, B, C, D, and R of the memory cell array.

FIG. 8 shows the basic unit KA in the block A.
1 schematically shows a pattern of a memory cell arrangement distribution in a cell. In this basic unit KA, two pairs (even and odd) of pairs of bit lines BL2n / BL2n- and BL2n + 1 /
BL (2n + 1)-in the Y direction is BL2n, BL2n + 1, BL2n-,
BL (2n + 1)-and four consecutive word lines WLa, WLa + 1, WLa + 2, WLa + 3 (a
.., 124) are arranged in this order in the X direction.

Focusing on even-numbered bit line pairs BL2n / BL2n-, inverted memory cells are arranged at the respective intersections between bit auxiliary lines BL2n- and first and second order word lines WLa, WLa + 1. A non-inverted memory cell O is arranged at each intersection between the bit line BL2n and the third and fourth word lines WLa + 2, WLa + 3.

The odd-numbered bit line pair BL2n + 1 / B
Focusing on L (2n + 1)-, an inverted memory cell ● is arranged at each intersection of the bit auxiliary line BL (2n + 1)-and the first and fourth order word lines WLa, WLa + 3. , Bit line BL
2n + 1 and the second and third order word lines WLa + 1, WLa +
2, a non-inverting type memory cell ○ is arranged.

FIG. 9 shows the basic unit KB in the block B.
1 schematically shows a pattern of a memory cell arrangement distribution in a cell. In this basic unit KB, two consecutive (even and odd) bit line pairs BL2n / BL2n- and BL2n + 1 /
BL (2n + 1)-is BL2n-, BL2n + 1, BL2n,
BL (2n + 1)-and four consecutive word lines WLb, WLb + 1, WLb + 2, WLb + 3 (b
. = 252) are arranged in this order in the X direction.

In this basic unit KB, if attention is paid to the even-numbered bit line pair BL2n / BL2n-, the bit complementary line BL2
2n− and first and second order word lines WLb, WLb + 1
Memory cell ● is arranged at each intersection with the bit line BL2n and the third and fourth order word lines WLb + 2,
A non-inverted memory cell O is arranged at each intersection with WLb + 3.

Also, the odd-numbered bit line pair BL2n + 1 / B
Focusing on L (2n + 1)-, an inverted memory cell ● is arranged at each intersection between the bit auxiliary line BL (2n + 1)-and the first and fourth order word lines WLb and WLb + 3. , Bit line BL
2n + 1 and second and third order word lines WLb + 1, WLb +
2, a non-inverting type memory cell ○ is arranged.

FIG. 10 shows the basic unit K in the block C.
3 schematically shows a pattern of a memory cell arrangement distribution in C.
In this basic unit KC, two consecutive (even and odd) bit line pairs BL2n / BL2n-, BL2n + 1
/ BL (2n + 1)-in the Y direction are BL2n-, BL (2n + 1)-, B
L2n, BL2n + 1 and 4
Word lines WLc, WLc + 1, WLc + 2, WLc + 3
(C = 256, 260,... 380) are arranged in this order in the X direction.

In this basic unit KC, if attention is paid to even-numbered bit line pairs BL2n / BL2n-, bit complementary lines BL2n / BL2n-
2n− and first and second order word lines WLc, WLc + 1
Memory cell ● is arranged at each intersection with the bit line BL2n and the third and fourth order word lines WLc + 2,
A non-inverted memory cell ○ is arranged at each intersection with WLc + 3.

The odd-numbered bit line pair BL2n + 1 / B
Focusing on L (2n + 1)-, an inverted memory cell ● is arranged at each intersection between the bit auxiliary line BL (2n + 1)-and the first and fourth order word lines WLc and WLc + 3. , Bit line BL
2n + 1 and the second and third order word lines WLc + 1, WLc +
2, a non-inverting type memory cell ○ is arranged.

FIG. 11 shows the basic unit K in the block D.
7 schematically shows a pattern of a memory cell arrangement distribution in D.
In this basic unit KD, two consecutive (even and odd) bit line pairs BL2n / BL2n-, BL2n + 1
/ BL (2n + 1)-in the Y direction is BL2n, BL (2n + 1)-, BL
2n-, BL2n + 1 and 4
Word lines WLd, WLd + 1, WLd + 2, WLd + 3
(D = 384,388,... 508) are arranged in that order in the X direction.

In this basic unit KD, even-numbered bit line pairs BL2n / BL2n- have bit complementary lines BL2n-
Memory cell ● is arranged at each intersection of the first and second order word lines WLd and WLd + 1, and the bit line BL2n and the third and fourth order word lines WLd + 2 and WL
A non-inverted memory cell ○ is arranged at each intersection with d + 3.

The odd-numbered bit line pair BL2n + 1 / B
In L (2n + 1)-, the bit complementary line BL (2n + 1)-
And an inversion type memory cell ● is arranged at each intersection with the fourth order word lines WLd and WLd + 3, and bit line BL2n
+1 and the second and third order word lines WLd + 1, WLd + 2
Non-inverting type memory cells に are arranged at the respective intersections with.

FIG. 12 schematically shows the pattern of the memory cell arrangement distribution in the basic unit KR in the redundant block R. In this basic unit KR, two pairs (even and odd) of pairs of bit lines BL2n / BL2n-, BL
2n + 1 / BL (2n + 1)-in the Y direction are BL2n, BL (2n + 1)-,
BL2n-, BL2n + 1 and four consecutive redundant word lines RW0, RW1, RW2, RW3.
Are arranged in this order in the X direction.

In the basic unit KR of the redundant portion, in the even-numbered bit line pairs BL2n / BL2n-, the bit auxiliary line BL2n- and the first and second order word lines RW0, RW are used.
1 is disposed at each intersection with the bit line BL2n and the third and fourth word lines RW2,
A non-inverting type memory cell に is arranged at each intersection with RW3.

Also, the odd-numbered bit line pair BL2n + 1 / B
In L (2n + 1)-, the bit complementary line BL (2n + 1)-
And an inversion type memory cell ● is arranged at each intersection with word lines RW0 and RW3 of the fourth order, and bit line BL2n + 1
A non-inverting type memory cell 配置 is arranged at each intersection of the word lines RW1 and RW2 of the second and third order.

As described above, between the blocks A, B, C, and D of the normal memory cell array, each basic unit K
In A, KB, KC, and KD, the arrangement distribution patterns of the inverted memory cell ● / non-inverted memory cell ○ are independent or different from each other, and the basic units KA, KB, KC, K
The relationship is established that the data topologies in D are identical to each other.

The basic unit KR of the redundant block R is:
Since the data topology as well as the pattern of the memory cell arrangement distribution is the same as the basic unit KD of the block D of the normal memory cell array, the basic unit KD of any of the other blocks A, B, and C of the normal memory array also has the data topology. Are the same.

As described above, in the DRAM of this embodiment,
The data topology in the basic unit K is the same among all blocks A, B, C, D, and R, and the inversion condition is simple as represented by the following equation (2).

[0650] inversion conditions _{= X1 - ※ Y0 - + (} X0 ◆ X1) - ※ Y0 ......... (2) where, _- is negative (inverted), + is the logical sum, ※ is a logical product,
◆ represents exclusive OR.

[0660] In other words, in this DRAM, the location (memory address) where each inversion type memory cell (●) is located is the individual (order) of the four word lines WL in the basic unit K of each memory cell location. ) And the even-numbered bit line pair BL2n / BL in the basic unit K of each memory cell arrangement.
2n- and the least significant bit (Y0) of the Y address signal for identifying the odd-numbered bit line pair BL2n + 1 / BL (2n + 1)-. X to identify each block
The upper two bits (X8, X7) of the address signal become unnecessary.

As described above, according to this embodiment, since the data topologies match among all the blocks A, B, C, and D in the normal memory cell array and the inversion condition (2) is simple, the data property A control circuit can be simplified.

Even if a partial area of any of blocks A, B, C, and D in the normal memory cell array is replaced with redundant block R, blocks A, B, C, and D and redundant block R
Is useful for testing the physical characteristics of individual memory cells as described above, i.e., not only for non-inverted memory cells but also for inverted memory cells. A test for storing data of the same value physically and logically can be performed correctly.

FIG. 13 is a view showing the structure of D according to the second embodiment of the present invention.
1 shows a configuration of a main part of a RAM. In the figure, parts having the same configuration and function as those of the first embodiment (FIG. 1) are denoted by the same reference numerals.

In this embodiment, the pattern or layout of the memory cell arrangement distribution is common or the same in all blocks, and the arrangement order of the word lines WL in the basic units KA, KB, KC, and KD is made independent between the blocks. , The data topology is common or the same for all blocks.

FIGS. 14 to 16 schematically show the distribution patterns of the memory cells in the basic units KB, KC, and KD in the blocks B, C, and D, respectively. The pattern of the memory cell arrangement distribution in the basic unit KA in the block A is the same as the pattern shown in FIG. The pattern of the memory cell arrangement distribution in the basic unit KR in the redundant block R is the same as the pattern of the memory cell arrangement distribution in the basic unit KD in the block D (FIG. 16).

For example, in FIG. 14, in the basic unit KB of the block B, two consecutive (even and odd) bit line pairs BL2n / BL2n- and BL2n + 1 / B
L (2n + 1)-is BL2n-, BL (2n + 1), BL2n,
BL (2n + 1)-and four consecutive word lines WLb, WLb + 1, WLb + 2, WLb + 3 (b
= 128,132, ... 252) in the X direction are WLb + 3, WLb + 2, WL
b + 1 and WLd are arranged in this order.

If attention is paid to even-numbered bit line pairs BL2n / BL2n-, inverted memory cells are arranged at intersections between bit auxiliary lines BL2n- and first and second order word lines WLb and WLb + 1. A non-inverted memory cell O is arranged at each intersection of the bit line BL2n and the third and fourth word lines WLb + 2, WLb + 3.

[0739] Also, the odd-numbered bit line pair BL2n + 1 / B
Focusing on L (2n + 1)-, an inverted memory cell ● is arranged at each intersection between the bit auxiliary line BL (2n + 1)-and the first and fourth order word lines WLb and WLb + 3. , Bit line BL
2n + 1 and second and third order word lines WLb + 1, WLb +
2, a non-inverting type memory cell ○ is arranged.

[0750] Therefore, the data topology in the basic unit KB of the block B is the same as that of the basic unit K in the block A.
Same as the data topology in A. Similarly, in the basic units KC, KD, and KR of the other blocks C, D, and R, the arrangement order of the four word lines is unique for each block. As a result, the data topology is the same as that of the blocks A and B. It can be seen that it is.

As described above, also in this embodiment, the data topology is common to all blocks A, B, C, and D in the normal memory cell array, and the inversion condition is expressed by the above equation (2). Therefore, the same effects as those in the first embodiment can be obtained in data property control, memory test, and the like.

Although both the first and second embodiments relate to the に pitch bit line contact method, as shown in FIGS. 17 and 18, the present invention employs a ピ ッ チ pitch bit line contact method. It is also applicable to the bit line contact method.

[0780] The example shown in FIG. 17 is the same as that of the first embodiment described above, except that the inverted memory cells in the respective basic units KA and KB are provided between the blocks A and B in the normal memory array.
/ The pattern of arrangement distribution of the non-inverting type memory cells ○ is independent or different from each other, and the relationship is established that the data topologies in the basic units KA and KB are the same.

In this DRAM, locations (memory addresses) where individual inversion type memory cells (●) are arranged
Is specified only by the least significant two bits (X1, X0) of the X address signal for identifying each (order) of the four word lines WL in the basic unit K of each memory cell arrangement. That is,
The inversion condition is represented by the following equation (3).

Inversion condition = X0 ◆ X1 (3) Here, ◆ represents exclusive OR.

In the example shown in FIG. 18, the pattern or layout of the memory cell arrangement distribution is the same or the same between the blocks A and B in the normal memory cell array as in the second embodiment, and the basic units KA, Word line WL in KB
Is independent between the blocks A and B, so that the data topology is common or identical between the blocks A and B. Also in this example, the inversion condition is represented by the above equation (3).

FIG. 19 shows an application example of the present invention. In the memory cell array in which the twist portion TW is not provided, the word line RW of the redundant portion is halved by using the method of changing the order of the word lines as in the second embodiment. According to this example, the pair of word lines RW of the redundant portion
0 (2) and RW1 (3) replace either the first pair of word lines (WLa, WLa + 1) or the second pair of word lines (WLa + 2, WLa + 3) in the normal memory cell array. can do.

In the above embodiment, the memory cell array area is developed on both sides of the sense amplifier bank. However, the memory cell array area may be developed on only one side, and the number of blocks in the normal memory cell array can be arbitrarily selected. is there. The position and capacity of the redundant section can be arbitrarily selected.

[0840]

As described above, according to the present invention,
The data topology is simplified, and the intended memory test can be correctly performed even if a part of the normal memory cells is replaced with the redundant memory cells.

[Brief description of the drawings]

FIG. 1 is a diagram schematically showing a configuration of a memory cell array of a DRAM according to a first embodiment of the present invention.

FIG. 2 is a diagram showing in more detail a left half region of the normal memory cell array of FIG. 1 in the first embodiment.

FIG. 3 is a diagram showing in more detail a right half region of the normal memory cell array of FIG. 1 in the first embodiment.

FIG. 4 is a diagram showing a layout of a memory cell arrangement in a block A of a normal memory cell array in the first embodiment.

FIG. 5 is a diagram showing a layout of a memory cell arrangement in a block B of a normal memory cell array in the first embodiment.

FIG. 6 is a diagram showing a layout of a memory cell arrangement in a block C of a normal memory cell array in the first embodiment.

FIG. 7 is a diagram showing a layout of a memory cell arrangement in a block D of a normal memory cell array in the first embodiment.

FIG. 8 is a diagram showing a pattern of a memory cell arrangement distribution in a basic unit of a block A of a normal memory cell array in the first embodiment.

FIG. 9 is a diagram showing a pattern of a memory cell arrangement distribution in a basic unit of a block B of a normal memory cell array in the first embodiment.

FIG. 10 is a diagram showing a pattern of a memory cell arrangement distribution in a basic unit of a block C of a normal memory cell array in the first embodiment.

FIG. 11 is a diagram showing a pattern of a memory cell arrangement distribution in a basic unit of a block D of a normal memory cell array in the first embodiment.

FIG. 12 is a diagram showing a pattern of a memory cell arrangement distribution in a basic unit of a block R of a redundant memory cell array in the first embodiment.

FIG. 13 is a diagram schematically showing a configuration of a memory cell array of a DRAM according to a second embodiment of the present invention.

FIG. 14 is a diagram showing a pattern of a memory cell arrangement distribution in a basic unit of a block B of a normal memory cell array in the second embodiment.

FIG. 15 is a diagram showing a pattern of a memory cell arrangement distribution in a basic unit of a block C of a normal memory cell array in the second embodiment.

FIG. 16 is a diagram showing a pattern of a memory cell arrangement distribution in a basic unit of a block D of a redundant memory cell array in the second embodiment.

FIG. 17 is a diagram schematically showing a configuration of a memory cell array of a DRAM according to a third embodiment of the present invention.

FIG. 18 is a diagram schematically showing a configuration of a memory cell array of a DRAM according to a fourth embodiment of the present invention.

FIG. 19 is a diagram schematically showing a configuration of a memory cell array of a DRAM according to a fifth embodiment of the present invention.

FIG. 20 is a diagram schematically showing a configuration of a memory cell array of a general DRAM.

FIG. 21 is a diagram illustrating inversion / non-inversion data property control in a DRAM.

FIG. 22 is a diagram showing an arrangement structure of bit line pairs in a memory cell array according to a ピ ッ チ pitch bit line contact method.

FIG. 23 is a diagram showing a layout of a memory cell arrangement by a ピ ッ チ pitch bit line contact method.

FIG. 24 is a diagram schematically showing a configuration of a conventional memory cell array.

25 is a diagram showing a pattern of a memory cell arrangement distribution within a basic unit of a block A of a normal memory cell array in the conventional example of FIG. 24;

26 is a diagram showing a pattern of a memory cell arrangement distribution in a basic unit of a block B of a normal memory cell array in the conventional example of FIG. 24;

FIG. 27 is a diagram showing a pattern of a memory cell arrangement distribution in a basic unit of a block C of a normal memory cell array in the conventional example of FIG. 24;

FIG. 28 is a diagram showing a pattern of a memory cell arrangement distribution in a basic unit of a block D of a normal memory cell array in the conventional example of FIG. 24;

29 is a diagram showing a pattern of a memory cell arrangement distribution in a basic unit of a block R of a redundant memory cell array in the conventional example of FIG.

FIG. 30 is a diagram showing a data topology of all blocks in the conventional example of FIG. 24;

[Explanation of symbols]

, XDL0, XDL1,..., XDL127, XDR Lower decoder SA0, SA1,... Sense amplifier BL0 / BL0-, BL1 / BL1-,. -, BL1-,... Bit supplementary lines WL0, WL1, WL2, WL3... Word lines KA, KB, KC, KD, KR Basic unit of memory cell arrangement

Claims (5)

[Claims] 1. A plurality of word lines and a plurality of bit line pairs intersect in a matrix, and an intersection position between each word line and any one of a bit line and a bit auxiliary line of each of the bit line pairs. One memory cell is placed in the vicinity,
The first type memory cell connected to the bit line has a first type.
Data is stored in the second type of memory cell connected to the bit auxiliary line.
The data is stored by the logic of, and bit lines and bit auxiliary lines of all or a part of the bit line pairs are twisted at predetermined twist locations to change positions with each other, and each of the word lines in a basic unit of memory cell arrangement. A semiconductor memory device having a memory cell array in which the arrangement distribution of the first and second type memory cells is the same among a plurality of blocks divided at the twisted portion, as viewed from the address order. 2. A plurality of normal word lines and a plurality of bit line pairs intersect in a matrix, and each of the normal word lines and one of the bit lines or the bit auxiliary lines of each of the bit line pairs intersects. One memory cell is arranged in the vicinity of the intersection, a first type memory cell connected to the bit line stores data with a first logic, and a second type memory connected to the bit auxiliary line. Data is stored in the cell by a second logic opposite to the first logic, and all or some of the bit lines and bit supplementary lines of the bit line pair are twisted at predetermined twist locations to position each other. In other words, in the basic unit of the memory cell arrangement, the arrangement distribution of the first and second type memory cells as viewed from the address order of each of the normal word lines is the same among a plurality of blocks divided at the twisted locations. Regular mail A memory cell array, a plurality of redundant word lines and the plurality of bit line pairs intersect in a matrix, and each of the redundant word lines and any one of the bit lines or the bit auxiliary lines of each of the bit line pairs. One redundant memory cell is connected in the vicinity of the crossing position, data is stored in the first type of redundant memory cell connected to the bit line by the first logic, and a second type is connected to the bit auxiliary line. Data is stored in the redundant memory cells of the first type and the second type, and the arrangement of the first and second type redundant memory cells in the basic unit of the memory cell arrangement as viewed from the address order of each of the redundant word lines A semiconductor memory device having a redundant memory cell array whose distribution is the same as the arrangement relationship of the memory cells in a basic unit of the memory cell arrangement of each block of the normal memory cell array; Place. 3. The arrangement order of each word line in the basic unit of the memory cell arrangement as viewed from the address order of the word lines is the same among the plurality of blocks, and the first type in the basic unit of the memory cell arrangement is 3. The semiconductor memory device according to claim 1, wherein the arrangement distribution of the memory cells of the second type is independent among the plurality of blocks. 4. The arrangement distribution of the first type and second type memory cells in the basic unit of the memory cell arrangement is the same among the plurality of blocks, and in the basic unit of the memory cell arrangement, 3. The semiconductor memory device according to claim 1, wherein the arrangement order of each word line in terms of an address order is independent among the plurality of blocks. 5. A plurality of word lines and a plurality of bit line pairs intersect in a matrix, and an intersection position between each word line and any one of a bit line and a bit auxiliary line of each of the bit line pairs. One memory cell is placed in the vicinity,
The first type memory cell connected to the bit line has a first type.
Data is stored in the second type of memory cell connected to the bit auxiliary line.
And a memory array in which a plurality of memory cell arrangement basic units having the same arrangement distribution of the first type memory cells and the second type memory cells are repeatedly arranged. Semiconductor memory device, wherein the arrangement order of each word line is the same as viewed from the address order of the word lines in each of the memory cell arrangement basic units.