JPH1063693A - Method of calculating signal delay time of logic circuit and method of displaying delay time - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To provide a delay time calculation method capable of calculating a delay time with high speed and high accuracy for a large-scale logic circuit. SOLUTION: The delay time of the path of the entire logic circuit is obtained by a static delay calculation process. Further, for a path requiring high-precision calculation, a high-accuracy calculation control path condition library is input and the static delay calculation is performed. Selecting a path that satisfies the condition by referring to the signal delay time of the path obtained by the above, and, based on the connection information of the logic circuit for the selected path, circuit simulation data and circuit simulation in the selected path To generate an input signal (test pattern) of the input. [Effect] A static delay calculation for the entire circuit and a circuit simulation for a path requiring particularly high precision can be automatically executed, and the delay time can be automatically calculated with high precision and high speed for a large-scale logic circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of designing a logic circuit based on design data based on design data before manufacturing.
The present invention relates to a method of calculating a signal delay time using a program, and more particularly to a method of calculating a signal delay time of a logic circuit suitable for calculating a signal delay time with high speed and high accuracy for a large-scale logic circuit.

[0002]

2. Description of the Related Art In a synchronous logic circuit, the signal delay time of a path between all flip-flops is required to be within a design reference limit value. For this reason, before manufacturing, delay verification is performed in which signal delay times of all paths are calculated based on design data of a logic circuit and compared with a design reference value. In addition, due to the recent increase in the speed of logic circuits, in the logic design and layout design steps, it is necessary to calculate the delay time of a path and optimize the logic and layout so that the delay time is within a design reference value. Will be As described above, in designing a large-scale and high-speed logic circuit, it is required that the calculation of the signal delay time be performed with high accuracy and high speed.

There are the following two methods for calculating the signal delay time of a logic circuit. (1) Circuit simulation: In circuit simulation, the relationship among transistor elements, resistance elements, and capacitance elements included in a logic circuit is described by simultaneous differential equations, and this is solved by numerical simulation. If a circuit simulation is used, a signal potential at an arbitrary place in the circuit at an arbitrary time can be obtained, so that a time at which a signal propagates at the start and end points of a path, that is, a signal delay time can be obtained. In general, a circuit simulation can perform high-precision calculations, but has a problem in that the time required for the calculations is long. Further, in order to perform a circuit simulation, an input signal waveform (test pattern) is required in addition to connection data of a target logic circuit. In order to operate all the paths included in the logical circuit, it is necessary to create a huge test pattern. Also, confirming that all paths are working by the created test pattern is
Near impossible.

(2) Static delay calculation: In the static delay calculation,
With the design data of the logic circuit as an input, the paths existing in the logic circuit are enumerated, and for all the paths, the information necessary for calculating the logic gate (element) in the path is read from the library, and the information for one stage of the logic gate is read. The delay time of the path is calculated by adding up along the path while calculating the delay time. This method does not require a test pattern.

In addition, instead of solving a circuit equation, a method of simply calculating a delay time of a logic gate and a wiring has been adopted. For example, in the "31st Design Automation Conference (1994) Preliminary Proceedings, pp. 327 to 332", the delay time T for one stage is determined by the following equation.

T = Tintrinsic + Tload + Twire + Tprev (1) where Tintrinsic is the delay time of the logic gate regardless of the load, Tload is the delay time of the logic gate due to the load, and Twire is the delay of the wiring. Time and Tprev indicate a delay time due to the rounding of the waveform in the preceding stage. Tin
“Trinsic” is a constant obtained in advance for each logic gate, and “Tload” is obtained by approximating a wiring serving as a load of the logic gate or a logic gate of the next stage with one equivalent capacitance and as a function of the capacitance. The function is predetermined for each logic gate, and is stored in the static delay calculation library together with Tintrinsic. Twire
Is obtained from the resistance and capacitance of the wiring. Tprev is
It is obtained as a function such as the rise and fall times of the signal waveform determined by the state of the logic gate and the load at the preceding stage, and the function is determined in advance for each logic gate and stored in the static delay calculation library.

As described above, in the static delay calculation, constants and functions necessary for the calculation are created in advance as a library,
By using it, a very high-speed calculation can be performed as compared with a circuit simulation because a method of solving a circuit equation, which is a complicated differential equation, by numerical calculation is not used. Further, since the delay time for all paths of the logic circuit can be calculated without a test pattern, it is used as a delay time calculation in designing a large-scale logic circuit.

However, calculation accuracy is inferior to circuit simulation. For example, in the above method, Tl
When calculating the load, it is necessary to approximate the wiring and the logic gate of the next stage with one equivalent capacitance. However, the load changes due to the effect of the resistance of the wiring and the operation state of the logic gate. Occur. Further, depending on the type of the element, there are some elements that cannot be easily modeled as in the above equation.

[0009]

As described above, as a method of calculating a delay time of a logic circuit, a circuit simulation can perform a calculation with high accuracy, but requires a great deal of calculation time. Also, it is necessary to prepare a test pattern for operating the path. For this reason, there is a problem that a large amount of advance preparation and a large amount of calculation time are required to calculate a large-scale logic circuit. On the other hand, static delay calculation has the advantage that high-speed calculation is possible and that the delay time of all paths can be calculated without a test pattern, but the calculation accuracy is inferior to circuit simulation. Was. An object of the present invention is to solve this problem and to provide a delay time calculation method capable of calculating a delay time with high speed and high accuracy even for a large-scale logic circuit.

[0010]

According to a signal delay time calculation method of the present invention, a design data of a logic circuit and a static delay calculation library of elements constituting the logic circuit are inputted, and a static delay calculation is performed for the entire logic circuit. Perform delay calculation. Further, in the static delay calculation, for a path having a problem in the calculation accuracy or a path for which a particularly high-precision calculation is to be performed, a more accurate delay time calculation is performed by using a circuit simulation. For this purpose, the path condition library that describes the conditions of the paths that are the targets of the high-precision calculations is input, and the paths that match the conditions are referenced by referring to the paths and the signal delay times obtained by the static delay calculation. Is selected.

Further, the following processing is provided for automatically executing a circuit simulation for the selected path. (1) Based on the connection information of the logic circuit, the wiring connected to the output terminal of the element and the element connected to the wiring are extracted and extracted as the element in the selected high-accuracy calculation reference path and the load of the element. (2) processing for generating circuit simulation data of a partial circuit based on circuit connection information inside the element included in the partial circuit, (3) path in the partial circuit A reference rising signal and a reference falling signal that are set in advance are set at the start node of the sub-circuit, and among the input terminals of the elements in the partial circuit, the potential fixed to the HIGH level or the LOW level is applied to the terminal to which the wiring is not connected. This is a process of generating an input signal (test pattern) for circuit simulation by setting.

A circuit simulation is executed using the circuit simulation data and the input signal created by the above processing, and a highly accurate delay time is calculated. By updating the path and the signal delay time of the path stored as the calculation result of the static delay calculation processing with this highly accurate delay time,
Automatically and quickly calculates the delay time for the entire logic circuit, and the high-precision delay time for paths that require high-precision calculations and for paths with large errors in static delay calculations. Becomes

[0013]

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a flowchart for explaining a signal delay time calculation method for a logic circuit according to the present invention. In the static delay calculation processing 101, the design data 110 of the logic circuit is input, the delay calculation is performed for all paths in the logic circuit with reference to the element static delay calculation library 111, and the result is stored in the path delay information file 112. Output to Further, the actual load circuit created in the process of this processing is stored in the actual load circuit file 120.

Next, a high-precision calculation comparison path selection process 102
In, the path delay information file 112 as an input,
The path matching the conditions is selected by referring to the high-precision calculation target path condition library 113 which describes the conditions of the paths that require high-precision calculation by circuit simulation, and stored in the high-precision calculation target path file 114. I do.

In the partial circuit cutout process 103, the connection information described in the design data 110 of the logic circuit is
A partial circuit including a path in the high accuracy calculation comparison path file 114 is cut out and stored in the partial circuit file 115.
In the circuit simulation data generation processing 104, the circuit simulation data 117 is generated from the partial circuit file 115, the in-element circuit information 116 included in the partial circuit, and the actual load circuit file 120.

Circuit simulation input signal generation processing 1
In step 05, a preset reference rising signal and reference falling signal are set at the start node of the path, and among the input terminals of the elements in the partial circuit, the HIGH or LOW level is applied to the terminal to which the wiring is not connected. , And write it into the circuit simulation data 117.

In the circuit simulation processing 106, a circuit simulation is performed on the circuit simulation data 117 generated by the circuit simulation data generation processing 104 and the circuit simulation input signal generation processing 105, and an analysis result 118 is generated.

In the delay time calculation process 107, the analysis result 1
Then, the path delay time is calculated from 18 and stored in the high-accuracy path delay information file 119. In the delay time correction processing 108, the signal delay time of the path delay information file 112 stored as the calculation result of the static delay calculation processing 101 is updated with the delay time of the high-accuracy path delay information file 119. In the delay time display processing 109, the finally obtained signal delay time is displayed on the display device.

Next, regarding the static delay calculation processing 101,
This will be described with reference to the PAD diagram of the static delay calculation process shown in (1) of FIG. As shown in FIG. 3A, the static delay calculation process 101 includes an actual load extraction process 301, a load capacity calculation process 302, a path enumeration process 303, and a path trace delay calculation process 304. The above processing will be described using an example of a logic circuit shown in FIG.

FIG. 2 shows a part of the logic circuit.
From the time when the clock signal is input to the flip-flop G201 which is the start point, the flip-flop G202 which is the end point
Is determined until the signal arrives at the input terminal. The section from the flip-flops G201 to G202 includes the logic gate elements G211 to G219. Further, logic gate elements G213, G21
8 and G219 are connected to logic gate elements G220, G221 and G222 not included in this section, respectively. Logic gate elements G220, G221, G22
2 are logic gates G213, G218, G2, respectively.
The load of 19 has the effect of increasing the delay time. Although each logic gate element is shown in FIG. 2 using an AND symbol, the logic gate element is not limited to the AND and is described for convenience. The alphabetic characters shown in each element in the figure represent the type of each element. In the logic circuit of FIG. 2, A, B, C,
Four types of elements D are used. Further, nets N231 to N240 in the figure show the connection relation between terminals of the same potential.

In the static delay calculation processing shown in FIG. 3, first, the logic circuit of FIG.
Do one. In the actual load extraction processing 301, when the design data of the logic circuit in FIG. 2 includes information after wiring, the logic circuit converts the data into resistance and capacitance according to the length of the wiring. If the design data of the logic circuit includes the placement information but does not include the wiring information, a virtual wiring length is obtained based on the arrangement location of each element, and then converted into resistance and capacitance. When the design data of the logic circuit does not include the placement and routing information, the estimation is performed based on the number of fan-outs. The resistance value and the capacitance value per unit length of the wiring differ depending on the semiconductor device on which the logic circuit is mounted and the circuit board. The resistance and capacitance created by this processing are stored in the actual load circuit file 120 in association with the net.

FIG. 4A shows the result of the conversion into an actual load circuit including a resistor and a capacitor. Next, in the load capacity calculation processing 301, the logic gate is also treated as a capacity because it acts as a load on the preceding logic gate. The resistance and capacitance of a wiring connected as a load to the output terminal of the logic gate in the section of FIG. 2 and the capacitance of the logic gate are converted into one equivalent capacitance according to a predetermined rule. This corresponds to each of the nets N231 to N240. The result is shown in FIG. As the simplest rule, there is a method in which the sum of all the capacitances is made into one equivalent capacitance. In addition, there is known a method of performing correction with a resistance value in order to consider the influence of the resistance.

Next, in the path enumeration process 303, all paths starting from the start flip-flop of the logic circuit of FIG. 2 and reaching the end flip-flop are obtained. This can be easily performed as a search problem on the graph, considering a graph in which each element is a node and the source terminal and the sink terminal of the net are edges. As a result, path information shown in FIG. 5 is obtained. In the logic circuit of FIG. 2, (1) of FIG.
There are three paths 501 to 503 indicated by thick solid lines. FIG. 5B shows the contents of the path delay information file.

Here, the path information has a structure in which elements and nets constituting the path are arranged. The names of the elements and the names of the nets correspond to the numbers given in FIG. In addition, rise delay and fall in the figure
“delay” indicates a delay time when a rising waveform is given to the start point of the path and a delay time when a falling waveform is given to the starting point of the path. The delay time is written after being calculated by the path trace delay calculation processing 304.

The path trace delay calculation processing 304 is shown in FIG.
The delay time of each element and wiring is calculated from the start point to the end point in accordance with the path information shown in (1), and the path delay time is obtained by accumulating the calculated delay times. Here, the delay time of the element and the delay time of the wiring are obtained by the following equations.

Tc = To + Td × Cl (2) Tw = Σ (RiΣCj) (3) where Tc is a delay time of the element and Tw is a delay time of the wiring. Represents To is the no-load delay time of the device, and Td is the increase in the delay time of the device per unit load capacitance. Cl
Is the load capacity obtained in the load capacity calculation processing 301.
To and Td are static delay calculation libraries 111 for elements.
It is described in.

FIG. 6 shows an example of the static delay library. FIG. 6 shows an example in which delay information of four types of elements used in the logic circuit of FIG. 2 is stored. In FIG. 6, the input / output terminals are paired and the no-load delay time To and the delay time Td per unit load capacity are stored when a rising signal is input and when a falling signal is input. I have. These delay times are obtained in advance by circuit simulation when the element is designed. Normally, the static delay calculation library 111 of the element has maximum, minimum, and average values of the no-load delay time To and the delay time Td per unit load capacity, but FIG. 6 describes only the maximum delay time. ing.

In equations (2) and (3),
This is a simplified calculation expression that does not include the waveform rounding term added in Expression (1). Ri in equation (3) is the resistance value of the i-th portion of the wiring. Cj is a capacitance existing on the end point side from Ri.

In the path trace delay calculation processing 304, calculation is performed for each of a case where a rising signal is input and a case where a falling signal is input at the start point of a path, and the result is written to the path delay information file of FIG. Normally, the maximum delay time, the minimum delay time, and the average delay time are obtained.
Shows only the maximum delay time. As described above, the path delay information file is created by the static delay calculation, and the path and the path delay time information are obtained.

In the example of FIG. 5, the delay time of the same logic gate is equal even if the path is different. For example, path 50
The element G211 of 1 is also included in the path 502,
The delay time at the time of rising input is 636 pse for both.
c. This is because, as described above, since the calculation method used here does not include the term of the rounded waveform, the delay time of the logic gate is determined only by the load capacitance regardless of the path. Therefore, in order to avoid the duplication of the calculation, the static delay calculation can be performed according to the processing flow shown in FIG. Before the path enumeration processing 303, the delay time calculation processing 305 calculates the delay time of each logic gate and wiring, and at the time of path tracing, a path trace delay addition processing 306 that simply adds them along the path. Do. In this method, calculation can be performed at a higher speed than the method (1) because there is no duplication of calculation.

Next, a high-accuracy calculation comparison path selection process 102
Will be described in detail. In the high-precision calculation target path selection processing 102, the path delay information file 112 is used as an input, and a high-precision calculation target path condition library 113 that describes conditions of a path that requires high-precision calculation by circuit simulation is referred to. Selects a path that meets the conditions.

FIG. 7 shows an example of the high accuracy calculation reference path condition library 113. Condition 701 is the path delay time Tp
The condition is that a path whose ath is 100% or more of the reference value Tref is selected. The condition 702 includes at least one element type E, and the delay time Tpath of the path is equal to the reference value Tr.
The condition is that a path that is 95% or more of ef is selected.
The condition 703 is that the delay time Tc of the circuit type C is multiplied by 1.1, the delay time of the other elements and wiring is added, and the recalculated delay time is 100% or more of the reference value Tref. It is. Condition 704 is a signal name SIG0
The condition is that a path including a net of 01 and having a delay time Tpath of 80% or more of the reference value Tref is selected. The condition 701 is a condition for recalculating a path with a delay time equal to or more than a reference value, that is, a design violation path, with high accuracy. The conditions 702 and 703 are conditions for specifying a type of an element which is expected to have a large calculation error in the static delay calculation, and recalculating a path including the element with high accuracy.

For example, in the example of the logic gate element using the pass transistor shown in FIG. 8, an error is generally large in the static delay calculation.

FIG. 8A shows a selector circuit, and FIG.
Is an ExclusiveOR circuit. Pass transistors 801 to 804 and inverters 806 and 806, respectively.
807. When a pass transistor is used, the number of transistors can be reduced and a logic gate can be formed. However, since the equivalent capacitance value changes depending on the gate potential of the pass transistor, the delay time of the preceding element changes. Therefore, an error occurs in the static delay calculation. The condition 704 is a condition for performing a highly accurate delay time calculation for a signal important in forming a logic circuit.

It is clear from FIG. 5 that all of the above conditions can be checked by referring to the information stored in the path delay information file 112 obtained by the static delay calculation. For example, the reference delay time of the section in FIG. 5 is set to 4400 psec. As shown in (2) of FIG. 5, the delay time at the time of the falling input of the path 501 is 4256.
psec, which is less than the reference value. However, when the delay time at the time of the falling input of the path 501 is recalculated according to the condition 703, the delay time Tpath ′ becomes 4445p
sec, and the path becomes a high-precision calculation control path. Next, the selected path is stored in the high accuracy calculation reference path file 114. The high accuracy calculation target path file 114 is a file of the same format as the path delay information file 112. In addition, the path delay information file 112 can be used by attaching a flag indicating that high-precision calculation is performed to the path delay information file 112 without creating a new file.

FIG. 9 shows an example in which a high-precision calculation flag is added to the path delay information file shown in FIG. Partial circuit cutout processing 10
In 3, a partial circuit including a path in the high-precision calculation target path file 114 is cut out from the connection information described in the design data 110 of the logic circuit, and the partial circuit file 1 is extracted.
15 is stored.

FIG. 10 shows a partial circuit of a path with a high-precision calculation flag in the high-precision calculation control path file shown in FIG. Since the circuit in FIG. 10 is a part of the logic circuit in FIG. 2, the elements and nets in FIG. 10 are given the same numbers as in FIG. Although a circuit simulation can be performed on the partial circuit including all the elements and nets of the logic circuit of FIG. 2, there is a problem that the processing time increases as the circuit scale increases. There is also a problem that it is difficult to create a test pattern that operates only the path of interest. Here, the minimum necessary circuit for accurately calculating the delay time of the path of interest is defined as a partial circuit, and a process of extracting the partial circuit will be described.

In the partial circuit extracting process 103, first,
List the elements included in the path information. In FIG. 10, the elements are 201, 211 to 215, 217, and 202. Next, wirings connected to the output terminals of the listed elements are extracted from the entire logic circuit. The wiring connected to the output terminal of the element can be easily extracted because it is described in the path information. In FIG. 10, the nets 231 to 235, 23
7,240. Further, an element to be added as a load of the element included in the path is extracted. The load element is an element connected to a net included in the path.
16, 218, 220. In this manner, a partial circuit for calculating a highly accurate delay time by circuit simulation including the path of interest is cut out. This is stored in the partial circuit file 115. In the next circuit simulation data generation processing 104, the circuit simulation data 1 is synthesized by synthesizing the partial circuit file 115 and the in-element circuit information 116 included in the partial circuit.
17 is generated. Here, the wiring in the partial circuit is converted into a resistance and a capacitance using the actual load circuit file 120.

FIG. 11 shows an example of in-element circuit information. FIG.
Reference numeral 1 is an example of an inverter formed of CMOS. The signal input to input terminal P1101 is inverted and output from output terminal P1102. In the circuit, a PMOS transistor T1101, an NMOS transistor T1102
In addition, as parasitic elements, resistors R1121 to R112
4. Capacitors C1131 to C1135 are included. FIG. 11 shows a circuit diagram.
Internally, it is a file that describes the connection relations and values of circuit elements such as transistors, resistors, and capacitors.

Circuit simulation data generation processing 10
4 shows a part of a circuit description example generated as a result of FIG. In the description of FIG. 12, one circuit element is indicated by one sentence,
A grammar rule is adopted in which element names, nodes to which the elements are connected, and element values are listed in order.

Circuit simulation input signal generation processing 1
The flow of operation 05 will be described with reference to the PAD diagram shown in FIG. The circuit simulation input signal generation processing 105 includes:
The processing mainly includes two processes, namely, a path start point input signal determination process 1301 and a potential floating terminal fixing process 1302.
In the path start point input signal determination processing 1301, the waveforms of a preset reference rising signal and reference falling signal are set to the path start node. In the example of the partial circuit in FIG. 10, since the element serving as the starting point is the flip-flop G201, the input terminal is fixed to HIGH or LOW, and a preset clock signal is supplied to the clock terminal. Next, in the potential floating terminal fixing process 1302, it is checked whether or not there is an input terminal to which a wiring is not connected, that is, a potential floating terminal, for an element in the partial circuit. In order to execute a circuit simulation, it is necessary to set a potential fixed to a HIGH level or a LOW level to a potential floating terminal.

In the partial circuit shown in FIG.
212, G213, G215, and G217, which is an element of element type D, have a potential floating terminal. The potentials of these potential floating terminals need to be determined so that when an input signal is applied to the start point of a path, a signal change is sequentially transmitted to the end point along the path. This condition corresponds to condition 1 shown in FIG. The fixing of the potential satisfying the condition 1 will be described with reference to the example of FIG.

FIG. 14A shows an AND gate and its truth table. Here, the I2 terminal is a potential floating terminal. When the I2 terminal is fixed at the LOW level (the case of 1 and 3 in the truth table in the figure), the potential of the output terminal O1 becomes the LOW level regardless of whether the potential level of the I1 terminal is LOW or HIGH. I have. When the I2 terminal is fixed at the HIGH level (2 and 4 in the truth table in the figure)
In the case where the potential level of the I1 terminal is LOW (in the case of 2 in the truth table in the figure), the potential of the output terminal O1 is at the LOW level, and when the potential level of the I1 terminal is HIGH (the truth table in the figure). In the case of 4), the potential of the output terminal is H
It becomes IGH level. In other words, when the terminal I2 is fixed at the LOW level, the signal change at the terminal I1 causes the output terminal O to change.
If the I2 terminal is fixed at the HIGH level without propagating to 1, the signal change at the I1 terminal propagates to the output terminal O1. This indicates that the I2 terminal needs to be fixed at the HIGH level.

FIG. 14B shows an OR gate and its truth table. Here, the I2 terminal is a potential floating terminal. When the I2 terminal is fixed at the LOW level (1 and 3 in the truth table in the figure), when the potential level of the I1 terminal is LOW (1 in the truth table in the figure), the output terminal O1 is used. Becomes LOW level, and the potential level of the I1 terminal is HIGH (in the case of 3 in the truth table in the figure).
Means that the potential of the output terminal is at the HIGH level. When the I2 terminal is fixed at a HIGH level (2 in the truth table in the figure).
And 4), the potential level of the I1 terminal is LOW,
Regardless of HIGH, the potential of the output terminal O1 is HIGH
Level. That is, when the I2 terminal is fixed at the HIGH level, the signal change at the I1 terminal does not propagate to the output terminal O1, and when the I2 terminal is fixed at the LOW level, the signal change at the I1 terminal is applied to the output terminal O1. Will be propagated. This indicates that the I2 terminal needs to be fixed at the LOW level.

Next, the case where there are a plurality of fixed potentials satisfying the condition 1 will be described. An element shown in FIG. 15 and including three AND gates 1501 to 1503, two inverters 1504 and 1505, and one OR gate 1506 is considered. The input terminals I2 and I3 are potential floating terminals. According to the truth table of the device of FIG. 15, in order to transmit a signal change of the terminal I1 to the output, both I2 and I3 are set to H level.
It can be seen that there is a case where the signal is at the IGH level and a case where both I2 and I3 are at the LOW level. In this case, it cannot be determined only by the condition 1, but must be determined by the condition 2. Condition 2 is determined in consideration of the delay time of the element. This can be determined by changing the conditions and executing a circuit simulation with the element of interest alone, and examining under which conditions the delay time is maximized or minimized.

Further, in addition to the delay time information, potential conditions of terminals other than the input terminal of interest can be described in the static delay library of the element. An example is shown in FIG. According to this, it is understood that the delay time is longer when both I2 and I3 are fixed at the LOW level. Therefore,
To determine the maximum delay, both I2 and I3 are fixed at the LOW level, and to determine the minimum delay, the I2 and I3 are fixed at the HIGH level.

Next, a more complicated example will be described. In the example of FIG. 15, two types of fixing of the potentials of I2 and I3 can be selected. In both cases, when a rising signal is input to I1, a rising signal is output to O1,
When a falling signal is input to I1, a falling signal is output to O1. As described above, when the signal polarity between I1 and O1 does not depend on the potential of another input terminal, the potential can be determined by the above method. However, the Excl shown in FIG.
In the case of a useOR gate, I1 is determined by the potential of I2.
And the signal polarity of O1 changes. Consider I2 as a potential floating terminal. As can be seen from the truth table, the potential of I2 is LOW.
The signal change of I1 propagates to the output terminal O1 regardless of the level or the HIGH level. However, when I2 is fixed at the LOW level, when the input signal of I1 is at the LOW level, O1
Becomes LOW level, but when I2 is fixed to HIGH level, when I1 input signal is LOW level,
1 becomes HIGH level, and the polarity between I1 and O1 is different. In this case, a comparison of only the delay values of the elements alone, such as the elements in FIG. 15, does not reveal the magnitude relation of the path delay values. This is shown in ExclusiveOR shown in FIG.
A simple path using a gate will be described.

FIG. 18 shows inverters G1801 and G18.
3 shows a path composed of three elements, that is, an exclusive OR gate 1802 and a delay time thereof. Exclu
Assuming that the input terminal I2 of the five-OR gate 1802 is a potential floating terminal, as shown in FIG. 18, there are four types of signals depending on whether the potential of I2 is HIGH or LOW, and whether the input signal at the starting point rises or falls. There is a change and each delay time is different. When the waveform rounding is not considered, the wiring delay of the same net is equal under all conditions, and therefore the wiring delay is omitted in FIG. E
Focusing only on the delay time of the xplusOR gate 1802, the maximum delay time is obtained when the item No. 4 I2 is fixed at the LOW level and the input at the start point falls.
However, when the delay times of the respective elements are added along the path, the maximum delay time is obtained in the case of item No. 2, that is, when I2 is fixed at the HIGH level and the input at the start point rises.

As described above, in order to obtain the maximum (minimum) delay time, it is necessary to determine the fixed potential of the potential floating terminal in consideration of the signal change of all the gates in the path. This is because, as a result of performing the static delay calculation processing 101, the polarity of each element is described in the path delay information file 112 together with the delay information, and the path delay information file 112 is referred to in the potential floating terminal fixing processing. The potential level of the potential floating terminal can be determined.

The circuit simulation input signal obtained by the above processing is written into the circuit simulation data 117, and the preparation for the circuit simulation processing 106 is completed. In the circuit simulation processing 106, a circuit simulation is executed on the circuit simulation data 117 generated by the circuit simulation data generation processing 104 and the circuit simulation input signal generation processing 105, and an analysis result 118 is generated.

Regarding the circuit simulation processing,
Since there are many well-known techniques, the description is omitted here. The form of the analysis result of the circuit simulation can be output in various forms. As an example, FIG. 19 shows a form in which the potential of each node of the circuit is output every time. Here, the potential output nodes are only the input terminal nodes and the output terminal nodes of the elements in the path. In the delay time calculation processing 107, the delay time of the element and the wiring is obtained from the analysis result 118. Usually, the delay time is generally defined as a time difference at which the input / output potential becomes 50% of the logic amplitude.

In the case of the analysis result in the form of FIG. 19, two points closest to 50% of the logic amplitude are obtained from the potential of each node at each time, and the two points are linearly complemented.
The time of 50% of the logic amplitude can be obtained. In order to obtain the delay time of the entire path, only the potential at the start and end points is required. However, in the delay time correction processing 108, the path delay information file as shown in FIG. In order to update the signal delay time of 112, the delay time of the element is calculated from the potential at each time of the input / output node of the element.
The wiring delay time is obtained from the potential of the output node of the element and the potential of the input node of the next-stage element every time. The result is stored in the high-accuracy path delay information file 119. In the delay time correction processing 108, the signal delay time of the path delay information file 112 is updated with the delay time of the high-accuracy path delay information file 119. At this time, for a path calculated by the circuit simulation, identification information indicating that the path has been calculated by the circuit simulation is added to the path delay information. As described above, the delay time of the entire logic circuit is obtained by static delay calculation, and for parts that require special accuracy and paths that include elements with large errors in static delay calculation, highly accurate delay calculation is performed by circuit simulation. Was able to do.

Finally, in the delay time display processing 109, the finally obtained signal delay time is displayed on a display device together with a logic circuit diagram or a layout diagram. At this time, the path that has recognized the identification information indicating that the calculation has been performed by the circuit simulation is displayed in a manner different from the delay time obtained by the static delay calculation and the display mode. FIG. 20 is a diagram showing a result of delay calculation performed on the logic circuit of FIG. 2, showing a case where only the path 501 of FIG. 5 is subjected to high-precision delay calculation by circuit simulation. (1) is a display in which the display form of the logic circuit diagram is changed, and the thickness of a line to be drawn is changed. (2) is an example in which the display format of the displayed delay time is changed, and the delay time value is displayed with a frame. In both (1) and (2), the numbers displayed on the wires indicate the wiring delay times, and the numbers displayed on the elements indicate the calculated values of the delay times of the elements. In addition, by changing the display mode by changing the color and displaying, the designer can easily recognize the portion where the delay calculation has been performed with high accuracy by circuit simulation.

[0055]

As described above, according to the signal delay time calculation method of the present invention, the design data of the logic circuit and the static delay calculation library of the elements constituting the logic circuit are input to the entire logic circuit. The static delay calculation is performed on the path. In the static delay calculation, a path with a problem in the calculation accuracy or a path in which a particularly high-precision calculation is to be performed is performed by using a circuit simulation to obtain a more accurate delay time. Calculations can be made.

A path to be subjected to high-precision calculation is input to a high-precision calculation control path condition library describing conditions of a path to be subjected to high-precision calculation, thereby obtaining a path and a signal of the path obtained by static delay calculation. Since the path matching the condition is automatically selected by referring to the delay time, the path can be comprehensively listed without having to manually select the path. As a result, a path to be calculated in a circuit simulation requiring a long processing time can be selected in a minimum necessary and exhaustively, and an increase in the calculation time can be suppressed.

For the selected path, a necessary and sufficient partial circuit for calculating the selected path by circuit simulation is cut out based on the connection information of the logic circuit, and the circuit simulation data of the partial circuit is extracted. It can be created automatically.

Further, since a process for generating an input signal (test pattern) for circuit simulation is provided, there is no need to manually create a test pattern. A circuit simulation is executed using the circuit simulation data and the input signal created by the above processing, and a highly accurate delay time is calculated. By updating the path and the signal delay time of the path stored as the calculation result of the static delay calculation processing with the high-precision delay time, the delay time of the entire logic circuit and particularly the high-precision calculation It is possible to automatically and quickly calculate a high-accuracy delay time for a path that requires the above-mentioned method, a path having a large error in the static delay calculation, and the like.

[Brief description of the drawings]

FIG. 1 is a processing flowchart showing an embodiment of the present invention.

FIG. 2 is an example of a logic circuit whose delay time is to be calculated.

FIG. 3 is a PAD diagram of a static delay time calculation process.

FIG. 4 is a diagram of an actual load circuit including a resistor and a capacitor, and a diagram of a circuit in which a load is approximated by a capacitor.

FIG. 5 is a diagram illustrating paths of a logic circuit and path delay time information.

FIG. 6 is a diagram illustrating an example of a static delay calculation library of an element.

FIG. 7 is a diagram showing an example of a high-precision calculation control path condition library.

FIG. 8 is a diagram illustrating an example of a logic gate element having a large error in a static delay calculation.

FIG. 9 is a diagram illustrating a path to which information of a path for which high-precision calculation is performed is added, and path delay time information;

FIG. 10 is a diagram showing an example of a partial circuit cut out for performing a circuit simulation.

FIG. 11 is a diagram showing an example of circuit information in an element.

FIG. 12 is a diagram showing a part of a description of circuit simulation data.

FIG. 13 is an explanatory diagram of a circuit simulation input signal generation process.

FIG. 14 is a diagram illustrating an example of a logic gate capable of uniquely determining a fixed potential of a potential floating terminal.

FIG. 15 is a diagram illustrating an example of a logic gate in which a fixed potential of a potential floating terminal cannot be uniquely determined.

FIG. 16 is a diagram illustrating an example of a static delay calculation library to which a fixed potential of a potential floating terminal is added.

FIG. 17 is a diagram illustrating an example of a logic gate in which the fixed potential of the potential floating terminal cannot be uniquely determined.

FIG. 18 is a diagram illustrating an example of a logic gate whose signal polarity changes according to a fixed potential of a potential floating terminal.

FIG. 19 is an example of an analysis result of a circuit simulation.

FIG. 20 is a diagram showing a result of performing a delay calculation.

[Explanation of symbols]

G201 to G202, G1801 to G1803 ... Logic gate element, N231 to 240 ... Net, 501 to 503 ... Path, I1 to I3, P1101, P1102, S1, S2 ... Input terminal, O1 ... Output terminal, R1121 to R1124 ... Resistance, C1131 to 1135: Capacitance, T1111: PMOS transistor, T1112: NMOS transistor.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Ichiro Kono 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd.

Claims (14)

[Claims] 1. A signal delay time calculating method for automatically calculating a signal delay time by using a computer system having an arithmetic processing unit, a storage unit, a display unit, and an input / output unit with design data of a logic circuit as an input. A static delay calculation library for elements constituting a logic circuit is input, a static delay calculation is performed for the entire logic circuit, and a path in the logic circuit as a calculation result and a signal delay time of the path are stored in a storage device. A path matching the above condition is selected from the above static delay calculation result, with the input of the high-accuracy calculation target path condition library describing the conditions of the path to be compared with the high-precision calculation, which is stored in the static delay calculation processing. Based on the high-precision calculation target path selection processing and the connection information of the logic circuit, the wiring in the selected high-precision calculation target path and the wiring connected to the output terminal of the element and the wiring A partial circuit cutout process of extracting a connected element and storing the extracted element and wiring as a partial circuit, based on connection information of the partial circuit and circuit connection information inside the element included in the partial circuit, A circuit simulation data generation process for generating circuit simulation data of the partial circuit; and setting a preset reference rising signal and a reference falling signal at a start point node of the path in the partial circuit. A circuit simulation input signal generation process for setting a potential fixed to a HIGH level or a LOW level to a terminal to which no wiring is connected among input terminals of the element, and a circuit simulation data generated by the circuit simulation data generation process. Created by the circuit simulation input signal generation process. A circuit simulation process of executing a circuit simulation using an input signal and storing an analysis result; a delay time calculation process of calculating a delay time of the path from an analysis result obtained by the circuit simulation process; and the delay time calculation With the high-precision delay time calculated by the processing, the path stored as the calculation result of the static delay calculation processing and the delay time correction processing for updating the signal delay time of the path, and finally obtaining A delay time display process of displaying the obtained signal delay time on a display device. 2. The logic circuit design data includes wiring information, and in the static delay calculation processing, based on physical characteristics of a semiconductor device or a circuit board on which the logic circuit is mounted.
2. The signal delay time calculation method according to claim 1, wherein the wiring information is converted into a resistance and a capacitance to calculate a delay time. 3. The design data of the logic circuit does not include wiring information. In the static delay calculation process, a virtual wiring length is estimated, and the physical data of a semiconductor device or a circuit board on which the logic circuit is mounted is estimated. 2. The delay time is calculated by converting the virtual wiring length into a resistance and a capacitance based on the characteristic.
The described signal delay time calculation method. 4. A condition that the delay time of a path is equal to or more than a predetermined ratio with respect to a reference value determined from a cycle time of a logic circuit to be designed is described in the high-precision calculation target path condition library. Claim 1
The described signal delay time calculation method. 5. The signal delay time calculation method according to claim 1, wherein said high-precision calculation control path condition library includes a condition specifying a type of an element included in the path. 6. The signal delay time calculating method according to claim 1, wherein a condition specifying a signal name included in the path is described in the high-precision calculation control path condition library. 7. In the high-precision calculation target path selection processing, the delay time stored by the static delay calculation processing is added to the path matching the condition described in the high-precision calculation target path condition library together with the logic circuit. The signal delay time calculation method according to claim 1, wherein a signal is displayed on a display device, a designer refers to the display device, adds a path selected by a process of designating a path using an input device, and performs subsequent processing. 8. A fixed potential of an input terminal in the circuit simulation input signal generation processing, wherein a signal level of an output terminal changes when a signal level input to an input terminal connected to a wiring of the element changes. 2. The signal delay time calculation method according to claim 1, wherein the potential is a fixed potential that satisfies a condition under which the change occurs. 9. A fixed potential of an input terminal in the circuit simulation input signal generation processing, wherein a signal level of an output terminal changes when a signal level input to an input terminal connected to a wiring of the element changes. 2. The signal delay time calculation method according to claim 1, wherein when a potential satisfying a condition that causes a change in the delay time is not uniquely determined, the signal is a fixed potential at which the delay time becomes maximum or minimum. 10. In the circuit simulation input signal generation processing, a fixed potential of an input terminal is previously obtained for each input terminal of each element, and described in a static delay calculation library of the element, and the library is referred to. 2. The signal delay time calculation method according to claim 1, wherein the fixed potential of the input terminal is determined. 11. In the circuit simulation input signal generation processing, the signal applied to the start node of the path and the fixed potential of the input terminal are the maximum delay or the minimum delay of the path in the result of the static delay calculation processing. 2. The signal delay time calculation method according to claim 1, wherein a signal applied to the start node of the path and a fixed potential of the input terminal are such that each element changes the signal in the same manner as the signal change. 12. A path for which a high-precision calculation has been performed by the circuit simulation processing is obtained by adding identification information for recognizing that a high-precision calculation has been performed to delay information of a path stored as a calculation result. 2. The signal delay time calculation method according to 1. 13. In the delay time display processing, a path delay time is displayed together with the logic circuit diagram or the layout diagram of the logic circuit, and the high-precision calculation added to the path delay information is performed. 2. The signal delay time calculation according to claim 1, wherein a display form of the path for which the delay time is calculated by the static delay calculation processing and a display form of the path calculated with high accuracy by the circuit simulation processing are displayed differently by the identification information capable of recognizing the delay time. Method. 14. The logic circuit design data, the delay time information of the logic circuit calculated by a plurality of different delay time calculation methods for each part of the logic circuit, and the calculation which calculates the delay time information. A method of inputting together identification information capable of recognizing a method, and displaying a delay time on a display device, wherein the delay time is displayed together with a circuit diagram of the logic circuit or a layout diagram of the logic circuit, and the delay information is displayed. A delay time display method for recognizing a calculation method used for each partial circuit based on the identification information added to the sub-circuit, and changing and displaying a logic circuit diagram, a layout diagram, or a delay time display form for each calculation method.