JPH1063576A - Hierarchical disk device and control method therefor - Google Patents

Abstract

(57) [Summary] [Problem] In a hierarchical disk cache,
It is possible to suppress the occurrence of duplication of data between caches and a decrease in cache use efficiency. Each of the hierarchized control devices is provided with a memory for storing a hierarchy level of its own control device, and when reading data, reads out the hierarchy level in the memory. Performs control not to store data. [Effect] Since the data stored in each cache does not overlap, the use efficiency of the cache is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a disk controller, and more particularly, to a hierarchical disk controller and a control method for improving the utilization efficiency and the performance of a hierarchical disk cache.

[0002]

2. Description of the Related Art Generally, a computer system comprises a processor and a secondary storage device. A secondary storage device mainly used is a magnetic disk device. Currently, disk storage capacity growth is extremely high,
The performance of a magnetic disk drive involving mechanical operations is not as high as the rate of increase in processor performance. The following two methods are known as methods for solving the problem.

A first method is to provide a disk cache in a disk control device. The disk cache stores data that has been read once in a disk cache, which is a semiconductor memory, and retrieves data from the disk cache when a read request for the same data occurs again, so that access to the disk device can be performed. This is a method for reducing and increasing the speed. The more caches, the better the hit rate and performance, but
Since the cost per capacity is higher than that of a magnetic disk, it is usually several tens to several tens of the capacity of the magnetic disk.
A capacity of 1/0 is provided. In the cache control method, data is stored in the order of the most frequently accessed, and data that has not been accessed most is evicted. This is called LRU processing and is common in cache control methods. These methods are described in JP-A-6-231455.

[0004] The second method is a method of improving performance by controlling magnetic disks in parallel. D.Patterso
"A Case for Red" by n, G. Gibson, and RHKartz
undantArrays of Inexpensive Disks (RAID), in ACM SI
GMOD Conference, Chicago, IL ", PP.109-116 (June 1
988) (hereinafter referred to as a first reference) shortens access time to data stored in a disk by distributing and allocating data to a plurality of disk drives, and is called parity or ECC. There is introduced a disk array configuration technology called RAID, which increases reliability by storing redundant data.

That is, in the array disk, data is read or written at a high speed because data is input / output to / from a plurality of disk drives in parallel. From this data, the data of the failed disk drive can be recovered.

More specifically, in the above-mentioned literature, RAID levels are classified into a plurality of types according to the data storage method.
Among them, the RAID level often used in products is R
AID1, RAID3, and RAID5. RAID1
Is mirroring, and the same data is stored in two disks to increase reliability against disk failure. At the time of reading, reading from the earlier disk of the two disks is faster than that of a single disk. RAID 3 can improve data transfer performance by striping single data bit by bit or byte by byte and reading / writing data from / to a plurality of disks in parallel.
RAID5 is a level at which striping is performed on a plurality of disks in units of input / output blocks.

In RAID3, a single input / output request is striped in smaller units, whereas in RAID5, striping is performed in larger units. The main purpose of RAID3 is to speed up large-scale data input / output of a single user, while the main purpose of RAID5 is to execute small-scale data input / output of many users in parallel. Therefore, RAID3 is used particularly for multimedia and scientific and technical calculations that require large-scale data input / output. RAI
D5 is used for database processing which is an online transaction for providing services of many users. A general disk array incorporates both the cache control described above and the parallel operation of disks to improve performance.

On the other hand, there is a growing demand for a large-capacity, low-cost disk array. In this case, a configuration in which a large number of disk devices are connected to a single disk array controller is conceivable, but the capacity increases but the performance does not increase due to the limit of the performance of the control processor in the disk array controller. Occurs. The control processor is provided to interpret and execute input / output requests from the host. Since a processing performance proportional to the number of disk devices to be controlled is required, at present, most disk arrays are several to several tens.

As a method for solving this problem, Japanese Patent Laid-Open Publication No. Hei 7-44322 discloses a method of hierarchizing control devices. The purpose of this is to reduce the number of control devices that must be controlled by layering the control devices. For example, assume that one controller can control five disk drives. One control device is provided at the highest level, and a plurality of outputs of the control device are connected to inputs of different control devices. This makes it possible to control a large number of disk devices as a whole.

[0010]

SUMMARY OF THE INVENTION Japanese Patent Laid-Open No. 7-44322
In the hierarchized disk array control device described in Japanese Patent Application Laid-Open Publication No. H10-209, a method of applying a cache becomes an issue.
The simplest way is to have a cache only in the top-level controller. However, since the cache capacity that can be connected to a single control device is not large, sufficient performance cannot be expected with a small-capacity cache for many disk devices. Therefore, a method of providing a cache in each of the hierarchized control devices can be considered. In this case, each cache performs the aforementioned LRU control. If control is performed to leave the most recently accessed data in each of the hierarchical caches, data that is duplicated between caches will be stored.

For example, it is assumed that a hierarchical disk array in which the control devices 2 and 3 are connected to the control device 1 and each control device is provided with a cache. It is assumed that a plurality of disk devices are connected to the control devices 2 and 3, respectively. At this time, when a read request to the disk connected to the control device 2 is issued, the control device 2 reads data from the disk and stores the data in its own cache according to LRU control. When the control device 2 transfers the data to the upper control device 1, the control device 1 stores the data in its own cache similarly to the control device 2. In this case, there arises a problem that data that only needs to be stored in the upper control device is redundantly stored in a plurality of caches. Note that Japanese Patent Application Laid-Open No. H7-44322 does not describe a cache control method.

An object of the present invention is to provide a means for suppressing duplicate storage of data in a plurality of caches and effectively using the caches.

[0013]

In order to achieve the above object, each of the hierarchized control devices is provided with a memory for storing a hierarchy level of its own control device, and when reading data, the hierarchy in the memory is read out. The level is read, and control is performed so that data is not stored in its own cache unless it is the highest control device. In addition, at the time of writing, the data is stored in the cache, the data required for parity generation is searched for in the upper cache, and if there is, the data is transferred from the upper controller to the cache in the lower controller to generate the parity. To

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a hierarchical disk cache control method according to the present invention will be described in more detail with reference to the drawings and embodiments.

FIG. 1 is a schematic block diagram of a disk array controller to which a hierarchical disk cache control method according to the present invention is applied. 102 is a disk array controller, and 137 and 138 are disk devices to which the disk array controller 102 performs input / output. The disk array control device 102 is connected to the host processor 101. The disk array controller 102 receives a disk input / output request from the host processor 101 and performs input / output with respect to the disk devices (137, 138). The disk array controller 102 includes a higher-level controller 103 and a plurality of lower-level controllers (139, 112). Plurality of lower control devices (139, 112)
Performs input / output of the disk devices (137, 138), the higher-level control device 103 receives and interprets an input / output request of the host processor 101, and performs a plurality of lower-level control devices (104,
112), the input / output requests are distributed.

The host control device 103 includes the control processor 1
06 (hereinafter abbreviated as CPU), a cache control memory 107 (hereinafter abbreviated as CCM), a microprogram 108, a host interface controller 104, a higher-level cache 105, a switch 109, and interface controllers (110 and 111). The main function of the host controller 103 is to interpret a disk input / output request of the host processor 101 and distribute the result to a plurality of lower controllers (139, 112). These controls are performed by the CPU 106, and the procedure and method of this control are described as software called a microprogram 108.

The microprogram 108 is usually stored in a semiconductor memory, and is read out from the CPU 106.
Execution takes place. Host interface control unit 104
Controls the connection with the host processor 101, accepts input / output requests, and transmits and receives data. Switch 10
Reference numeral 9 has a function of distributing input / output requests to a plurality of lower control devices (139, 112). With an instruction from the CPU 106,
It is determined to which lower-level control device the input / output request is to be distributed. The interface control units (110, 111) control connection with the lower-level control devices (139, 112), and transfer input / output requests and transmit / receive data. Host controller 10
3 is an upper cache 10 for speeding up input / output.
There are five.

The upper cache 105 is provided to temporarily store data requested by the host processor 101, thereby reducing access to the disk devices (137, 138) and speeding up input / output processing. Can be C
The CM 107 stores information on a control method of the upper cache.

The lower controllers (139, 112) include interface controllers (113, 125) for controlling connection with the upper controller 103, and lower controllers (139, 11).
2) CPUs (114, 126), microprograms (116, 128), and disk devices (137,
138), the lower caches (124, 130) for temporarily storing the data, and the lower caches (124, 13).
CCM (115, 1) storing control information related to
27), a switch for distributing disk commands (12
3, 131), and interface control (117-121, 1) for controlling the connection with the disk devices (137, 138).
32 to 136) and parity control (122, 129).

The main function of the lower control devices (139, 112) is to perform disk array control for improving performance and reliability. There are a plurality of types of disk arrays depending on the method of storing data and parity. In the present embodiment, any of them can be used. The main types are as follows. RAID1 is mirroring, and the same data is stored in two disks to increase reliability against disk failure. At the time of reading, reading from the earlier disk of the two disks is faster than that of a single disk. RAID
No. 3 can improve data transfer performance by striping (dividing) single data for each bit or byte.

RAID 5 is a level for striping a plurality of disks in units of input / output blocks.
In RAID3, a single input / output request is striped in smaller units, whereas in RAID5, striping is performed in larger units. The main purpose of RAID3 is to speed up the input / output of a single user.
The main purpose 5 is to execute input and output of a plurality of users in parallel. Therefore, RAID3 is used for multimedia or scientific / technical calculations for processing images or the like that require large-scale data input / output. RAID5 is used for database processing which is an online transaction for providing services of many users.

In any of RAIDs 1, 3, and 5,
Reliability is also improved by writing redundant data to the disk at the same time as storing data. Specifically, RAID1
In case (1), the same data is written to a plurality of disks to provide redundancy. In RAID3 and RAID5, data is striped to multiple disks.
The exclusive OR of old data, old parity, and new data is written to the disk as new parity. By doing this,
If one of the disks fails, RAID1,
In each of the cases 3 and 5, it is possible to recover the data of the failed disk.

For example, it is assumed that data is stored in RAID 3 as follows. Disk 1 data = 10101010 Disk 2 data = 11110000 Disk 3 Parity = 011011010 In this state, if the disk 2 fails and cannot be read / written, the exclusive OR of the disk 1 and the disk 3 is calculated. Disk 1 data = 10101010 Disk 3 Parity = 01011010 Logical sum = 11110000 (data of disk 2) In this manner, data of disk 2 can be reproduced. The parity control (122, 129) in FIG. 1 is a mechanism for generating parity.

In the present invention, as shown in FIG. 1, the cache is composed of the upper control device 103 and the lower control device (139, 11).
It is hierarchized between 2). The effect of layering the cache is that the configuration can be flexibly changed according to the required access time and cost. As an example, the upper cache 105 is composed of a high-cost but high-speed semiconductor memory to hold frequently accessed data, and the lower cache is composed of a slower but lower-cost semiconductor memory than the upper cache. Can be considered. Most of the disk controllers had a single cache, and thus could not have such a flexible configuration.

A feature of the present invention is that in a disk array control device in which caches are hierarchized, a host control device 10
3 and a plurality of lower-level control devices (104, 112) are provided with caches (105, 124, 130), and control is performed to eliminate duplication of data stored in each other's caches, thereby improving cache use efficiency. That is.

FIGS. 2 and 3 show an outline of an embodiment of the present invention. FIG. 2 shows an outline of the operation, and FIG. 3 shows an effect. 201 is an upper cache,
A plurality of lower caches (20
5, 206) are connected to form a hierarchical cache structure. It shows an operation when an input request is issued from the host processor. When an input request for the data 204 stored in the disk device occurs, whether to store the data in the lower cache is determined based on the hierarchical level. The hierarchy level defines the cache closest to the host processor as the highest level (hierarchy level = 0) 208, and the rest is hierarchy level = 1 (209, 210). Whether to store in the cache or not is determined by determining whether the own cache is the top-level cache.
Since the lower cache 205 is not the highest cache, the lower cache 205 does not store the read data 212. The read data is transferred to the upper cache 201.

Here, similarly to the lower cache, it is determined whether or not the cache is the highest cache (211). Here, since it is the top-level cache, the data read into the cache is stored (202), and the data is simultaneously transferred to the host processor. At this time, if the highest-order cache is full, the eviction process of any data in its own cache is performed. The data 203 selected as the eviction data is transferred to a predetermined lower cache (207). The lower cache does not determine whether data transferred from the upper cache is to be stored. The determination as to whether to store the data is made only when data is transferred to a higher level than the own cache, and the data transferred from the higher level is unconditionally stored. This means that the top cache stores only the most frequently used data,
This is because the data that could not be stored in the upper cache is stored in the lower cache to improve the cache hit rate.

By performing the control shown in FIG. 2, the effect shown in FIG. 3 can be obtained. FIG. 3 is a diagram comparing the effect of the conventional cache control with the effect of the hierarchical cache in the embodiment of the present invention. In the conventional cache control, data duplication occurs because all caches perform exactly the same control. Twelve data can be stored in the upper cache 1101, and the lower cache (1102, 1103)
Shows a case where six data can be stored respectively.

When an input request is issued from the host processor, the upper cache 1101 and the lower cache (110
(2, 1103) control is performed to keep the most recently accessed data. As a result, the data stored in the cache is duplicated, and the cache is wasted. In the present invention, the upper cache 1104
, The most frequently accessed data is left as in the past, and the lower cache (1105, 1106) is controlled not to store the data transferred to the upper cache 1104. No duplication occurs. Therefore, the area where the duplicate data is stored in the past becomes an empty area, and new data can be stored in this area.

FIG. 4 shows the structure of the microprogram 301 according to the embodiment of the present invention. Host controller 10
3 and the lower control devices (139, 112) have the same configuration. 302 is a command control, 303 is a hierarchical cache control, 304 is a cache management list, 305 is a disk read & prefetch control, 306 is a disk write & batch write control, and 307 is a hierarchical cache initial setting control. A request from a higher-level device than the own control device is accepted and interpreted by the command control 302. as a result,
Disk read & read ahead control 3 if read processing
05 is called, and if it is a write process, the disk read & prefetch control 306 is called. In the disk read & prefetch control 305 and the disk read & prefetch control 306, the hierarchical cache control 303 is called, and the cache control in the own control device is performed. At that time, the cache management list 304 is used. The cache management list 304 is a use list of the own cache,
An empty list is stored. The hierarchical cache initial setting control 307 is mainly executed at the time of device startup, and sets information necessary for controlling the hierarchical cache. These pieces of information will be described below.

FIG. 5 shows a data structure of the CCM (107, 115, 127) in which information necessary for controlling the hierarchical cache is stored. These pieces of information are set by the hierarchical cache initialization control 307 at the time of starting the apparatus. Reference numeral 401 denotes a hierarchy level field. The cache closest to the host processor is at hierarchy level 0, and the rest is at hierarchy level 1. Cache control mode 4
A flag 02 indicates whether or not to perform cache read-ahead and batch write control. The cache use upper limit value 403 and the cache use lower limit value 404 store numerical values indicating when the cache overflow and the prefetch control are performed. When the cache usage reaches the cache usage upper limit, data is transferred to the lower-level control device or the disk device to increase the unused area. When the value falls below the cache use lower limit value, the data is pre-read from the lower-level control device or the disk device to increase the data stored in the cache. Cache use list pointer 40
Reference numeral 5 and a cache unused list pointer indicate a pointer to the cache management list 304 in FIG. 4, and are used when securing or releasing a cache.

FIG. 6 shows the microprogram 301 of FIG.
2 shows a flow of the command control 302 in FIG. Step 501 is a process of receiving a disk input / output command transferred from a higher-level device. Step 502 determines a command. Here, it is determined whether the command is an input request or an output request. If the command is an input request (READ), the process proceeds to step 503. If the command is an output process (WRITE), the process proceeds to step 506.

Step 503 performs disk read & prefetch control. This process will be described later in detail. In step 504, cache control is performed on the data read in step 503. In step 505, an end report is sent to the host device. Step 506 performs hierarchical cache control of the data transferred from the host device. Step 507 performs disk writing and batch writing control.
This process will be described later in detail. A step 508 sends a completion report to the host device.

FIG. 7 shows the hierarchy cache control 303 of FIG.
FIG. Step 601 is a command determination process, which determines whether the request is an output request or an input request. If it is an input request, the process proceeds to step 602; if it is an output request, the process proceeds to step 609. In step 602, the CCM (FIG. 1)
Of the hierarchy level field (401 in FIG. 5) in the columns 107, 115, and 127). In this field, 0 is stored for the top cache, and 1 is stored for other caches. Step 6
03 determines whether the own cache is the top-level cache or not. If it is the top cache, step 60
4; otherwise, go to step 606. In step 604, LRU processing is performed. What is LRU processing?
An algorithm that determines which data is evicted when the cache becomes full, and is generally used for cache management.

In step 604, the data transferred in response to the read request is stored in the cache with the highest priority. If the cache is full at that time, a process of flushing any data from the cache is performed. . In step 605, the data is transferred to the host device.

Steps 606 and 607 are processing when the own cache is not the highest cache. If the cache is not the highest-level cache, control for not caching is performed. This is because there is no need to store data in its own cache if it is stored in a higher-level cache because a higher-level cache exists. Step 6
At 06, the data is transferred to the host device. Step 60
At 7, the cache area is released.

Steps 604, 605, 606, 607
Thus, if the own cache is the top-level cache, the process is stored in the cache, and if not, the process is not stored in the cache. For this determination, information indicating the hierarchy level is stored in the CCM for each cache.

Step 609 is executed in the case of write processing, and normal LRU processing is performed. With this hierarchical cache control, in a hierarchical cache configuration, data that is duplicated between caches can be eliminated, and the cache utilization efficiency can be improved.

FIG. 8 shows the data structure of the cache management list 304. 405 is a cache use list pointer in FIG. 5, and 406 is a cache unused list pointer. In the cache use list pointer 405, areas used in the own cache are stored in a list format, and in each list, a pointer 703 to the next list and a use area identifier 704 are stored. Pointer 703 to the list next to the end of the list
Stores the value indicating the end of the list. This list is
When referenced, control is performed to switch the list chain at the end of the list.

As a result, the most recently accessed area is placed at the end of the list, and the least recently accessed area is chained to the list closest to the cache use list pointer 405. Therefore, when the cache becomes full and any area must be released, the cache usage list pointer 4
LRU control is realized by selecting the list closest to 05. In the list indicated by the cache unused list pointer 406, an unused cache area is chained, and when securing a cache, the head or area of the list is selected.

FIG. 9 shows the flow of the disk read & prefetch control. In step 801, it is determined whether or not the data requested by the host device is stored in the cache. This can be realized by searching the cache use list of FIG. In step 802, if data is stored in the cache (cache hit), the process ends. If not stored in the cache (cache miss), the process proceeds to step 803.
In step 803, a cache area is secured. This can be realized by selecting the list indicated by the cache unused list pointer in FIG. Step 804
Then, a disk input request is generated, and data is input from the disk device. Step 805 is prefetch control, but this processing is executed in the background. The prefetching process is interrupted when the cache use upper limit value 403 in FIG. 5 is reached or when the next input command occurs.

FIG. 10 shows the flow of disk writing and batch writing control. In step 901, a cache area for storing data transferred from the host device is secured. This can be realized by selecting the list indicated by the cache unused list pointer 406. In step 902, it is determined whether the amount of data not written to the disk in its own cache has exceeded N. If it exceeds N, writing to the disk is executed. This is because, in the case of small data, the processing time increases if writing to the disk is performed every time a request is generated.Therefore, the performance is improved by writing to the disk in a certain unit. Processing. Steps 903 and 904 are processing for performing parity generation.

As described above, in the disk array, the parity is generated and stored in the disk to improve the reliability. Generation of parity requires old data, old parity, and new data. In step 903, a search is made to see if these data are in the upper cache. This is because the present invention performs cache control so as not to duplicate data, so that the latest data may exist in the host device. If the data necessary for parity generation does not exist in the upper cache or the own cache, the lower device is accessed to collect data. In step 904, an exclusive OR of the old data, the old parity, and the new data is calculated to generate a parity. In step 905, the process ends by writing the write data (new data) and parity to a predetermined disk.

In FIG. 11, the CCM (1) shown in FIG.
07, 115, 127) indicate what values are stored in the hierarchy level field (401 in FIG. 5). Although the embodiments described so far have been described with a two-level cache, as shown in FIG. 11, the effects of the present invention can be obtained even with three levels or more. Top-level control device 10
01 (1002, 100
3) In the case of a configuration such as the lowest control device (1004, 1005) connected to the intermediate control device (1002, 1003), the hierarchy level field is as follows.

The highest control device 1001 is 0, the intermediate control devices (1002, 1003) are 1, and the lowest control device (10
04, 1005) is set to 1 so that data does not overlap between the layers. So far, the case where the device is operating normally has been described, but there are cases where it is better to change the hierarchical level dynamically. This is when a failure occurs in the device or the cache. If the cache in the highest-level control device 1001 fails,
Next level cache (in FIG. 11, intermediate control device 1
002, 1003) are set as the top cache (hierarchy level field = 0). As a result, the effects of the present invention can be sufficiently obtained even when a failure occurs.

[0046]

According to the present invention, in a disk array composed of hierarchical caches, when transferring data to the upper order, the lower cache controls the data not to be stored in its own cache. As a result, the upper cache stores only the data that is used most frequently, and the lower cache stores data that cannot be stored in the upper cache, thereby improving the cache hit rate. .

[Brief description of the drawings]

FIG. 1 is a diagram showing an overall view of an embodiment of the present invention.

FIG. 2 is a diagram showing an operation outline in the embodiment of the present invention.

FIG. 3 is a diagram showing an effect in the embodiment of the present invention.

FIG. 4 is a diagram showing a microprogram configuration in an embodiment of the present invention.

FIG. 5 is a diagram showing a cache control memory (CCM) structure in the embodiment of the present invention.

FIG. 6 is a diagram showing a command control flow in the embodiment of the present invention.

FIG. 7 is a diagram showing a hierarchical cache control flow in the embodiment of the present invention.

FIG. 8 is a diagram showing a cache management list structure according to the embodiment of the present invention.

FIG. 9 is a diagram showing a disk read & prefetch control flow according to the embodiment of the present invention.

FIG. 10 shows a disc writing &
It is a figure showing a control flow.

FIG. 11 is a diagram showing a hierarchy level in the embodiment of the present invention.

[Explanation of symbols]

 101 host processor, 102 disk array control device, 137, 138 disk device, 103 upper control device, 139, 112 lower control device, 105 upper cache, 124, 130 lower cache, 107, 115, 127 cache control memory.

Claims (4)

[Claims] An upper-level controller connected to a host processor; a plurality of lower-level controllers connected to the upper-level controller; a plurality of disk devices connected to the plurality of lower-level controllers; A hierarchical disk device including a top-level control device and a disk cache provided in the plurality of lower-level control devices, wherein the lower-level control device reads data from the host processor without storing the read data in the disk cache; A hierarchical disk device comprising: means for transferring the read data to a control device; and the uppermost control device stores the read data in a disk cache and transfers the read data to the host processor. 2. A disk array controller for operating a plurality of disk devices in parallel and storing redundant data, the disk array controller being connected to a host processor and being connected to the uppermost controller. A hierarchical disk device including a plurality of lower-level control devices, a plurality of disk devices connected to the plurality of lower-level control devices, and a disk cache provided in the highest-level control device and the plurality of lower-level control devices; When reading data from a processor, it is determined whether or not the hierarchical level is the highest control device from the identifiers indicating the hierarchical levels of the highest control device and the plurality of lower control devices. Hierarchical disk cache characterized by performing control so that data is not stored in the disk cache. Gerhard control method. 3. When a data write request is issued from the host processor, a control device for generating redundant data searches a higher-level control device to determine whether the latest data exists. 3. The hierarchical disk cache control method according to claim 2, wherein the data is transferred from the disk cache of the lower control device to the disk cache of the lower control device. 4. When the cache of the highest-level control device fails, the identifiers of the plurality of lower-level control devices connected to the highest-level control device are changed to identifiers indicating the highest-level control device. 3. The hierarchical disk cache control method according to claim 2, wherein: