JPH1056641A - MPEG decoder - Google Patents

Abstract

(57) Abstract: An MPEG decoder capable of efficiently decoding compressed data having a large amount of information, such as MPEG2 high level, without requiring a large-scale memory capacity and without increasing operation speed. To provide. SOLUTION: Decoding means for decoding variable-length code data into run-length code data, storage means for dividing the run-length code data for each block and storing the same, and a plurality of divisions for each block from the storage means Transforming means for reading in parallel run length code data, decoding run length in parallel, inverse quantizing, inverse discrete cosine transform, and converting into spatial data,
And a motion compensator for generating image data by performing motion compensation prediction processing on the spatial data. The converter performs parallel processing of the variable-length code data in block units and decodes the variable-length code data into image data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a so-called MPEG decoder, and more particularly to an MPEG decoder for decoding compressed data having a large amount of information of a high definition class such as an MPEG2 high level in real time.

[0002]

2. Description of the Related Art In recent years, with the rapid improvement in performance of multimedia equipment, the amount of data to be handled has been dramatically increased. In storing or transmitting this large amount of data, the amount of data is reduced by data compression in order to use hardware resources efficiently.
In particular, for moving image data, the joint working group M
Details on data compression are standardized by the Moving Picture Experts Group (PEG), and a so-called decoding method for decoding encoded (data compressed) data into image data in accordance with the standards standardized by the Joint Working Group MPEG. There is an MPEG decoder.

Hereinafter, a conventional MPEG decoder will be described with reference to FIGS. Here, FIG.
FIG. 6 is a diagram illustrating a configuration of a conventional MPEG decoder, FIG. 6 is a diagram illustrating a hierarchical structure of data targeted by the MPEG decoder, and FIG. 7 is a diagram illustrating a data ratio before and after decoding.

As shown in FIG. 5, a conventional MPEG decoder includes a pre-buffer 1 for fetching a bit stream of variable-length code data obtained by compressing data by an MPEG encoder (not shown) from the outside, and a fetch by the pre-buffer 1. And outputs quantized DCT (Discrete Cosine Transform) coefficients (hereinafter, referred to as "quantized DCT coefficients") and outputs various control information such as motion vectors. The variable-length decoding unit 2 dequantizes the quantized DCT coefficient to obtain the original DCT coefficient (hereinafter simply referred to as “DCT coefficient”).
And an inverse DCT transform unit 4 that performs an inverse discrete cosine transform (hereinafter referred to as “inverse DCT transform”) on the DCT coefficients to generate difference data as spatial data.
A motion compensation unit 5 that generates image data by performing motion compensation prediction processing by adding the difference data to reference image data described below, and a reference image memory 6 that stores the reference image data. I have.

A conventional MPE constructed as described above will be described below.
The operation of the G decoder will be described. First, the pre-buffer 1 fetches a bit stream of variable-length code data from the outside, and the variable-length decoding unit 2 decodes the variable-length code data to obtain various control signals such as motion vectors and quantized DCT.
And coefficients. Here, the variable-length code data captured by the variable-length decoding unit 2 is data whose data amount has been reduced by the run-length encoding, and includes a continuous value “0” (zero run) and a subsequent non-zero value. By assigning a code having a shorter bit length to a symbol having a higher frequency of occurrence to a combination of symbols, the data amount is reduced as a whole.

Next, an inverse quantization unit 3 converts the quantized DCT coefficients generated by the variable length decoding unit 2 into (original) DCT coefficients, and thereafter, an inverse DCT conversion unit 4 performs an inverse DCT transform. ,
Difference data is generated for reference image data described later.
The motion compensation unit 5 adds the difference data to the reference image data read from the reference image memory 6 based on the information such as the motion vector output from the variable length decoding unit 2 to obtain the image data subjected to the motion compensation prediction processing. Generate Here, the reference image data read from the above-described reference image memory 6 is
This is image data that has been transmitted and decoded before this, and has been written to the reference image memory 6, and specifically means an I picture or P picture to be described later.

Here, as shown in FIG. 6, image data compressed in accordance with the standard standardized by MPEG has a hierarchical structure, and the sequence layer is the highest layer, and the GOP (Group Of Pictures) layer, They are a picture layer, a slice layer, a macroblock layer, and a block layer. For details on each of these layers, see the commonly available M
Since it is described in detail in many reference books on PEG, only a brief description of layers mainly related to the present invention, such as a block layer, will be given here.

That is, the lowermost block layer is composed of 8 pixels ×
A macroblock layer is a processing unit of DCT processing composed of data of eight lines of luminance components or chrominance components. The macroblock layer includes four blocks of luminance components Y of 16 pixels × 16 lines and 8 pixels × 8 pixels. This is a motion prediction processing unit composed of color difference components _Cb and _Cr composed of lines. Further, the picture layer is a basic coding processing unit, and includes an I (Intra-coded) picture, a P (Predictive-
coded) picture, B (Bidirectionally predictive-co)
ded) pictures. Of these, all I-pictures are composed of intra (intra-frame coded) blocks and are used to start coding and as entry points. The P picture and the B picture are used for forward inter-frame prediction and bidirectional inter-frame prediction, respectively.

Here, as shown in the upper part of FIG. 7, the composition ratio of each picture in a bit stream is generally a P picture and a B picture which are decoded using previously decoded reference image data. On the other hand, the I picture that is decoded alone occupies several times the data amount, and there is a difference in the data amount of each picture. In the example shown in the figure, for simplification of the description, it is assumed that the data to be decoded is completed with nine pictures, and the I picture is 4,
The P picture is expressed as a ratio of 1 and the B picture as a ratio of 0.5. Actually, this ratio varies, and depends on the specifications of the system, that is, the size of the VBV (Video Buffering Verifier) buffer used for rate control on the encoder side, the data rate of the image, the configuration of the GOP, and the like. The data amount ratio (disparity) of the picture is suppressed so as not to exceed several times.

After decoding the data of each picture, the amount of data corresponding to each picture finally becomes the same as illustrated in the lower part of FIG. Therefore, when trying to output the decoded image data in real time with respect to the input of the bit stream, at least I
The picture is 4 times the average bit rate of the bit stream.
It is necessary to fetch and process data at twice the speed of a P picture, one time for a P picture, and 0.5 times for a B picture. In reality, in consideration of an operation margin and the like, it is necessary to capture and decode data at high speed and completely with more margin.

[0011]

By the way, if the average bit rate of the input bit stream (variable length code data) is about several Mbps (bps; bit per second), decoding processing is performed with an operation clock of about several tens of MHz. It is possible to do. However, in the high-level class of MPEG2, the average bit rate of the bit stream is 20M.
A high-speed operation clock exceeding 100 MHz is required. Therefore, when the circuit constituting the decoding processing system has a restriction on the operation speed, it becomes difficult to perform the decoding process following a high-speed operation clock.

In this case, as a first conceivable measure,
There is a method of increasing the apparent processing speed by parallelizing the decoding processing. However, the variable-length coded data is added to the head of each layer above the slice layer in the bit stream because the head of the next data cannot be known without decoding processing and parallelization is difficult. By detecting the start code, parallel processing is performed in units of slice layers. The start code is a 32-bit code that does not exist in the bit stream, and is added to the head of each layer above the slice layer.

However, if the parallel processing is performed by dividing the slice layer into units, each motion compensator operating in parallel reads out the reference image data from the memory because the motion vector differs for each macroblock. In such a case, there is a possibility that address batting may occur, and motion compensation prediction processing cannot be performed in parallel. To avoid this, a reference image memory in which the same reference image data is written may be provided for each parallel processing and accessed independently, but this is not practical from the viewpoint of memory cost.

Next, as a second conceivable countermeasure, for example, a frame memory is provided further downstream of the motion compensation unit to absorb a time difference in decoding processing according to a difference in data amount of a picture, thereby achieving decoding. There is a method in which the processing speed is apparently increased and, as a result, the data is output at a constant data rate. According to this method, it is necessary to parallelize the processing after the inverse quantization processing of the inverse quantization unit 3, but the processing speed itself of the variable length decoding processing in the variable length decoding unit 2 depends on the average bit rate of the captured bit stream. The rate may be higher than the rate, and it can be realized with a relatively simple circuit configuration. However, in this case, the frame memory provided in the subsequent stage needs to have a storage capacity capable of storing a large amount of image data over several frames, which is not practical from the viewpoint of memory cost.

The present invention has been made in view of such a problem, and does not require a large-scale memory capacity even for compressed data having a large amount of information such as MPEG2 high level, and has an operation speed. MP that can perform efficient and high-speed decoding without having to raise
It is an object to provide an EG decoder.

[0016]

Means for Solving the Problems The present invention has the following arrangement to achieve the above object. That is, claim 1
An MPEG decoder according to the present invention is an MPEG decoder for decoding variable-length code data into image data, a decoding unit for decoding the variable-length code data into run-length code data, and a block for decoding the run-length code data. Storage means for dividing and storing the run length code data in units of blocks, and the run length code data divided in units of blocks are read out in parallel from the storage means, and the run length code data is run length decoded in parallel in units of blocks. Conversion means for converting the spatial data into spatial data by inversely quantizing in parallel and performing inverse discrete cosine transform in parallel, and motion compensating means for generating image data by performing motion compensation prediction processing on the spatial data. I have.

An MPE according to the second aspect of the present invention.
The G decoder is an MPEG decoder that decodes variable-length code data into image data, and stores the variable-length code data in units of one horizontal line of a macroblock and stores the divided data. Decoding variable-length code data in parallel, decoding and storing the variable-length code data into run-length code data in parallel, and decoding and storing the run-length code data from the decoding storage means in units of blocks. A conversion means for reading in parallel the run length code data in parallel in units of blocks, run length decoding in parallel, inverse quantization in parallel, and inverse discrete cosine transform in parallel to convert to spatial data; And motion compensation means for generating image data by performing motion compensation prediction processing.

According to the MPEG decoder according to the first aspect of the present invention, the decoding means decodes the variable length code data into run length code data, and the storage means divides the run length code data into blocks as units. Remember. Next, the conversion unit reads the plurality of run length code data divided in units of blocks from the storage unit in parallel, and decodes the plurality of run length code data in parallel by run length decoding. It is converted into DCT coefficients for each block, and this D
The CT coefficients are inversely quantized in parallel and converted to the original DCT coefficients. Then, the transforming unit converts the original DCT coefficients into a plurality of spatial data by performing inverse discrete cosine transform in parallel, and the compensating unit performs motion compensation prediction processing on the spatial data to generate image data. As described above, the variable-length code data is processed in parallel and decoded into image data.

According to a second aspect of the present invention, there is provided an MPEG decoder for decoding variable length code data into image data, wherein the storage means stores the variable length code data in one horizontal line of a macro block. Divide and store as a unit. The decoding storage means reads a plurality of variable length code data divided for each horizontal line of the macroblock from the storage means, decodes the data into run length code data for each block in parallel, and stores the data. Next, the conversion unit reads the plurality of run length code data divided in units of blocks from the decoding storage unit in parallel, and decodes the plurality of run length code data in parallel by run length decoding. The DCT coefficients are converted into DCT coefficients, and the DCT coefficients are inversely quantized in parallel and converted into original DCT coefficients. Then, the transforming unit converts the original DCT coefficients into a plurality of spatial data by performing an inverse discrete cosine transform in parallel, and the compensating unit performs motion compensation prediction processing on the spatial data to generate image data. As described above, the variable-length code data is processed in parallel and decoded into image data.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, MPEG according to first and second embodiments of the present invention will be described with reference to FIGS.
The decoder will be described. Here, FIG. 1 is a configuration diagram of the MPEG decoder of the first embodiment. FIG.
Represents the sequence of is an explanatory view of the operation, the luminance signal data [Y Data and color difference signal data [C _b data and C _r data. FIG. 3 is a configuration diagram of an MPEG decoder according to a second embodiment of the present invention, and FIG. 4 is an explanatory diagram of its operation.

(First Embodiment) The MPEG decoder according to the first embodiment shown in FIG. 1 is a pre-stage buffer which takes in a bit stream of variable-length code data obtained by compressing data by variable-length coding from the outside. 1 and a variable length decoding unit 2A (decoding means) for decoding variable length code data fetched by the preceding buffer into run length code data and extracting various control signal information such as motion vectors.
A block memory unit BM (storage means) for dividing and storing the run length code data in units of blocks, and reading a plurality of run length code data from the block memory unit BM and storing the plurality of run length code data A run length decoding unit RD (part of the conversion unit) that performs run length decoding in parallel for each block and converts it to a plurality of quantized DCT coefficients for each block, and the plurality of quantized DCT coefficients for each block Multiple DCTs for each block by inverse quantization in parallel
An inverse quantization unit RQ (a part of a conversion unit) for converting into a coefficient,
An inverse DCT transforming unit RT (part of a transforming unit) for transforming the plurality of DCT coefficients into a plurality of differential data for each block as spatial data by performing an inverse discrete cosine transform in parallel on a block basis; A motion compensator 5A (motion compensator) for generating image data by performing motion compensation prediction processing based on the difference data and reference image data read from a reference image memory described later, and various types of signals output by the variable length decoder 2A. Control signal memory SM for storing control signal information
The operation of the run length decoding unit RD and the inverse quantization unit RQ is controlled based on external start pulses in consideration of synchronization with an audio decoder (not shown) and various control signal information read from the control signal memory SM. Together with the motion compensator 5
A control unit CTL that gives motion vector information to A
A common processing unit CM (part of the conversion unit) that collectively performs processing common to each block in the inverse quantization unit; and a reference image memory RM (the motion compensation unit) that stores the reference image data. ).

Here, the block memory unit BM is composed of block memories Y _{1 to} Y ₄ , CB and CR, each corresponding to each block of luminance and color difference. In addition, the run length decoding unit RD stores these block memories Y _{1 to} Y ₄ , C
Run length decoders RD _{1 to} RD ₄ , RD _CB , which read run length code data of a corresponding block from each of B and CR, and run length decode in parallel in block units to output quantized DCT coefficients. RD _CR .

Further, the inverse quantization unit RQ receives the corresponding quantized DCT coefficients from each of the run-length decoders RD _{1 to} RD ₄ , RD _CB , and RD _CR and performs inverse quantization in units of blocks in parallel. It comprises inverse quantizers RQ _{1 to} RQ ₄ , RQ _CB , and RQ _CR which output the converted DCT coefficients. Furthermore, the inverse DCT transform unit RT includes the inverse quantizer RQ
_{1 ~RQ 4,} RQ _CB, parallel inverse DCT inverse DCT transformer RT ₁ outputs the differential data of each block-block as a unit by entering the DCT coefficients of the corresponding block from each RQ _CR It is composed of RT ₄ , RT _CB and RT _CR . Furthermore, the reference image memory unit RM
The run length decoding unit RD, the inverse quantization unit RQ, and the inverse DCT transform unit RT each include a number of memories M _{1 to} M ₆ according to the number of blocks to be processed in parallel.

Hereinafter, the operation of the MPEG decoder having the above-described configuration according to the present embodiment will be described. First, when the variable length decoding unit 2A captures a bit stream of variable length code data via the pre-stage buffer 1, the variable length decoding unit 2A converts the variable length code data into a control signal, quantization matrix data, Alternatively, various control signal information relating to a macroblock such as a motion vector and a macroblock address is extracted and written into the control signal memory SM.

At the same time, the variable-length decoding unit 2A extracts run-length code data including image information from the fetched variable-length code data and distributes the data to the block memories Y _{1 to} Y ₄ , CB, and CR in units of blocks. To go. In the present embodiment, the block memory unit BM is configured by providing a dedicated block memory for each block. However, a flag is attached so that 0 run of run length code data and the subsequent level can be identified in block units. Then, the run length code data for each block may be continuously stored in a continuous address space of one memory. In this case, a dedicated block memory is provided for each block. There is no need to provide them.

Here, when the variable-length decoding unit 2A sorts the run-length code data into the block memories Y _{1 to} Y ₄ , CB, and CR, CBP, which is information on macro blocks, is used.
If (Coded Block Pattern) indicates that data does not exist in a specific block in the macroblock (all 0), 0 run is set to 64 (total number of pixels in the block), or A flag indicating that the block does not exist is attached and written in the block memory of the block. A start flag is added to the start of a block, or an end-of-block flag is added to the end of a block, so that a block break can be identified at the time of reading.

Next, the control section CTL starts operation by an external start pulse in consideration of synchronization with an audio decoder (not shown) or the like. This control section C
The TL fetches various control signal information from the control signal memory SM, and controls the run length decoding unit RD and the inverse quantization unit RQ on a macroblock basis or on a picture basis based on the various control signal information.

That is, each of the run length decoders RD _{1 to} RD ₄ , RD _CB , and RD _CR constituting the run length decoding unit RD is triggered by a start pulse for each macro block from the control unit CTL as a trigger. Memory Y ₁
To Y _4, CB, starts reading of the run-length code data from the CR, the run-length code data and run length decoding while accessing the block memory Y ₁ ~Y _4, CB, CR until it detects a delimiter of the block, Quantization D per block
Output CT coefficients.

When a block break is detected,
The run length decoders RD _{1 to} RD ₄ , RD _CB , and RD _CR stop reading from the block memories Y _{1 to} Y ₄ , CB, and CR, and output 0 values until the next start pulse is input. to continue. Even when the control unit CTL determines that the address of the macroblock is skipped based on the information from the control signal memory SM, the control unit CTL similarly outputs the value 0 during the period in which the macroblock address is skipped. .

Thereafter, the processing up to the motion compensation section 5A is performed in parallel on a block basis. That is, the run length decoding unit R
Quantized DCT coefficients for each block obtained by parallel run length decoding by D are supplied to an inverse quantization unit RQ, and inverse quantizers RQ _{1 to} RQ ₄ , R constituting the inverse quantization unit RQ
Each of Q _CB and RQ _CR converts the quantized DCT coefficient of the corresponding block into an (original) DCT coefficient. In the inverse quantization unit RQ, generally, data is rearranged and a multiplication process with a quantization matrix or the like is performed to obtain a DCT coefficient. However, a value for multiplying data is calculated using a quantization matrix or the like. The processes common to the blocks are collectively performed by the common processing unit CM that operates under the control of the control unit CTL.

Next, the DCT coefficients for each block obtained by the inverse quantization unit RQ are supplied to an inverse DCT transform unit RT, and the inverse DCT transform units RT _{1 to} RT ₄ , RT _{4 to} RT ₄ constituting the inverse DCT transform unit RT Each of RT _CB and RT _CR converts the DCT coefficient of the corresponding block into difference data as spatial data in parallel on a block basis. This difference data represents a difference from the image data decoded before and stored in the reference image memory RM. In the inverse DCT transform section RT, when generating image difference data from DCT coefficients, the control section C
Field DCT and frame DCT given from TL
Are rearranged on the basis of a selection signal for selecting (i) and (ii) and output to the subsequent motion compensation unit 5A.

Then, the motion compensation unit 5A adds the reference image data read from the reference image memory RM to the difference data of each block constituting the macroblock input from the inverse DCT transform unit RT to perform the motion compensation prediction process. After that, the image data of each block is rearranged and connected, and Y
The image data configured as the / C component signal is output at high speed. As described above, the motion compensation unit 5A captures the difference data of each block constituting the macroblock, and performs the motion compensation prediction process on a macroblock basis.

Here, when the motion compensation unit 5A adds the reference image data to the difference data, if the difference data is an intra block, the motion compensation unit 5A adds 0 to the difference data. When the image data obtained by adding the difference data and the reference image data is an I picture or a P picture, the image data of the I picture or the P picture of each block is stored in a memory constituting the reference image memory RM. The content is divided and written into M _{1 to} M ₆ to update the contents of the reference image memory RM. That is, the reference image memory RM divides and stores the I-picture or P-picture image data in units of one block.

When updating the contents of the reference image memory RM, for example, as shown in FIG. 2, the image data in the block is divided and written into the memories M _{1 to} M ₆ in units of pixels in parallel with the block (FIG. 2). of the numbers 1 to 6, corresponding to the memory M ₁ ~M _6). At this time, the address to be accessed is stored in the memory M
It is the same in each of the ₁ ~M _6. As a result, when data is read out from the memories M _{1 to} M _{6 in a} block parallel manner, as shown in the figure, since the read data corresponding to each block is always in different memories, it is necessary to avoid memory access batting. Can be.

As described above, M of the first embodiment
According to the PEG decoder, decoding processing is performed in a block parallel manner in a macroblock having the same motion vector, and image data in the block is divided and written into the reference image memory unit RM. It is possible to read the reference image data of each block from the reference image memory RM while avoiding butting.

The processing time difference caused by the data amount difference is absorbed by the block memory during the variable length decoding process.
A decoder can be configured. Further, since the decoding process is performed in units of blocks in parallel, a control signal for each block can be generated by sharing a circuit portion for generating a common control signal within a macroblock.

(Regarding the Second Embodiment) Next, an MPEG decoder according to a second embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG. The second described below
The difference between the MPEG decoder of this embodiment and the MPEG decoder of the first embodiment is that
The G decoder converts the variable-length code data into one macro block.
It is divided into horizontal lines, and the run length decoding processing and subsequent steps are performed in parallel in block units as in the first embodiment.

That is, the MPE of the second embodiment shown in FIG.
The G decoder replaces the variable length decoding unit 2A and the block memory unit BM that constitute the MPEG decoder shown in FIG.
A picture information extraction unit for extracting picture information such as various control signals and quantization matrix data from the variable length code data taken into the preceding buffer 1 and extracting the variable length code data for each horizontal line of a macroblock; A macroblock line memory BLM (storage means) for dividing the variable-length code data extracted by the picture information extraction unit in units of one horizontal line of a macroblock and storing the divided data, and the divided macroblock line memory BLM. A variable-length decoding processing unit VLC (decoding) that reads a plurality of variable-length code data, decodes and stores the plurality of variable-length code data in parallel into run-length code data “per block”, and outputs macroblock information. Storage means)
And a control signal memory SM shown in FIG.
A picture control signal memory P for storing the picture information instead of the control unit CTL and the common processing unit CM
M, and a control unit CTLa that controls operations of the run length decoding unit RD and the inverse quantization unit RQ based on the picture information and the macroblock information, and outputs motion vector information and the like to the motion compensation unit 5A. Have been.

Here, the macro block line memory BL
M is composed of line memories YL _{1 to} YL ₆ for storing variable-length code data for each horizontal line of the macro block. The variable-length decoding processing unit VLC reads the corresponding variable-length code data from each of the line memories YL _{1 to} YL ₆ , and performs variable-length decoding in parallel with one horizontal line of the macroblock as a unit to execute the run-length code. a variable length decoder VL ₁ ~VL ₆ for generating data, from the macro block memory YB ₁ ~YB ₆ Tokyo for storing the run-length code data of each horizontal line of the corresponding macroblock are connected to these latter stage It is configured. Incidentally, the line memory YL ₁ stores data of one horizontal line of the macroblock as a unit ～YL ₆ is block memory Y ₁ to Y ₄ which stores data in units of blocks shown in FIG. 1 described above,
The storage capacity is much smaller than CB and CR.

Hereinafter, the operation of the MPEG decoder thus configured according to the present embodiment will be described. First, a decoding operation is started by an external start pulse in consideration of synchronization with an audio decoder or the like (not shown), and a bit stream of variable-length code data is taken into the picture information extraction unit PE via the pre-stage buffer 1. Picture information extraction unit P
E extracts picture information such as a control signal relating to the picture and quantization matrix data and writes the extracted picture information into the picture control signal memory PM.

At the same time, the picture information extraction unit PE
Detects the start code of the slice layer from the variable-length code data, allocates the bit stream of the slice layer and below to each macroblock horizontal line (in units of one horizontal line of the macroblock), and stores the macroblock line memory BLM in the macroblock line memory BLM. Six line memories YL _{1 to} Y to configure
Sequentially writes to L _6. Next, the variable length decoding processing unit V
The variable length decoders VL _{1 to} VL ₆ constituting the preceding stage of the LC are 6
One macro when writing data to the block line memory YL ₁ ~YL ₆ is completed, starts the variable length decoding in parallel of these units of one horizontal line of the appropriately read by the macroblock.

The parallel processing of each variable-length decoding in the variable-length decoding processing unit VLC is performed in the state of run-length code data, as in the first embodiment, and the processing result is stored in the macroblock memory YB in the subsequent stage. written in each of the _{1 ~YB 6.} The information on the picture layer and above is common to each macroblock line, and is written in the picture control signal memory PM.

Here, in the case of the above-described first embodiment, the control unit starts the decoding operation with an external start pulse in consideration of synchronization with an audio decoder or the like as a trigger. Form of line memory YL
_{Since 1 to} YL ₆ have a much smaller storage capacity than the block memories Y _{1 to} Y ₄ , CB, and CR of the first embodiment shown in FIG. 1, they cannot store picture-based data. Therefore, the operation cannot be triggered by a start pulse output from an external device (not shown) for each picture.

For this reason, the control of the start of the decoding operation is performed when the bit stream is fetched from the preceding buffer 1 into the picture information extraction unit PE. That is, the control unit CTLa
Starts operation when the line memory YL ₁ ~YL ₆ is a state filled with some data, incorporating the various control signal information from the memory PM for picture control signal, a picture unit on the basis of the various control signal information Controls the start of the decoding operation of the run length decoding unit RD and the like.

When the decoding operation is started in this way, the control unit CTLa sends the macro block memory YB ₁
Incorporating in turn the macroblock information added to ~YB _6. Then, based on this information, the operation after the run length decoding unit RD is controlled, and the run length code data respectively stored in the block memories YB _{1 to} YB ₆ are sequentially taken out, and the same as in the first embodiment described above. Is subjected to parallel processing in units of blocks.

Here, the parallel processing after the run length decoding unit RD is basically the same as that of the first embodiment, but the processing order of the macro blocks is different. That is, when a macroblock is skipped, it is necessary to secure information such as a motion vector during the skip period. Therefore, the control unit CTLa provides a buffer for temporarily storing macroblock information for six macroblocks. A memory (not shown) is provided. Then, as illustrated in FIG. 4, the processing order for the data of six macroblocks once stored in the buffer memory of the control unit CTLa is
First, the operations after the run length decoding unit RD are controlled so that decoding processing is sequentially performed in the vertical direction in units of macroblocks in accordance with the order of allocation to the macroblock line memories BLM.

In this case, the processing order of the macroblocks is similarly different in the motion compensating unit 5A, but the prediction processing is performed based on the address information (macroblock information) of the macroblock, whereby the above-described first embodiment is performed. As in the case of (1), it is possible to avoid the batting of the address of the reference image data. Finally, the motion compensating unit 5A rearranges and connects the order of the image data obtained by performing the parallel processing in units of blocks, and outputs the image data configured as the Y / C component signal at a high speed.

[0048]

As is apparent from the above description, according to the present invention, the following effects can be obtained. That is, according to the first aspect of the present invention, a plurality of units of variable length code data in units of blocks are configured to be subjected to run length decoding, inverse quantization, and inverse discrete cosine transform in parallel. The processing speed of the variable-length decoding unit (decoding means) should be at least equal to or higher than the average bit rate of the bit stream of variable-length code data, and a large amount of compressed data can be processed in real time without increasing the operation speed of the variable-length decoding unit. Can be decrypted.

According to the second aspect of the present invention, in addition to the configuration of the first aspect, variable-length code data is configured to be variable-length decoded in parallel in units of macroblocks. In addition to the effects obtained by the first aspect of the present invention, the variable-length decoding processing speed can be increased. As a result, the memory capacity required in the variable length decoding process can be significantly reduced.

Therefore, according to the first and second aspects of the present invention, even if the compressed data has a large amount of information such as MPEG2 high level, the operation speed is not increased and the memory capacity is small. Thus, it is possible to realize an MPEG decoder that can efficiently perform decoding processing in real time.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an MPEG decoder according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of an operation of the MPEG decoder according to the first embodiment of the present invention.

FIG. 3 is a configuration diagram of an MPEG decoder according to a second embodiment of the present invention.

FIG. 4 is an explanatory diagram of an operation of an MPEG decoder according to a second embodiment of the present invention.

FIG. 5 is a configuration diagram of a conventional MPEG decoder.

FIG. 6 is an explanatory diagram for explaining a hierarchical structure of variable-length code data to be decoded by an MPEG decoder.

FIG. 7 is a diagram illustrating a data ratio of a picture layer of variable-length code data to be decoded by an MPEG decoder.

[Description of Code] 1 Pre-stage buffer 2A Variable length decoding unit 5A Motion compensation unit BM block memory unit BLM macro block line memory unit CM common processing unit CTL, CTLa control unit PE Picture information extraction unit PM Picture control signal memory RD Run length Decoding unit RM Reference image memory unit RQ Inverse quantization unit RT Inverse DCT transformation unit SM Control signal memory VLC Variable length decoding processing unit

Claims (2)

[Claims] An MPEG decoder for decoding variable-length code data into image data, decoding means for decoding the variable-length code data into run-length code data, and dividing the run-length code data into blocks. Storage means for reading and storing the divided run length code data from the storage means in units of blocks in parallel, and run length decoding of the run length code data in units of blocks in parallel and inversely in parallel An MPE comprising: a conversion unit for quantizing and performing inverse discrete cosine transform in parallel to convert to spatial data; and a motion compensation unit for generating image data by performing motion compensation prediction processing on the spatial data.
G decoder. 2. An MPEG decoder for decoding variable-length code data into image data, wherein said storage means divides and stores said variable-length code data in units of one horizontal line of a macroblock. Decoding storage means for reading the divided variable-length code data in parallel, decoding the variable-length code data into run-length code data in parallel, and storing the run-length code data in blocks; Conversion means for reading in parallel as a unit, and run length decoding the run length code data in units of blocks in parallel, inversely quantizing in parallel, and inverse discrete cosine transform in parallel to convert to spatial data; A motion compensation means for generating image data by performing motion compensation prediction processing on data.
G decoder.