JPH1056020A - Semiconductor device with bump electrode - Google Patents
Semiconductor device with bump electrodeInfo
- Publication number
- JPH1056020A JPH1056020A JP9139196A JP13919697A JPH1056020A JP H1056020 A JPH1056020 A JP H1056020A JP 9139196 A JP9139196 A JP 9139196A JP 13919697 A JP13919697 A JP 13919697A JP H1056020 A JPH1056020 A JP H1056020A
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor device
- bump electrode
- protective film
- polyimide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 230000001681 protective effect Effects 0.000 claims abstract description 35
- 239000004642 Polyimide Substances 0.000 claims abstract description 17
- 229920001721 polyimide Polymers 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims description 5
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 239000010408 film Substances 0.000 abstract description 72
- 239000002344 surface layer Substances 0.000 abstract description 15
- 239000010409 thin film Substances 0.000 abstract description 12
- 238000001312 dry etching Methods 0.000 abstract description 11
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052737 gold Inorganic materials 0.000 abstract description 10
- 239000010931 gold Substances 0.000 abstract description 10
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Substances [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052786 argon Inorganic materials 0.000 abstract description 7
- -1 argon ions Chemical class 0.000 abstract description 6
- 230000002411 adverse Effects 0.000 abstract description 5
- 230000006866 deterioration Effects 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 3
- 239000001301 oxygen Substances 0.000 abstract description 3
- 229910052760 oxygen Inorganic materials 0.000 abstract description 3
- 238000002161 passivation Methods 0.000 description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000005530 etching Methods 0.000 description 4
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 239000003960 organic solvent Substances 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- OCJBOOLMMGQPQU-UHFFFAOYSA-N 1,4-dichlorobenzene Chemical compound ClC1=CC=C(Cl)C=C1 OCJBOOLMMGQPQU-UHFFFAOYSA-N 0.000 description 1
- ZNQVEEAIQZEUHB-UHFFFAOYSA-N 2-ethoxyethanol Chemical compound CCOCCO ZNQVEEAIQZEUHB-UHFFFAOYSA-N 0.000 description 1
- ZCYVEMRRCGMTRW-UHFFFAOYSA-N 7553-56-2 Chemical compound [I] ZCYVEMRRCGMTRW-UHFFFAOYSA-N 0.000 description 1
- CTQNGGLPUBDAKN-UHFFFAOYSA-N O-Xylene Chemical compound CC1=CC=CC=C1C CTQNGGLPUBDAKN-UHFFFAOYSA-N 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229940117389 dichlorobenzene Drugs 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- QUCZBHXJAUTYHE-UHFFFAOYSA-N gold Chemical compound [Au].[Au] QUCZBHXJAUTYHE-UHFFFAOYSA-N 0.000 description 1
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052740 iodine Inorganic materials 0.000 description 1
- 239000011630 iodine Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
- 239000008096 xylene Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Wire Bonding (AREA)
Abstract
(57)【要約】
【目的】 バンプ電極を備えた半導体装置（ＩＣチッ
プ）の表面にポリイミドからなる保護膜が形成されたも
のの製造中に、保護膜の表面層が変質しても、この変質
による悪影響が生じないようにする。
【構成】 中間接続膜形成用膜９および金薄膜形成用薄
膜１０を形成する前に、接続用電極４の表面に形成され
た自然酸化膜を除去するためにアルゴンイオンによるド
ライエッチングを行う。この場合、ポリイミドからなる
保護膜７の表面層がアルゴンイオンの影響を受けて変質
する。そして、バンプ電極１４、金薄膜１０ａおよび中
間接続膜９ａを形成した後に、保護膜７の表面層を酸素
プラズマによるドライエッチングにより除去する。
(57) [Summary] [Object] Even if a surface layer of a protective film is deteriorated during the manufacturing of a semiconductor device (IC chip) having a bump electrode on which a protective film made of polyimide is formed, the deterioration occurs To prevent the adverse effects of Before forming an intermediate connection film forming film and a gold thin film forming thin film, dry etching with argon ions is performed to remove a natural oxide film formed on the surface of the connection electrode. In this case, the surface layer of the protective film 7 made of polyimide is altered under the influence of argon ions. Then, after forming the bump electrode 14, the thin gold film 10a and the intermediate connection film 9a, the surface layer of the protective film 7 is removed by dry etching using oxygen plasma.
Description
【０００１】[0001]
【産業上の利用分野】この発明はバンプ電極を備えた半
導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a bump electrode.
【０００２】[0002]
【従来の技術】例えばＴＡＢ方式と呼ばれる半導体装置
（ＩＣチップ）の実装技術では、半導体装置をＴＡＢテ
ープ上に搭載している。この場合、半導体装置に設けら
れたバンプ電極をＴＡＢテープのフィンガリード（イン
ナリード）に金すず共晶法や金金熱圧着法等によるボン
ディングによって接続している。2. Description of the Related Art For example, in a semiconductor device (IC chip) mounting technique called a TAB method, a semiconductor device is mounted on a TAB tape. In this case, the bump electrodes provided on the semiconductor device are connected to the finger leads (inner leads) of the TAB tape by bonding using gold-tin eutectic method, gold-gold thermocompression bonding method, or the like.
【０００３】ところで、半導体装置は、一般に、シリコ
ンウエハ（半導体装置本体）上に形成されたパッシベー
ション膜に形成された開口部を介してシリコンウエハ上
に形成された接続用電極が露出され、この接続用電極上
にバンプ電極が形成された構造となっている。そして、
このような構造の半導体装置を製造する場合、バンプ電
極を形成する前に、アルミニウムやアルミニウム合金か
らなる接続用電極の表面に形成された自然酸化膜をアル
ゴンイオンによるドライエッチングにより除去してい
る。In a semiconductor device, a connection electrode formed on a silicon wafer is generally exposed through an opening formed in a passivation film formed on the silicon wafer (semiconductor device body). It has a structure in which a bump electrode is formed on an electrode for use. And
When manufacturing a semiconductor device having such a structure, a natural oxide film formed on the surface of a connection electrode made of aluminum or an aluminum alloy is removed by dry etching with argon ions before forming a bump electrode.
【０００４】[0004]
【発明が解決しようとする課題】ところで、最近では、
半導体装置の表面をより一層保護するために、窒化シリ
コン等からなるパッシベーション膜の上面にポリイミド
からなる保護膜を形成した構造のものが試みられてい
る。しかるに、このような構造の半導体装置を製造する
場合、接続用電極の表面に形成された自然酸化膜を除去
するためにアルゴンイオンによるドライエッチングを行
うと、ポリイミドからなる保護膜の表面層がアルゴンイ
オンの影響を受けて変質し、保護膜の絶縁抵抗が低下
し、最終的にはリーク不良を生じてしまうことがあると
いう問題があった。この発明の目的は、ポリイミドから
なる保護膜の表面層が変質しても、この変質による悪影
響が生じないようにすることのできるバンプ電極を備え
た半導体装置を提供することにある。By the way, recently,
In order to further protect the surface of the semiconductor device, a structure in which a protective film made of polyimide is formed on the upper surface of a passivation film made of silicon nitride or the like has been tried. However, when a semiconductor device having such a structure is manufactured, dry etching with argon ions is performed to remove a natural oxide film formed on the surface of the connection electrode, and the surface layer of the polyimide protective film becomes argon. There is a problem that the material is deteriorated under the influence of ions, the insulation resistance of the protective film is reduced, and ultimately a leak failure occurs. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a bump electrode capable of preventing adverse effects due to deterioration of a surface layer of a protective film made of polyimide.
【０００５】[0005]
【課題を解決するための手段】この発明は、半導体装置
本体上に形成された接続用電極とバンプ電極との周縁部
の間に無機絶縁膜とポリイミドからなる保護膜が介在さ
れ、前記ポリイミドからなる保護膜の前記バンプ電極か
ら露出した領域において少なくともその表面が除去され
ているものである。According to the present invention, a protective film made of an inorganic insulating film and a polyimide is interposed between peripheral portions of a connection electrode and a bump electrode formed on a semiconductor device main body. At least the surface of a region of the protective film exposed from the bump electrode is removed.
【０００６】[0006]
【作用】この発明によれば、接続用電極の表面に形成さ
れた自然酸化膜を除去するためのドライエッチングによ
りポリイミドからなる保護膜の表面層が変質しても、こ
のポリイミドからなる保護膜の表面層を除去しているの
で、保護膜の表面層の変質による悪影響が生じないよう
にすることができる。According to the present invention, even if the surface layer of the protective film made of polyimide is altered by dry etching for removing the natural oxide film formed on the surface of the connection electrode, the protective film made of polyimide can be used. Since the surface layer is removed, it is possible to prevent adverse effects due to deterioration of the surface layer of the protective film.
【０００７】[0007]
【実施例】図１（Ａ）〜（Ｅ）はそれぞれこの発明の一
実施例における半導体装置の各製造工程を示したもので
ある。そこで、これらの図を順に参照しながら、この実
施例の半導体装置の構造についてその製造方法と併せ説
明する。1A to 1E show respective steps of manufacturing a semiconductor device according to an embodiment of the present invention. Therefore, the structure of the semiconductor device of this embodiment will be described together with its manufacturing method with reference to these drawings in order.
【０００８】まず、図１（Ａ）に示すように、シリコン
ウエハ（半導体装置本体）１の上面にゲート電極等の内
部電極２および酸化シリコン等からなる絶縁膜３を形成
し、絶縁膜３の上面にアルミニウムやアルミニウム合金
からなる接続用電極４を内部電極２と接続させて形成す
る。次に、接続用電極４を含む絶縁膜３の上面全体に窒
化シリコン等からなるパッシベーション膜（無機絶縁
膜）５を形成した後、パッシベーション膜５の所定の個
所にエッチングにより開口部６を形成することにより、
接続用電極４の周縁部および絶縁膜３の上面にパッシベ
ーション膜５を残存させるとともに、パッシベーション
膜５の開口部６を介して接続用電極４の中央部を露出さ
せる。次に、接続用電極４を含むパッシベーション膜５
の上面全体にポリイミドからなる保護膜７を厚さ１〜５
μｍ程度に形成した後、保護膜７の所定の個所にエッチ
ングにより開口部８を形成することにより、パッシベー
ション膜５の開口部６の周囲を除く上面に保護膜７を残
存させるとともに、保護膜７の開口部８を介して接続用
電極４の中央部を露出させる。First, as shown in FIG. 1A, an internal electrode 2 such as a gate electrode and an insulating film 3 made of silicon oxide or the like are formed on the upper surface of a silicon wafer (semiconductor device body) 1. A connection electrode 4 made of aluminum or an aluminum alloy is formed on the upper surface so as to be connected to the internal electrode 2. Next, after a passivation film (inorganic insulating film) 5 made of silicon nitride or the like is formed on the entire upper surface of the insulating film 3 including the connection electrode 4, an opening 6 is formed in a predetermined portion of the passivation film 5 by etching. By doing
The passivation film 5 is left on the periphery of the connection electrode 4 and the upper surface of the insulating film 3, and the center of the connection electrode 4 is exposed through the opening 6 of the passivation film 5. Next, passivation film 5 including connection electrode 4
Protective film 7 made of polyimide over the entire upper surface of
After forming the protective film 7 to a thickness of about μm, an opening 8 is formed at a predetermined location of the protective film 7 by etching, so that the protective film 7 remains on the upper surface of the passivation film 5 excluding the periphery of the opening 6 and the protective film 7 is formed. The central portion of the connection electrode 4 is exposed through the opening 8 of FIG.
【０００９】次に、接続用電極４の表面に形成された自
然酸化膜（図示せず）を除去するためにアルゴンイオン
によるドライエッチングを行う。この場合、ポリイミド
からなる保護膜７の表面層がアルゴンイオンの影響を受
けて変質し、厚さ１０００〜２０００Å程度の変質層
（図示せず）が形成される。次に、接続用電極４の表面
酸化を防止するためにシリコンウエハ１を真空中で次工
程に移動させ、そしてチタン−タングステン等の合金お
よび金をこの順で蒸着またはスパッタリングすることに
より、上面全体に中間接続膜形成用膜９および金薄膜形
成用薄膜１０をそれぞれ数千Å程度の厚さに形成する。Next, dry etching using argon ions is performed to remove a natural oxide film (not shown) formed on the surface of the connection electrode 4. In this case, the surface layer of the protective film 7 made of polyimide is deteriorated under the influence of argon ions, and a deteriorated layer (not shown) having a thickness of about 1000 to 2000 ° is formed. Next, in order to prevent surface oxidation of the connection electrode 4, the silicon wafer 1 is moved to the next step in a vacuum, and an alloy such as titanium-tungsten and gold are vapor-deposited or sputtered in this order, so that the entire upper surface is formed. Next, a film 9 for forming an intermediate connection film and a thin film 10 for forming a gold thin film are each formed to a thickness of about several thousand Å.
【００１０】次に、図１（Ｂ）に示すように、金薄膜形
成用薄膜１０の上面に、フォトレジスト液を滴下してス
ピンコーティングすることにより、フォトレジスト膜１
１を膜厚が２０〜３０μｍ程度となるように比較的厚く
形成する。この場合、フォトレジスト膜１１の膜厚を２
０〜３０μｍ程度と比較的厚くするために、フォトレジ
スト液として粘度が数百〜千数百ＣＰＳ（センチポイ
ズ）で通常のスピンコーティングのものよりも数倍ない
し数十倍高いもの（例えば東京応化工業（株）製のＢＭ
Ｒ１０００）を使用し、スピンコーティング時の回転速
度を数百ｒｐｍとする。Next, as shown in FIG. 1B, a photoresist solution is dropped on the upper surface of the thin film 10 for forming a gold thin film and spin-coated to form a photoresist film 1.
1 is formed relatively thick so that the film thickness is about 20 to 30 μm. In this case, the thickness of the photoresist film 11 is 2
In order to make it relatively thick as about 0 to 30 μm, a photoresist liquid having a viscosity of several hundreds to several hundreds CPS (centipoise) which is several times to several tens times higher than that of ordinary spin coating (for example, Tokyo Ohka Kogyo BM manufactured by
R1000), and the rotation speed during spin coating is set to several hundred rpm.
【００１１】次に、所定のマスク１２を用いてフォトレ
ジスト膜１１を露光し、次いで現像すると、図１（Ｃ）
に示すように、フォトレジスト膜１１の所定の個所つま
り保護膜７の開口部８およびその周囲に対応する部分に
開口部１３が形成される。この場合、現像液としてはキ
シレンを主成分とする有機溶剤（例えば東京応化工業
（株）製のＣ−３）を用いる。次に、開口部１３内に金
を電解メッキすることにより、図１（Ｄ）に示すよう
に、開口部１３内の金薄膜形成用薄膜１０の上面にバン
プ電極１４を形成する。この場合、バンプ電極１４の上
面を平坦とするために、バンプ電極１４の厚さを２０〜
３０μｍ程度とし、その上面がフォトレジスト膜１１の
上面から突出しないようにする。この後、フォトレジス
ト膜１１をエチルセルソルブ、ジクロルベンゼンを主成
分とする有機溶剤（例えば東京応化工業（株）製の剥離
液ＳＰ）を用いて剥離するNext, the photoresist film 11 is exposed to light using a predetermined mask 12 and then developed, so that FIG.
As shown in (1), an opening 13 is formed at a predetermined portion of the photoresist film 11, that is, at a portion corresponding to the opening 8 of the protective film 7 and its periphery. In this case, an organic solvent containing xylene as a main component (for example, C-3 manufactured by Tokyo Ohka Kogyo Co., Ltd.) is used as a developer. Next, as shown in FIG. 1D, a bump electrode 14 is formed on the upper surface of the thin film 10 for forming a gold thin film in the opening 13 by electroplating gold in the opening 13. In this case, in order to make the upper surface of the bump electrode 14 flat, the thickness of the bump electrode 14 is set to 20 to
The thickness is about 30 μm so that the upper surface does not protrude from the upper surface of the photoresist film 11. Thereafter, the photoresist film 11 is stripped using an ethyl cellosolve or an organic solvent containing dichlorobenzene as a main component (eg, stripping solution SP manufactured by Tokyo Ohka Kogyo Co., Ltd.).
【００１２】次に、図１（Ｅ）に示すように、バンプ電
極１４をマスクとして金薄膜形成用薄膜１０の不要な部
分をヨウ素系のエッチング液でエッチングして除去する
と、残存する金薄膜形成用薄膜１０によって金薄膜１０
ａが形成される。次に、再びバンプ電極１４をマスクと
して中間接続膜形成用膜９の不要な部分をドライエッチ
ングして除去すると、残存する中間接続膜形成用膜９に
よって中間接続膜９ａが形成される。次に、酸素プラズ
マによるドライエッチングを行い、保護膜１４の表面の
変質層を除去する。この場合、マイクロ波アッシャー
（例えばキャノン（株）製のＭＡＳ８００）を用い、周
波数２４５０ＭＨｚ、出力５００Ｗ、プレート温度１５
０℃、酸素流量１５０ＳＣＣＭ、圧力０．８ｍｍＴｏｒ
ｒ、処理時間２０〜４０秒としたところ、ポリイミドか
らなる保護膜１４の表面が２０００〜５０００Å程度除
去された。なお、ＲＦアッシャー等を用いてもよく、ま
たオゾン処理等を行ってもよい。Next, as shown in FIG. 1 (E), unnecessary portions of the thin film 10 for forming a gold thin film are removed by etching with an iodine-based etchant using the bump electrode 14 as a mask. Gold thin film 10
a is formed. Next, unnecessary portions of the intermediate connection film forming film 9 are again removed by dry etching using the bump electrode 14 as a mask, and the intermediate connection film 9a is formed by the remaining intermediate connection film forming film 9. Next, dry etching using oxygen plasma is performed to remove the altered layer on the surface of the protective film 14. In this case, using a microwave asher (for example, MAS800 manufactured by Canon Inc.), a frequency of 2450 MHz, an output of 500 W, and a plate temperature of 15
0 ° C., oxygen flow rate 150 SCCM, pressure 0.8 mmTorr
When the treatment time was set to 20 to 40 seconds, the surface of the protective film 14 made of polyimide was removed at about 2000 to 5000 °. Note that an RF asher or the like may be used, or ozone treatment or the like may be performed.
【００１３】このようにして得られた半導体装置では、
接続用電極４の表面に形成された自然酸化膜を除去する
ためのドライエッチングにより保護膜７の表面層が変質
しても、バンプ電極１４、金薄膜１０ａおよび中間接続
膜９ａを形成した後に、保護膜７の表面層をドライエッ
チングにより除去しているので、保護膜７の表面層の変
質による悪影響が生じないようにすることができる。In the semiconductor device thus obtained,
Even if the surface layer of the protective film 7 is altered by dry etching for removing the natural oxide film formed on the surface of the connection electrode 4, after forming the bump electrode 14, the gold thin film 10a, and the intermediate connection film 9a, Since the surface layer of the protective film 7 is removed by dry etching, it is possible to prevent adverse effects due to deterioration of the surface layer of the protective film 7.
【００１４】次に、図２（Ａ）および（Ｂ）を参照し
て、上記のように構成された半導体装置のバンプ電極を
ＴＡＢテープのフィンガリードに接続する場合について
説明する。まず、上述した処理工程を経た後シリコンウ
エハ１はダイシングにより切断され、複数の半導体装置
２１に分割される。ここで、１つの半導体装置２１には
上述したバンプ電極１４が複数配列されている。一方、
ＴＡＢテープ２２の複数のフィンガリード２３は、表面
に半田２３ａがメッキされた銅箔２３ｂをベーステープ
２４上にラミネートした後エッチングして所定の形状に
パターン形成したものからなり、ベーステープ２４に形
成されたデバイスホール２５内に突出されている。そし
て、半導体装置２１をデバイスホール２５内に配置し、
各バンプ電極１４をそれぞれ対応するフィンガリード２
３にボンディングして接続する。なお、半導体装置２１
のバンプ電極１４をＴＡＢテープ２２のフィンガリード
２３に接続した後は、半導体装置２１上に図示しない保
護用レジンをポッティングして、このポッティングした
保護用レジンによって半導体装置２１を覆って保護し、
この後図２（Ａ）において一点鎖線で示す部分で切断す
ることになる。Next, with reference to FIGS. 2A and 2B, a description will be given of a case where the bump electrodes of the semiconductor device configured as described above are connected to finger leads of a TAB tape. First, after passing through the above-described processing steps, the silicon wafer 1 is cut by dicing and divided into a plurality of semiconductor devices 21. Here, a plurality of bump electrodes 14 described above are arranged in one semiconductor device 21. on the other hand,
The plurality of finger leads 23 of the TAB tape 22 are formed by laminating a copper foil 23b having a surface plated with solder 23a on a base tape 24 and then etching and patterning the copper foil 23b into a predetermined shape. Projecting into the device hole 25 formed. Then, the semiconductor device 21 is arranged in the device hole 25,
Finger bumps 2 corresponding to each bump electrode 14
3 and connected. The semiconductor device 21
After the bump electrodes 14 are connected to the finger leads 23 of the TAB tape 22, a protective resin (not shown) is potted on the semiconductor device 21, and the semiconductor device 21 is covered and protected by the potted protective resin.
Thereafter, cutting is performed at a portion indicated by a dashed line in FIG.
【００１５】次に、図３はこの発明を適用した半導体装
置の変形例を示したものである。この変形例の半導体装
置では、図１（Ｅ）に示すものと比較して、保護膜８の
開口部８がパッシベーション膜５の開口部６よりも小さ
くなっている。FIG. 3 shows a modification of the semiconductor device to which the present invention is applied. In the semiconductor device of this modification, the opening 8 of the protective film 8 is smaller than the opening 6 of the passivation film 5 as compared with the semiconductor device shown in FIG.
【００１６】[0016]
【発明の効果】以上説明したように、この発明によれ
ば、接続用電極の表面に形成された自然酸化膜を除去す
るためのドライエッチングによりポリイミドからなる保
護膜の表面層が変質しても、このポリイミドからなる保
護膜の表面層を除去しているので、保護膜の表面層の変
質による悪影響が生じないようにすることができる。As described above, according to the present invention, even if the surface layer of the protective film made of polyimide is deteriorated by dry etching for removing the natural oxide film formed on the surface of the connection electrode. Since the surface layer of the protective film made of the polyimide is removed, it is possible to prevent adverse effects due to the deterioration of the surface layer of the protective film.
【図１】（Ａ）〜（Ｅ）はそれぞれこの発明の一実施例
における半導体装置の各製造工程を示す断面図。FIGS. 1A to 1E are cross-sectional views illustrating respective manufacturing steps of a semiconductor device according to an embodiment of the present invention;
【図２】（Ａ）はこの半導体装置のバンプ電極をＴＡＢ
テープのフィンガリードに接続した状態の平面図、
（Ｂ）はその一部の断面図。FIG. 2 (A) shows a bump electrode of this semiconductor device formed by TAB.
Plan view of a state connected to the finger leads of the tape,
(B) is a partial cross-sectional view thereof.
【図３】この発明を適用した半導体装置の変形例を示す
断面図。FIG. 3 is a sectional view showing a modification of the semiconductor device to which the present invention is applied;
【符号の説明】 １ シリコンウエハ（半導体装置本体） ４ 接続用電極 ５ パッシベーション膜（無機絶縁膜） ６ 開口部 ７ 保護膜 ８ 開口部 １４ バンプ電極[Description of Signs] 1 Silicon wafer (semiconductor device main body) 4 Connection electrode 5 Passivation film (inorganic insulating film) 6 Opening 7 Protective film 8 Opening 14 Bump electrode
Claims (4)
極とバンプ電極との周縁部の間に無機絶縁膜とポリイミ
ドからなる保護膜が介在され、前記ポリイミドからなる
保護膜の前記バンプ電極から露出した領域において少な
くともその表面が除去されていることを特徴とするバン
プ電極を備えた半導体装置。A protective film made of an inorganic insulating film and polyimide is interposed between peripheral portions of a connection electrode and a bump electrode formed on a semiconductor device main body. A semiconductor device comprising a bump electrode, wherein at least a surface of the exposed region is removed.
記無機絶縁膜の開口部とこの開口部よりも大きく形成さ
れた前記ポリイミドからなる保護膜の開口部を介して接
続されていることを特徴とする請求項１記載のバンプ電
極を備えた半導体装置。2. The method according to claim 1, wherein the connection electrode and the bump electrode are connected via an opening in the inorganic insulating film and an opening in the protective film made of polyimide, which is formed to be larger than the opening. A semiconductor device comprising the bump electrode according to claim 1.
縁部の間に介在された前記ポリイミドからなる保護膜
は、その表面除去前において１μｍ程度以上の厚さを有
することを特徴とする請求項１または２記載のバンプ電
極を備えた半導体装置。3. The protective film made of polyimide interposed between the peripheral portions of the connection electrode and the bump electrode has a thickness of about 1 μm or more before the surface is removed. Item 3. A semiconductor device comprising the bump electrode according to item 1 or 2.
ンプ電極から露出した領域の表面が５０００Å程度以下
除去されていることを特徴とする請求項１〜３のいずれ
かに記載のバンプ電極を備えた半導体装置。4. The bump electrode according to claim 1, wherein a surface of a region of the protection film made of the polyimide which is exposed from the bump electrode is removed by about 5000 ° or less. Semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13919697A JP3371757B2 (en) | 1997-05-15 | 1997-05-15 | Semiconductor device with bump electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13919697A JP3371757B2 (en) | 1997-05-15 | 1997-05-15 | Semiconductor device with bump electrode |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5299057A Division JP2698827B2 (en) | 1993-11-05 | 1993-11-05 | Method of manufacturing semiconductor device having bump electrode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH1056020A true JPH1056020A (en) | 1998-02-24 |
| JP3371757B2 JP3371757B2 (en) | 2003-01-27 |
Family
ID=15239801
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13919697A Expired - Lifetime JP3371757B2 (en) | 1997-05-15 | 1997-05-15 | Semiconductor device with bump electrode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3371757B2 (en) |
-
1997
- 1997-05-15 JP JP13919697A patent/JP3371757B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JP3371757B2 (en) | 2003-01-27 |
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