JPH1051434A - Differentiation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent deterioration in a reception characteristic of a transmitter by eliminating an undesired resonance frequency caused by mismatching between an output impedance of a differential input buffer and an output impedance of a fixed delay circuit thereby eliminating distortion of a clock waveform produced by a rectifier circuit. SOLUTION: In this differentiation circuit provided with a differential input buffer 2, a delay circuit 4 and a differential output buffer 3, the length of a delay line of the delay circuit 4 is selected so that a frequency of an input signal is not close to an undesired resonance frequency caused by mismatching between an impedance of the differential input buffer 2 and an impedance of the delay circuit 4. Low-pass filters 7a, 7b to eliminate a resonance frequency are provided to an output of the differential output buffer 3 and an output side of the low-pass filters is provided with a rectifier circuit 5 to rectify output signals from the low-pass filters 7a, 7b and to generate the rectified signal of the clock component and a differential matching buffer 8 which prevents signal reflection is provided between the output of the low pass filters 7a, 7b and the rectifier circuit 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in, for example, a doubler for doubling a reference clock signal and a timing extracting circuit for extracting a clock component from input data in an optical communication device and an optical receiver of an optical transmission system. Related to the differentiating circuit used.

[0002]

2. Description of the Related Art Conventionally, techniques in such a field include:
For example, there is one described in the following literature. References: Proceedings of IEICE Autumn Conference 1991, C-418, Hiroyuki Kikuchi, Noboru Ishihara, Eiichi Sano, Yukio Akazawa, Yasuo Yamane, "10
Gb / s GaAs-MESFET Timing Extraction IC ”, P.5-132 Generally, in an optical transmission system, an optical transmitting terminal is provided at one end of an optical transmission line, and a plurality of lines with low transmission speeds are time-division multiplexed. An optical signal having a higher transmission rate is transmitted to an optical transmission line.
In this time division multiplexing, a reference clock signal supplied to an optical transmitting terminal is normally performed based on a clock signal multiplied by a clock signal having a transmission speed of an optical signal to be transmitted to an optical transmission line. Will be In order to multiply the clock signal, it is necessary to generate a differential waveform of the reference clock signal and rectify the differential waveform.

In the optical receiver, when the logic level and jitter of an input data signal are discriminated and reproduced, usually, the equalized data signal is latched by a predetermined clock signal. The input data signal is RZ (Retu
If the signal has a clock component such as an (rn to Zero) code, the clock component can be easily extracted by passing through a filter. However, recently, the code format of the input data signal is being standardized to a non-return to zero (NRZ) code, and a circuit for differentiating the input data signal is required to extract a clock component. For example, a conventional optical receiver, particularly an optical receiver operating at a high speed of about Gb / s, employs a differentiating circuit as described in the above document.

FIG. 5 is a block diagram showing the configuration of a conventional differentiating circuit. FIG. 6 is a time chart for explaining the operation of FIG. 5, in which voltage is plotted on the vertical axis and time is plotted on the horizontal axis. FIG. 7 is a graph showing the relationship between the clock frequency and the unnecessary resonance frequency of the conventional differentiating circuit. The vertical axis represents dBm (output power) and dB (filter gain), and the horizontal axis represents f (frequency). This differentiating circuit includes a differential input buffer 2, a differential input buffer 3, and a fixed delay circuit 4. The input terminal 1a is connected to the non-inverting input terminal of the differential input buffer 2. The input terminal 1b is connected to the inverting input terminal of the differential input buffer 2. The differential input buffer 2 has a function of generating a non-inverted signal S1 and an inverted signal S11 of the input signal S1.

The non-inverting output terminal of the differential input buffer 2 is connected to the non-inverting input terminal of the differential input buffer 3 and to the inverting input terminal of the differential output buffer 3 via the fixed delay circuit 4. It is connected. The inverting output terminal of the differential input buffer 2 is connected to the inverting input terminal of the differential input buffer 3 and to the non-inverting input terminal of the differential output buffer 3 via the fixed delay circuit 4. ing. The differential output buffer 3 converts the differential waveform signals respectively generated by the fixed delay circuit 4 into rectifier circuits 5.
It has a function to propagate to. The fixed delay circuit 4 is configured by a transmission line having a delay time τ. Output terminals of the differential output buffer 3 are connected to input terminals of the rectifier circuit 5, respectively, and output terminals of the rectifier circuit 5 are output terminals 6a and 6a, respectively.
6b.

The operation of FIG. 5 will be described with reference to FIG.
When a signal having a waveform like the signal S1 shown in FIG. 5 is input from the input terminals 1a and 1b to the input terminal of the differential input buffer 2, the signal S1 is output from the non-inverted output terminal of the differential input buffer 2. Then, the signal is input to one end of the fixed delay circuit 4, the inverted signal S 11 of the signal S 1 is output from the inverted output terminal of the differential input buffer 2, and is input to the other end of the fixed delay circuit 4. Assuming that the delay time of the fixed delay circuit 4 is τ, the fixed delay circuit 4 determines that the signal S1 having the pulse width T ₀ and the inverted signal S11 pass through the fixed delay circuit 4 itself and the propagation time is τ.
Differential signal S3 obtained by combining delayed inverted signal S2
To generate a, inversion signal S1 having a pulse width T ₀
1 and the signal S1 pass through the fixed delay circuit 4 itself to generate a differential signal S13 obtained by synthesizing the inverted signal S12 whose propagation time is delayed by τ. The signal S3 is input to the non-inverting input terminal of the differential output buffer 3, and the signal S13 is input to the inverting input terminal.

Further, by rectifying the differential waveform S3 with the rectifier circuit 5, a waveform such as the signal S4 in FIG. 6 is obtained.
The clock component A1 is generated, and the clock component A1 is output from the output terminal 6a. Also, by rectifying the differential waveform S13 by the rectifier circuit 5, a waveform like the signal S14 in FIG. 6 is obtained, a clock component A2 is generated, and the clock component A2 is output from the output terminal 6a. The clock component A generated by Fourier-transforming the rectified waveform is expressed by the following equation (1) with a delay time τ and a pulse width T ₀ corresponding to a one-bit cycle.

[0008]

(Equation 1)

Therefore, the delay time τ is calculated under the condition of the following equation (2).
, The maximum clock component can be obtained. _{τ = T 0/2 ····· (} 2)

[0010]

In the above-described conventional differentiating circuit, a differentiating operation is performed by inserting a fixed delay circuit 4 between the output of the differential input buffer 2 and the input of the differential input buffer 3. This is based on the premise that the output impedance of the differential input buffer 2 and the input impedance of the fixed delay circuit 4 are matched.
In actuality, the output impedance of the differential input buffer 2 formed as an IC is determined by an active element incorporated therein, for example, FE.
The output impedance of T, the additional resistance, the peaking inductor, the wiring, and the like are determined. The input / output impedance of the fixed delay circuit 4 is determined by, for example, the dielectric constant of the substrate and the manufacturing accuracy such as the line width in consideration of a strip line. Therefore, deviation from the design value cannot be avoided.

Furthermore, a connection technique such as wire bonding is required to insert a fixed delay circuit 4 between the output of the differential input buffer 2 and the input of the differential input buffer 3 to achieve electrical connection. However, since the IC output pad necessary for performing the wire bonding appears as a capacitance, it may affect the output impedance of the differential input buffer 2. If there is an impedance mismatch, an influence on the original waveform and an effect of resonance due to the folding between the mismatches will occur. Especially,
The effect of resonance is rectified in the subsequent stage, and if a conventional differentiating circuit is used to obtain a clock component, if other unnecessary resonance frequency components are present, the clock waveform will be distorted, and the reception characteristics of the transmission device will deteriorate. Cause. This is because the unnecessary resonance frequency component is removed by a filter at the subsequent stage, but if the unnecessary resonance frequency f1 is too close to the clock frequency f0 as shown in the graph of FIG. There was a problem that it disappeared.

[0012]

SUMMARY OF THE INVENTION A differentiating circuit according to the present invention generates a non-inverted signal and an inverted signal of an input signal composed of an NRZ code, and generates a differential signal which propagates the non-inverted signal and the inverted signal, respectively. A first differential is obtained by combining a dynamic input buffer, the non-inverted signal input from one terminal, and the inverted signal input from the other terminal and passed through and delayed in propagation time. A second waveform is generated by synthesizing the inverted signal input from the other terminal and the non-inverted signal input from the one terminal and passed through and delayed in propagation time while generating a waveform. And a differential output buffer for transmitting the first and second differential waveforms generated by the delay circuit to an output terminal. The delay line length of the extension circuit is set so that the unnecessary resonance frequency caused by the mismatch between the impedance of the differential input buffer and the impedance of the delay circuit does not approach the frequency of the input signal. A low-pass filter for removing an unnecessary resonance frequency is provided on an output side; a rectification circuit for rectifying an output signal of the low-pass filter to generate a rectified signal of a clock component is provided on an output side of the low-pass filter; A differential matching buffer for preventing signal reflection is provided between the rectifier circuit and the rectifier circuit.

In the present invention, the delay line length of the delay circuit is set so that the unnecessary resonance frequency caused by the mismatch between the impedance of the differential input buffer and the impedance of the delay circuit does not approach the frequency of the input signal. A low-pass filter is provided on the output side of the differential output buffer to remove unnecessary resonance frequencies, and a rectifier circuit is provided on the output side of the low-pass filter to rectify the output signal of the low-pass filter and generate a rectified signal of a clock component. Since a differential matching buffer for preventing signal reflection is provided between the output side of the low-pass filter and the rectifier circuit, a mismatch between the frequency and the impedance of the original output signal output from the differential output buffer may be caused. The generated unnecessary resonance frequencies are separated so that they can be removed by the low-pass filter. Will be able to remove the undesired resonance frequency caused by the mismatch between the impedance by the low-pass filter provided in the clock waveform generated that eliminates the distorted by the rectifier circuit.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. 1 is a block diagram showing a configuration of a differentiating circuit according to Embodiment 1 of the present invention. FIG. 2 is a graph showing a relationship between a clock frequency and an unnecessary resonance frequency of the differentiating circuit.
(Output power) and dB (filter gain), f is on the horizontal axis
(Frequency) is taken. In the figure, the same components as those of the conventional example are denoted by the same reference numerals, and the description of the duplicated components will be omitted. 7a and 7b are low-pass filters provided on the output terminal side of the differential output buffer 3, 8 is an input side connected to the output side of the low-pass filters 7a and 7b, and an output side is a rectifier circuit 5.
Is a differential matching buffer connected to the input side of the buffer. In the first embodiment, as shown in the graph of FIG. 2, the length of the delay line of the fixed delay circuit 4 depends on the impedance of the differential input buffer 2 and the fixed delay circuit 4 with respect to the frequency f0 of the input signal.
Is set so that the unnecessary resonance frequency f1 caused by the mismatch with the impedance does not approach. Such a setting can be made because the unnecessary resonance frequency f1 is obtained by the following equation (3).

[0015]

(Equation 2)

In the above equation, n is the resonance mode, C ₀ is the speed of light, l is the delay line length, and εr is the relative permittivity of the substrate of the delay line. That is, the frequency of the original output signal is known, and if the unnecessary resonance frequencies separated enough to be removed by the low-pass filters 7a and 7b are known, the delay line length 1 of the fixed delay circuit 4 can be calculated by the above equation. . Since the low-pass filters 7a and 7b for removing the unnecessary resonance frequency are provided between the differential output buffer 3 and the rectifier circuit 5, the unnecessary resonance frequency f1 caused by the mismatch with the impedance can be removed. In addition, the clock waveform generated by the rectifier circuit 5 is not distorted, and deterioration of the reception characteristics of the transmission device is prevented. Note that the differential matching buffer 8 is a low-pass filter 7.
This is necessary to prevent reflection of a signal generated between the rectifier circuit 5 and the rectifier circuit 5.

Embodiment 2 FIG. 3 is a block diagram showing a configuration of a differentiating circuit according to Embodiment 2 of the present invention. In the figure, the same components as those of the first embodiment of the present invention are denoted by the same reference numerals, and the description of the duplicate components will be omitted. The second embodiment differs from the first embodiment in that low-pass filters 7a and 7b for removing a resonance frequency are provided on the output side of the rectifier circuit 5. Further, the length of the delay line of the fixed delay circuit 4 depends on the impedance of the differential input buffer 2 with respect to the frequency of the input signal.
The setting is the same so that the unnecessary resonance frequency generated due to the mismatch with the impedance of the target does not approach.

In the second embodiment, the delay line length of the delay circuit 4 is set so that the unnecessary resonance frequency does not approach the frequency twice as high as the frequency of the clock that comes closest to the unnecessary resonance frequency. Unnecessary resonance frequencies are removed by low-pass filters 7a and 7b provided on the output side of the rectifier circuit 5. The differential signal obtained by inserting the delay circuit 4 between the outputs of the differential input buffer 2 is
The frequency component that is the basis of the clock (frequency F0) is F1
= F0 / 2, and the unnecessary resonance component caused by the impedance mismatch between the differential input buffer 2 and the delay circuit 4 is represented by F2 = F0
If + δF, the non-linearity of the rectifier circuit 5 causes F1 and F2 and their respective twice, three times,... Frequency components to pass through as they are. Is considered to be sufficiently small, and can be ignored. Therefore, the output of the rectifier circuit 5 includes F1 = F0 / 2, F2 = F0 + δF,
F3 = 2 * F1 = F0, F4 = 2 * F2 = 2 * F0 + 2
* ΔF will appear. In general, in an electric circuit, when the input frequency is low, the leakage to the output side is small, and as the input frequency increases, the component leaking to the output increases. Here, if the F1 component is further reduced, then F2 = F0 + δF, F3 = 2 * F1 = F0, F4 =
The component of 2 * F2 = 2 * F0 + 2 * .delta.F is the main component, but the frequency difference is closest to the unnecessary resonance frequency F.
This is because the frequency component F3 is twice the frequency component that is the basis of the clock.

In the second embodiment, since the unnecessary resonance frequency caused by the mismatch with the impedance is removed by the low-pass filters 7a and 7b after the rectification of the rectification circuit 5, the clock waveform generated by the rectification circuit 5 has distortion. This does not occur, and deterioration of the reception characteristics of the transmission device is prevented. In the second embodiment, the rectifier circuit 5
Low-pass filter 7 for removing the resonance frequency at the output side of
Since a and 7b are provided, there is no problem of signal reflection,
The differential matching buffer 8 provided in the first embodiment of the present invention becomes unnecessary. The integration of the IC from the differential input buffer 2 to the rectifier circuit 5 is limited to the limitation of the inductor and capacitor values of the low-pass filters 7a and 7b composed of LC circuits, problems in area, manufacturing accuracy. Although there are problems such as (error) and yield, these problems are alleviated by reducing the number of buffers by one, and it becomes easier to implement IC as compared with the case of the first embodiment.

Embodiment 3 FIG. 4 is a block diagram showing a configuration of a differentiating circuit according to Embodiment 3 of the present invention. In the figure, the same components as those of the first embodiment of the present invention are denoted by the same reference numerals, and the description of the duplicate components will be omitted. The third embodiment differs from the first embodiment in that a resonance filter 9 having a high resonance Q value for extracting only a clock component of a rectified signal is provided on the output side of a rectifier circuit 5. Further, the delay line length of the fixed delay circuit 4 is set so that an unnecessary resonance frequency caused by a mismatch between the impedance of the differential input buffer 2 and the impedance of the fixed delay circuit 4 does not approach the frequency of the input signal. Is the same. In the third embodiment, only the high-frequency component of the frequency of the original output signal is extracted by the resonance filter 9 provided on the output side of the rectifier circuit 5, so that unnecessary resonance frequencies caused by mismatching with impedance are removed. And low frequency components other than the clock frequency (noise)
Can also be removed, and the clock waveform generated by the rectifier circuit 5 does not cause any further distortion, and the deterioration of the reception characteristics of the transmission device is further prevented.

[0021]

As described above, according to the first aspect of the present invention, the delay line length of the delay circuit is adjusted by the mismatch between the impedance of the differential input buffer and the impedance of the delay circuit with respect to the frequency of the input signal. A low-pass filter that removes the resonance frequency is provided on the output side of the differential output buffer, and the output signal of the low-pass filter is rectified on the output side of the low-pass filter, so that a clock component is generated. A rectifier circuit that generates a rectified signal is provided, and a differential matching buffer that prevents signal reflection between the output side of the low-pass filter and the rectifier circuit is provided. Unnecessary resonance frequencies caused by the mismatch between the frequency of the output signal and the impedance are separated so that they can be removed by a low-pass filter. An unnecessary resonance frequency caused by mismatching with impedance can be removed by a low-pass filter provided between the power buffer and the rectifier circuit, so that a clock waveform generated by the rectifier circuit does not generate distortion and transmission. This has the effect that deterioration of the reception characteristics of the device is prevented.

According to the second aspect of the present invention, when the delay line length of the delay circuit is twice the frequency of the input signal, there is a mismatch between the impedance of the differential input buffer and the impedance of the delay circuit. Rectifier circuit that rectifies the output signal of the differential output buffer to generate a rectified signal of the clock component, and removes the unnecessary resonant frequency from the output side of the rectifier circuit. Low-pass filter is provided, so that unnecessary resonance frequencies caused by mismatch between the frequency of the original output signal output from the differential output buffer and the impedance are separated so that the low-pass filter can remove the unnecessary resonance frequency. An unnecessary resonance frequency caused by impedance mismatch is eliminated by a low-pass filter provided between the buffer and the rectifier circuit. It will be capable of, prevents the clock waveform which is generated by the rectifier circuit distorted, an effect that reception property degradation of the transmission device can be prevented. Further, since the low-pass filter for removing the unnecessary resonance frequency is provided on the output side of the rectifier circuit, there is no problem of signal reflection, and the differential matching buffer provided in the case of claim 1 of the present invention becomes unnecessary. As a result, the number of buffers is reduced by one, and it is easy to integrate the components from the differential input buffer to the rectifier circuit into one IC.

Further, according to the third aspect of the present invention, the delay line length of the delay circuit is set to an unnecessary resonance frequency caused by a mismatch between the impedance of the differential input buffer and the impedance of the delay circuit with respect to the frequency of the input signal. Rectifier circuit that rectifies the output signal of the differential output buffer to generate a rectified signal of a clock component, and extracts only the clock component of the rectified signal at the output side of the rectifier circuit. Since a high-value resonance filter is provided, unnecessary resonance frequencies caused by mismatch between the frequency of the original output signal output from the differential output buffer and the impedance are separated so that the resonance filter can remove the unnecessary resonance frequency. Only the high frequency component of the original output signal is extracted by the resonance filter provided on the output side of the As a result, the unnecessary resonance frequency generated by the rectifier circuit can be removed and low-frequency components other than the clock frequency can be removed. This has the effect of being further prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a differentiating circuit according to Embodiment 1 of the present invention.

FIG. 2 is a graph showing a relationship between a clock frequency and an unnecessary resonance frequency of the differentiating circuit.

FIG. 3 is a block diagram showing a configuration of a differentiating circuit according to Embodiment 2 of the present invention.

FIG. 4 is a block diagram showing a configuration of a differentiating circuit according to Embodiment 3 of the present invention.

FIG. 5 is a block diagram showing a configuration of a conventional differentiating circuit.

FIG. 6 is a time chart for explaining the operation of FIG. 5;

FIG. 7 is a graph showing a relationship between a clock frequency and an unnecessary resonance frequency of a conventional differentiation circuit.

[Explanation of symbols]

 1a Input terminal 1b Input terminal 2 Differential input buffer 3 Differential output buffer 4 Fixed delay circuit 5 Rectifier circuit 6a Output terminal 6b Output terminal 7a Low-pass filter 7b Low-pass filter

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification number Agency reference number FI Technical indication location H04B 10/06 H04L 7/00 25/49

Claims (3)

[Claims] 1. A differential input buffer for generating a non-inverted signal and an inverted signal of an input signal composed of an NRZ code, and propagating the non-inverted signal and the inverted signal, respectively. A first differential waveform is generated by synthesizing the non-inverted signal and the inverted signal that has been input from the other terminal and that has been passed through and the propagation time of which has been delayed. A delay circuit that generates a second differentiated waveform by combining the inverted signal and the non-inverted signal that has been input from the one terminal and that has been passed through and the propagation time of which has been delayed,
A differential output buffer that propagates the first and second differential waveforms generated by the delay circuit to an output terminal, wherein the length of the delay line of the delay circuit is determined with respect to the frequency of the input signal. A low-pass filter that removes the unnecessary resonance frequency from the output side of the differential output buffer by setting so that the unnecessary resonance frequency caused by the mismatch between the impedance of the differential input buffer and the impedance of the delay circuit does not approach. A rectifier circuit for rectifying an output signal of the low-pass filter to generate a rectified signal of a clock component on an output side of the low-pass filter; and reflecting a signal between the output side of the low-pass filter and the rectifier circuit. A differential matching buffer for preventing the differential circuit. 2. A differential input buffer for generating a non-inverted signal and an inverted signal of an input signal composed of an NRZ code, and propagating the non-inverted signal and the inverted signal, respectively. A first differential waveform is generated by synthesizing the non-inverted signal and the inverted signal that has been input from the other terminal and that has been passed through and the propagation time of which has been delayed. A delay circuit that generates a second differentiated waveform by combining the inverted signal and the non-inverted signal that has been input from the one terminal and that has been passed through and the propagation time of which has been delayed,
A differential output buffer for propagating the first and second differential waveforms generated by the delay circuit to an output terminal, wherein the delay line length of the delay circuit is set to 2 times the frequency of the input signal. The frequency is set so that the unnecessary resonance frequency caused by the mismatch between the impedance of the differential input buffer and the impedance of the delay circuit does not approach the double frequency. A differentiating circuit, comprising: a rectifying circuit that generates a rectified signal of a component; and a low-pass filter that removes an unnecessary resonance frequency on an output side of the rectifying circuit. 3. A differential input buffer for generating a non-inverted signal and an inverted signal of an input signal composed of an NRZ code, and propagating the non-inverted signal and the inverted signal, respectively. A first differential waveform is generated by synthesizing the non-inverted signal and the inverted signal that has been input from the other terminal and that has been passed through and the propagation time of which has been delayed. A delay circuit that generates a second differentiated waveform by combining the inverted signal and the non-inverted signal that has been input from the one terminal and that has been passed through and the propagation time of which has been delayed,
A differential output buffer that propagates the first and second differential waveforms generated by the delay circuit to an output terminal, wherein the length of the delay line of the delay circuit is determined with respect to the frequency of the input signal. The unnecessary resonance frequency caused by the mismatch between the impedance of the differential input buffer and the impedance of the delay circuit is set so as not to approach. The output signal of the differential output buffer is rectified, and the rectified signal of the clock component is converted. A differentiating circuit, comprising: a rectifying circuit for generating a signal; and a resonance filter having a high resonance Q value for extracting only a clock component of a rectified signal on an output side of the rectifying circuit.