JPH1050820A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make gettering effect of a heaving doped semiconductor substrate work and make metallic contamination which enters a silicon epitaxial layer trapped in a semiconductor substrate in a manufacturing process by forming a lightly doped silicon epitaxial layer on a high concentration semiconductor substrate. SOLUTION: A field shield part 24 for insulating and separating active regions 39 mutually is formed on a heaving doped P-type silicon single crystalline substrate 23. The field shield part 24 is constituted of a polycrystalline silicon layer 29 as a field electrode part and a silicon dioxide film 30. The field shield part 24 is buried by a single crystalline silicon epitaxial layer 25a and an MOS transistor 26 is formed on the single crystalline silicon epitaxial layer 25a. The MOS transistor 26 is constituted of a gate electrode part 31, a heavly doped N-type diffusion layer and a source/drain region 32 comprised of a heavly doped N-type diffusion layer. Thereby, charge storage characteristic of the transistor 26 can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a field shield element isolation structure which is one of element isolation means and a method of forming the same.

[0002]

2. Description of the Related Art In a semiconductor device using silicon as a semiconductor substrate, an element isolation method has conventionally been used for LO.
The COS (Local Oxidation of Silicon) method has often been used. However, in the LOCOS method, bird's beaks growing laterally toward the active region hinder miniaturization, and in recent years, other techniques, particularly field shield element isolation techniques, have attracted attention. Field shield element isolation technology is to form a single MOS structure consisting of a field shield insulating film and a field shield electrode between active regions forming semiconductor elements, and fix the field shield electrode to a certain reference potential, thereby forming a substrate. This is to prevent the occurrence of a parasitic channel on the surface and to perform isolation between the active regions.

For example, Japanese Patent Application Laid-Open No. 62-162353 discloses a semiconductor device having a field shield element isolation structure and a method of manufacturing the same. Hereinafter, the semiconductor device and its manufacturing method will be described with reference to FIG. First, a silicon dioxide film 2 is formed on a P-type silicon substrate 1 by a thermal oxidation method or the like. Then, a low pressure CVD (Chemical Vapor Deposition,
Hereinafter, a polycrystalline silicon film is formed by a CVD method or the like, and a silicon dioxide film is newly formed thereon by a CVD method or the like. Then, the silicon dioxide film and the polycrystalline silicon film are selectively etched. Then, the polycrystalline silicon film remaining after the etching becomes the field electrode portion 3, the silicon dioxide film becomes the insulating film 4 covering the field electrode portion 3, and the field shield portion 5 is formed.
Here, the region where the silicon dioxide film and the polycrystalline silicon film are selectively etched between the field shield portions 5 becomes the active region 6.

Next, a gate electrode portion 7 in which a silicon dioxide film, a polycrystalline silicon film, and a silicon dioxide film are sequentially laminated is formed on the active region 6, and then the gate electrode portion 7 is formed.
Is used as a mask to implant an n-type impurity ion such as phosphorus or arsenic to form an N ⁺ -type diffusion layer 8 on the P-type silicon substrate 1 in the active region 6. This N ⁺ type diffusion layer 8 becomes the source / drain of the MOS transistor. Then, a silicon dioxide film 9 is formed on the N ⁺ type diffusion layer 8, and an electrode wiring 10 made of a polycrystalline silicon film of the same layer as the gate electrode is formed on the insulating film 4 of the field shield portion 5, and then an intermediate insulating film is formed. A PSG film 11 as a film is grown on the entire surface. At this time, PS
Since the film thickness of the G film 11 is almost the same regardless of the location, the height from the surface of the P-type silicon substrate 1 is different from the step between the field shield portion 5 and the N ⁺ -type diffusion layer 8 and the gate electrode 7 and N ⁺
The mold diffusion layer 8 has a step. Then, after forming the contact hole 12, A
A metal wiring 13 made of an l-Si film is formed.

The problem with the field shield element isolation structure described in the above publication is that the field shield part and the n
In other words, the semiconductor device has a step of the n-type diffusion layer and a step of the n-type diffusion layer. For this reason, defocus occurs in the step of forming the gate electrode portion. Here, the defocus is a phenomenon in which the width of the gate electrode portion actually patterned by photolithography is larger than the designed value of the width of the gate electrode portion due to the step. In order to solve this problem, another field shield element isolation technique is disclosed in Japanese Patent Laid-Open No. 3-296247.
No. 6,086,045.

[0006] The semiconductor device described in this publication has an element isolation insulating layer formed at a substantially uniform height surrounding the active region, and formed flat in the active region at substantially the same height as the element isolation insulating layer. The semiconductor layer is provided, and the surface of the semiconductor layer is used as an element formation region. Further, the method of manufacturing a semiconductor device described in this publication includes a step of selectively patterning and forming an element isolation insulating layer on a semiconductor substrate,
Forming a semiconductor layer on a semiconductor substrate, applying a resist film over the entire surface, and etching the semiconductor layer and the resist film at substantially the same selectivity to expose the element isolation insulating layer and And a step of flattening the element isolation insulating layer so as to prevent a step from occurring, and a step of forming an element on the semiconductor surface.

[0007]

However, according to the prior art described in the above publication, the flatness between the active region and the field shield portion is certainly improved, but the junction leakage between the semiconductor substrate and the semiconductor layer and the semiconductor are not improved. There is a characteristic problem that the charge storage characteristics are degraded due to metal contamination of the layer. Also, an ultra-fine MOS type L with a reduced active area interval
In the case of SI, there is also a problem that electrical isolation becomes insufficient due to a mismatch defect between the semiconductor substrate and the semiconductor layer.
Further, a problem in a manufacturing method in this technique will be described with reference to FIG.

As shown in FIG. 1A, first, a field shield portion 16 is formed on a P-type semiconductor substrate 15, and a vapor phase epitaxial growth method (with a surface of the semiconductor substrate 15 other than the field shield portion 16 exposed) is performed. Vapor Phase
Epitaxy (hereinafter, referred to as VPE) is performed to form a silicon epitaxial film 18. In this growth method, SiCl ₄ and H ₂ are introduced as raw material gases into a reaction tube to precipitate Si. The portion of the deposited Si epitaxially grown on the active region 17 becomes heterogeneous single crystal silicon, and the portion epitaxially grown on the field shield portion 16 becomes polycrystalline silicon. Thereafter, a resist film 19 is applied on the entire surface of the silicon epitaxial film 18 and the semiconductor substrate 15 is rotated at a high speed by a spinner to flatten the resist film 19.

Next, as shown in FIG. 5B, etching is performed so that the upper surfaces of the silicon epitaxial film 18 and the field shield portion 16 are flat and substantially coplanar. Specifically, the silicon epitaxial film 18 and the resist film 19 are etched at the same selectivity using a sputter etching method using CF ₄ or the like as an etching gas. However, since the polycrystalline silicon deposition portion on the field shield portion 16 is heterogeneous, and the silicon dioxide film 20 on the field shield portion 16 is also etched, the flatness after the etching process is insufficient. Problems arise.

Next, as shown in FIG. 5C, a MOS transistor 21 is formed in the active region 17.
Even if the glass layer is covered after the S transistor 21 is formed, unevenness due to the inhomogeneity of the base is amplified, so that a step is formed in the intermediate insulating film and the metal wiring, and defocus also occurs in the step of forming the metal wiring. There was a problem that. That is, in this technique, the field shield part 16 is
Although the device is buried with the silicon nitride film 8 and the device is formed on the silicon epitaxial film 18, the structure seems to be considerably flattened. However, a step is actually formed on the wiring, and the problem of defocus is still solved. Remains untouched.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a semiconductor device having a field shield element isolation structure excellent in characteristics and a manufacturing process, and a method of manufacturing the same. And

[0012]

To achieve the above object, a semiconductor device according to the present invention comprises a semiconductor substrate containing a first conductive type impurity at a high concentration and an insulating substrate formed on the semiconductor substrate in order. A field shield part comprising a film, a field shield electrode, and an insulating film, which insulates and isolates between active regions, and a first conductive type of the first conductive type, in which the field shield part is embedded and the upper surface is substantially the same height as the upper surface of the field shield part. Characterized by having a silicon epitaxial layer containing impurities at a low concentration, and a MOS transistor comprising a gate electrode portion formed on the silicon epitaxial layer and an impurity diffusion layer of a first conductivity type and a reverse conductivity type. It is. Specifically, the semiconductor substrate contains boron at a high concentration and has a specific resistance of 5/1000 to 50 / 1000Ω.
Cm single crystal silicon substrate, the silicon epitaxial layer contains boron at a low concentration and has a specific resistance of 0.5 to
It is desirable to use a silicon epitaxial layer of 15 Ω · cm. Further, a BPSG film may be provided as an intermediate insulating film covering the MOS transistor and the field shield portion, and wiring may be provided on the BPSG film.

Further, a method of manufacturing a semiconductor device according to the present invention
A step of forming a field shield portion by sequentially forming an insulating film, a field shield electrode, and an insulating film on a semiconductor substrate containing a first conductive type impurity at a high concentration; A step of forming a silicon epitaxial layer containing a low concentration, and selectively removing the silicon epitaxial layer on the field shield part by chemical mechanical polishing or wet etching using a strong alkaline solution, thereby forming an upper surface of the field shield part. Forming a gate electrode portion and an impurity diffusion layer of a conductivity type opposite to the first conductivity type on the silicon epitaxial layer. And a step of forming.

According to the present invention, the gettering effect of the high-concentration semiconductor substrate acts by forming the low-concentration silicon epitaxial layer on the high-concentration semiconductor substrate, and metal contamination penetrating into the silicon epitaxial layer during the manufacturing process. Is captured on the semiconductor substrate. Further, in the present invention, since the silicon epitaxial layer containing impurities at a low concentration is formed, the polycrystalline silicon layer formed on the field shield portion becomes uniform. In addition, the polycrystalline silicon layer on the field shield is removed by CMP or wet etching using a strong alkali. However, since these methods have a high selectivity, only the homogeneous polycrystalline silicon layer is removed. Can be reliably removed. As a result, the flatness of the upper surface of the field shield portion and the upper surface of the silicon epitaxial layer can be improved.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a view showing a semiconductor device according to the present embodiment. In the figure, reference numeral 23 denotes a high-concentration P-type silicon single crystal substrate (semiconductor substrate), reference numeral 24 denotes a field shield portion, and reference numeral 25a denotes a single crystal silicon epitaxial layer (silicon). Epitaxial layer), 26 is a MOS transistor, 27 is a BPSG film, and 28 is an Al wiring (wiring).

As shown in FIG. 1, a field shield portion 24 for insulating and isolating between active regions 39 is formed on a high-concentration P-type silicon single crystal substrate 23. High concentration P
Type silicon single crystal substrate 23 is 10 ²⁰ to 10 ²¹ atom / cm ³
Contains boron at a high concentration of about 5 / 1000-
It is a silicon single crystal substrate (P ⁺⁺ substrate) of 50 / 1000Ω · cm. The field shield part 24 includes a polycrystalline silicon layer 29 as a field electrode part and a silicon dioxide film 30. The field shield portion 24 is embedded with a single-crystal silicon epitaxial layer 25a, and a MOS transistor 26 is formed on the single-crystal silicon epitaxial layer 25. The single crystal silicon epitaxial layer 25a contains boron at a low concentration of about 10 ¹⁷ atom / cm ^{3 and} has a specific resistance of 0.5 to 15 Ω · cm. The MOS transistor 26 includes a gate electrode portion 31 and source / drain regions 32, 32 each formed of a high-concentration n-type diffusion layer and a high-concentration N-type diffusion layer, and is an Nch transistor having an LDD structure. .

A silicon nitride film 33 is formed on the upper surface of the field shield portion 24.
A BPSG (Boron Phosphorous Silicate Glass) film 27 as an intermediate insulating film is formed on the gate electrode 3 and the gate electrode 31.
Are formed. The source / drain region 32 penetrates through the BPSG film 27 and the silicon nitride film 33.
Are formed, and a Ti / TiN film 35, a W plug 36, and an Al wiring 28 are sequentially formed in the groove 34.

Next, a method of manufacturing the semiconductor device having the above configuration will be described with reference to FIGS. FIG. 2 and FIG.
FIG. 4 is a process flow chart showing a method of manufacturing a semiconductor device according to the present embodiment in the order of steps.

As shown in FIG. 2 (a), first, 10 ²⁰ ~
A high-concentration P-type silicon single crystal substrate 23 containing boron at a high concentration of about 10 ²¹ atom / cm ³ and a specific resistance of 5/1000 to 50/1000 Ω · cm is prepared, and a field shield portion 24 is formed on the surface thereof. I do. In this case, for example, a silicon dioxide film formed by a thermal oxidation method or the like, a polycrystalline silicon film formed by a low-pressure CVD method or the like, and a silicon dioxide film formed by a CVD method or the like are sequentially formed on the substrate.
The polycrystalline silicon film is selectively etched. Then
The polycrystalline silicon film 29 remaining after the etching becomes a field electrode portion, and the silicon dioxide film 30 becomes an insulating film covering the field electrode portion.
Is formed.

Next, with the surface of the high-concentration P-type silicon single crystal substrate 23 other than the field shield portion 24 exposed, the surface of the field shield portion 24 and the single crystal substrate 2 are exposed.
A silicon epitaxial layer 25 is formed on the three surfaces. At this time, a uniform and flat polycrystalline silicon layer 25b grows on the upper surface of the field shield portion 24, and a single crystal silicon epitaxial layer 25a is formed on the active region 39 surrounded by the field shield portion 24. When forming a silicon epitaxial layer, V is a type of CVD method.
Using the PE method, monosilane (Si
H ₄ ), hydrogen (H ₂ ) and diborane (B ₂ H ₆ ).
Silicon is deposited by vapor phase growth at a high temperature of 00 ° C. The single crystal silicon deposited on the active region is 1
A single crystal silicon epitaxial film 25a containing boron at a low concentration of about 0 ¹⁷ atom / cm ³ and having a specific resistance of 0.5 to 15 Ω · cm is obtained.

Next, as shown in FIG. 2B, chemical mechanical polishing (hereinafter, referred to as CMP).
The surface is polished using a chemical solution and an abrasive, or wet etching is performed using a potassium hydroxide solution. Remove. In the polishing using a strong alkaline chemical solution and an abrasive by the CMP method, the protruding polycrystalline silicon layer 25b is polished and removed to flatten the upper surfaces of the field shield portion 24 and the single crystal silicon epitaxial layer 25a without any step. it can. Also, by wet etching using a strong alkaline chemical such as a potassium hydroxide solution, only the polycrystalline silicon layer 25b can be selectively chemically etched,
The silicon dioxide film 30 and the single crystal silicon epitaxial layer 25a of the field shield portion 24 are not removed. Therefore, even if wet etching using a potassium hydroxide solution at 85 ° C. is performed instead of the CMP method, the polycrystalline silicon layer 25b is selectively etched significantly more favorably than the silicon dioxide film 30 and the single crystal silicon epitaxial layer 25a. Thus, the planarization process similar to the CMP method, in which the upper surfaces of the field shield portion 24 and the single crystal silicon epitaxial layer 25a can be planarized without any step, can be performed.

Next, as shown in FIG. 2C, a MOS transistor 26 is formed on the single crystal silicon epitaxial layer 25a by a known method. The gate electrode portion 31 of the MOS transistor 26 includes a polycrystalline silicon layer 40 doped with impurities by a CVD method and a silicon dioxide film 41 covering the polycrystalline silicon layer 40. After the gate electrode portion 31 is formed, n-type impurity ions such as phosphorus and arsenic are implanted over the entire surface of the substrate using the gate electrode portion 31 as a mask,
High-concentration n-type diffusion layers 42, 42 serving as source / drain regions of MOS transistor 26 are formed.

Next, as shown in FIG.
A high concentration N-type diffusion layer 43 is formed by implanting n-type impurity ions such as phosphorus and arsenic over the entire surface of the substrate, leaving a part of the diffusion layer in the region 42. High concentration n-type diffusion layer 4
2 and the high-concentration N-type diffusion layer 43, an n-type LD having a conductivity type opposite to that of the substrate 23 is formed on both sides of the gate electrode portion 31.
Source / drain regions 32 having a D structure are formed. Thereafter, a silicon nitride film 33 is formed on the surface of the single-crystal silicon epitaxial layer 25a except for the gate electrode portion 31 and on the surface of the field shield portion 24.

Next, as shown in FIG. 3E, a BPSG, which is a silicon oxide film doped with phosphorus and boron at a high concentration, is formed on the gate electrode portion 31 and the silicon nitride film 33.
The film 27 is deposited as an intermediate insulating film, and is flattened by reflow by heat treatment. Then, as shown in FIG. 3F, a groove 34 reaching the high-concentration N-type diffusion layer 43 is formed by etching the BPSG film 27 and the silicon nitride film 33, and a Ti / TiN film 35 is formed in the groove 34. W plug 36, Al
The wirings 28 are sequentially formed. The high-concentration N-type diffusion layer 43
The reason why the Ti / TiN film 35 is provided thereon is to prevent alloy spikes on the high-concentration N-type diffusion layer 43. Thus, the semiconductor device of the present embodiment is completed.

In the semiconductor device of the present embodiment, the following effects can be obtained in terms of characteristics. By forming the low-concentration single-crystal silicon epitaxial layer 25a on the high-concentration P-type silicon single-crystal substrate 23, the gettering effect of the high-concentration P-type silicon single-crystal substrate 23 acts, and the single-crystal silicon epitaxial Metal contamination contained in the layer 25a is taken into the high-concentration P-type silicon single crystal substrate 23. As a result, the single-crystal silicon epitaxial layer 25 having a large effect on the device characteristics
Since metal contamination is excluded from the active region 39 on the a surface,
The charge storage characteristics of the MOS transistor 26 can be improved. Also, a high-concentration P-type silicon single crystal substrate 23
, The induction of the inverted n-layer can be completely eliminated. Then, the single crystal silicon epitaxial layer 25a
Since the region immediately below the gate electrode portion 31 becomes a low-concentration P-type region and the N-type diffusion layer becomes a high-concentration N-type region, these junctions have the breakdown voltage of the PN junction. Nothing.

The high-concentration P-type silicon single crystal substrate 23
The reason for setting the specific resistance to 5/1000 to 50/1000 Ω · cm is that if the specific resistance is less than 5/1000 Ω · cm, the boron concentration becomes small and the single crystal silicon epitaxial layer 25
This is because the metal contamination contained in a cannot be controlled, and the induction of the inversion n layer cannot be completely eliminated. On the other hand, when the specific resistance exceeds 50/1000 Ω · cm, the boron concentration becomes large, so that the metal contamination contained in the single-crystal silicon epitaxial layer 25 a is prevented from being taken into the high-concentration P-type silicon single-crystal substrate 23, resulting in a gettering effect. Does not work. Therefore, the specific resistance 5 /
The gettering effect is effectively generated in the range of 1000 to 50/1000 Ω · cm. Further, the specific resistance of the single crystal silicon epitaxial layer 25a is set to 0.5 to 15 Ω · cm.
The reason is that if it is less than 0.5 Ω · cm, it is inappropriate for single crystallization of silicon, and if it exceeds 15 Ω · cm, there is a problem that a latch-up phenomenon occurs and electrical isolation between the active regions 39 is insufficient. This is because it is difficult to obtain the isolation characteristics particularly in an ultra-fine LSI structure of 0.4 μm or less.

Further, the following effects can be obtained in the manufacturing process. In the prior art, a silicon epitaxial layer containing no impurities is formed, whereas in the present invention, a silicon epitaxial layer 25 containing impurities at a low concentration is formed.
The polycrystalline silicon layer 25b formed on the substrate 4 becomes uniform. In addition, the polycrystalline silicon layer 25b on the field shield portion 24 is
Or a method of removing by wet etching,
Since these methods have a high selectivity, the polycrystalline silicon layer 2
5b can be reliably removed, and the upper surface of the field shield portion 24 and the single crystal silicon epitaxial layer 25 can be removed.
a The flatness of the upper surface can be increased as compared with the related art. Therefore, since a large step cannot be formed on the BPSG film 27 and the like formed thereon, defocus can be prevented from occurring in the step of forming the Al wiring 28.

Furthermore, in the prior art, P is used as an intermediate insulating film.
Although the SG film is employed, the PSG film has a lower fluidity than the BPSG film 27 and the like. Therefore, if the PSG film is employed in the element structure of the present embodiment, the PSG film is formed of a silicon nitride film 33. The level difference of the gate electrode portion 31 is reflected, and it is difficult to planarize. On the other hand, in the case of the present embodiment, since the BPSG film 27 having higher fluidity is used as the intermediate insulating film, the step between the silicon nitride film 33 and the gate electrode portion 31 is canceled, and flattening can be easily achieved. it can.

The technical scope of the present invention is not limited to the above embodiment, and various changes can be made without departing from the spirit of the present invention. For example, in this embodiment, an example is shown in which the low-concentration P-type silicon epitaxial layer 25a is formed on the high-concentration P-type silicon single crystal substrate 23, and the Nch transistor 26 is formed thereon. , An N-type silicon epitaxial layer is formed on an N-type silicon single crystal substrate, and a Pch
A transistor may be formed. Further, specific numerical values such as the film thickness of various films and manufacturing conditions can be appropriately set.

[0030]

As described above in detail, according to the semiconductor device and the method of manufacturing the same of the present invention, gettering of a high-concentration semiconductor substrate by forming a low-concentration silicon epitaxial layer on a high-concentration semiconductor substrate. The effect works, and the metal contamination contained in the silicon epitaxial layer is taken into the high-concentration semiconductor substrate during the manufacturing process.
As a result, metal contamination is eliminated from the active region on the surface of the silicon epitaxial layer which has a great influence on the device characteristics, and the charge storage characteristics of the MOS transistor are improved. Also, excellent characteristics can be obtained in terms of securing the junction breakdown voltage and preventing the latch-up phenomenon. Further, in terms of the manufacturing process, the polycrystalline silicon layer formed on the field shield portion becomes homogeneous, and only this homogeneous polycrystalline silicon layer is surely removed by the CMP method or the wet etching method having a high selectivity. Therefore, the flatness of the upper surface of the field shield portion and the upper surface of the silicon epitaxial layer can be increased as compared with the related art. As a result, since a large step cannot be formed in the intermediate insulating film and the metal wiring formed thereon, defocus can be prevented from occurring in the step of forming the metal wiring.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a process flow diagram showing a method for manufacturing a semiconductor device in the order of steps.

FIG. 3 is a continuation of the process flow diagram.

FIG. 4 is a cross-sectional view illustrating an example of a conventional semiconductor device having a field-field element isolation structure.

FIG. 5 is a process sectional view showing another example of a conventional semiconductor device having a field-field element isolation structure.

[Explanation of symbols]

Reference Signs List 23 High-concentration P-type silicon single crystal substrate (semiconductor substrate) 24 Field shield portion 25 Silicon epitaxial layer 25a Single crystal silicon epitaxial layer (silicon epitaxial layer) 25b Polycrystalline silicon layer 26 MOS transistor 27 BPSG film 28 Al wiring (wiring) 31 Gate electrode part 32 Source / drain region 39 Active region 42 High concentration n-type diffusion layer 43 High concentration N-type diffusion layer

Claims (4)

[Claims] 1. A field which comprises a semiconductor substrate containing an impurity of a first conductivity type at a high concentration, an insulating film, a field shield electrode, and an insulating film sequentially formed on the semiconductor substrate, and insulates and separates active regions from each other. A shield portion, a silicon epitaxial layer in which the field shield portion is buried, the upper surface of which is substantially the same height as the upper surface of the field shield portion, and the first epitaxial layer contains a first conductivity type impurity at a low concentration; A semiconductor device comprising: a formed gate electrode portion; and a MOS transistor including an impurity diffusion layer of a conductivity type opposite to the first conductivity type. 2. The semiconductor device according to claim 1, wherein said semiconductor substrate contains boron at a high concentration and has a specific resistance of 5%.
/ 1000 to 50/1000 Ω · cm, wherein the silicon epitaxial layer is a silicon epitaxial layer containing boron at a low concentration and having a specific resistance of 0.5 to 15 Ω · cm. Semiconductor device. 3. The semiconductor device according to claim 1, wherein a BPSG film is provided as an intermediate insulating film covering said MOS transistor and a field shield portion.
A semiconductor device, wherein a wiring is provided on a G film. 4. A step of forming a field shield portion by sequentially forming an insulating film, a field shield electrode, and an insulating film on a semiconductor substrate containing a first conductive type impurity at a high concentration; Forming a silicon epitaxial layer containing one conductivity type impurity at a low concentration; and selectively removing the silicon epitaxial layer on the field shield portion by chemical mechanical polishing or wet etching using a strong alkaline solution. A step of flattening the upper surface of the field shield portion and the upper surface of the silicon epitaxial layer so as to have substantially the same height; and a step of diffusing an impurity of a gate electrode portion and a conductivity type opposite to the first conductivity type on the silicon epitaxial layer. Forming a MOS transistor by forming a layer. Semiconductor device manufacturing method.