JPH1041496A - Manufacture of solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make storage capacitors almost uniform in capacitance and to exactly eliminate fixed pattern noises by a method wherein the electrodes of storage capacitors and the storage capacitor's conductive layers which are formed of the same layers with the electrodes are separately formed through different processes. SOLUTION: A reticle is possessed of a storage capacitor section 21 which includes a pattern for forming a storage capacitor which stores optical signal charge from a picture element and dark signal charge and an optical shielding belt 22 which specifies a chip size. The reticle is aligned with a ground layer on a wafer, and light is projected onto the wafer's region which becomes the electrodes of an optical signal storage capacitor CTS for exposure. Furthermore, a region to be the electrodes of a dark signal charge storage capacitor CTD is exposed to light. After an exposure process is carried out, a polycrystalline silicon layer is patterned for the formation of the electrodes of the storage capacitors and other conductive layers. By this setup, the storage capacitors CTS and CTD can be lessened in capacitance dispersion, and fixed pattern noises can be almost completely eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a solid-state imaging device, and more particularly to a method of manufacturing a solid-state imaging device having a storage capacitor for storing signal charges from photoelectric conversion elements. The present invention relates to a technique for obtaining a high-quality captured image.

[0002]

2. Description of the Related Art As a solid-state imaging device having a storage capacitor for storing signal charges, a CCD or a MOS as a pixel is used.
Amplification type solid-state imaging device using a MOS-type static induction transistor (MOSSIT).

FIG. 8 shows a schematic configuration of an amplification type solid-state imaging device using MOSSIT as a pixel. FIG.
In FIG. 1, pixels are arranged in a matrix of 3 rows × 3 columns for simplicity of description and illustration. However, actually, a larger number of pixels are usually used.

[0004] The solid-state imaging device shown in FIG.
Each of the pixels 101a, 101b,..., 101i made of IT has a pixel matrix arranged in 3 rows × 3 columns as described above. Pixels 101a, 101b, 10 in the first row
The gate electrode 1c is commonly connected through a gate line 102a, and the gate electrodes of the pixels 101d, 101e, and 101f in the second row are commonly shared through a gate line 102b, and the pixels 101g, 101h, and 101i in the third row. The gate electrodes are commonly connected to the vertical drive circuit 103 via a gate line 102c. Note that each pixel 10
The drain electrodes 118 of 1a, 101b,..., 101i are connected to a power source of a predetermined potential in common to all pixels.

[0005] A drive pulse of a desired drive timing and voltage level is applied to a gate electrode of each pixel through a corresponding gate line to a horizontal selection row selected by the vertical drive circuit 103. Depending on whether the voltage level of the drive pulse applied to the gate electrode of each pixel is low, intermediate or high, the MOSSIT of each pixel takes three states: accumulation, reading and reset.

The source electrode of each pixel is commonly connected to source lines 104a, 104b and 104c for each column. That is, the pixels 101a, 101d, 10
The source electrode of 1 g is connected to the source line 104a and the pixel 10
The source electrodes of 1b, 101e and 101h are connected to the source line 104b and the pixels 101c, 101f and 101i.
Are commonly connected to a source line 104c.

Each source line 104a, 104b, 10
4c are vertical reset transistors 105a, 105c.
5b, 105c via a predetermined reset voltage source VRST
V and each of the constant current bias circuits 106
a, 106b, and 106c. The gates of the vertical reset transistors 105a, 105b, 105c are connected in common, and are configured so that a reset pulse φRSTV can be applied.

[0008] Source lines 104a, 104b, 104
c are transfer MOSFETs 107a and 107, respectively.
7b, 107c, the optical signal storage capacitors 109a, 10c.
9b, 109c, and a transfer MO
It is connected to one end of dark signal storage capacitors 110a, 110b, 110c via SFETs 108a, 108b, 108c. Each of the storage capacitors 109a, 109b, 109c,
The other ends of 110a, 110b, 110c are grounded. Each transfer MOSFET 107a, 107b, 107
The gates of c are connected in common so that a transfer control pulse φTS can be supplied. Also, transfer MOSF
The gates of the ETs 108a, 108b, and 108c are commonly connected so that a transfer pulse φTD can be supplied.

Optical signal storage capacitors 109a, 109b, 10
9c each has a horizontal readout MOSFET.
It is connected to the optical signal output line 115 via 112a, 113a, 114a. The dark signal storage capacitor 11
The respective ends of Oa, 110b, and 110c are connected to dark signal output line 116 via horizontal readout MOSFETs 112b, 113b, and 114b, respectively. Gates of the horizontal readout MOSFETs 112a and 112b, 113a and 113b, and 114a and 114b are commonly connected to each other, and a drive pulse is supplied from the horizontal drive circuit 111.

The optical signal output line 115 supplies an optical signal voltage output VOS via an amplifier or a buffer. The dark signal output line 116 provides a dark signal voltage output VOD via an amplifier or buffer. Optical signal output line 11
5 and the dark signal output line 116 are configured to be resettable by horizontal read line reset MOSFETs 117a and 117b, respectively.

In such a solid-state imaging device, the pixel M
When the gate potential of OSSIT is at a low level, the pixel is turned off and is in an accumulation state, and accumulates holes generated by incident light immediately below the gate electrode. However, the pixel can maintain the non-conducting (off) state even when holes corresponding to the saturated exposure amount are accumulated, and a false signal is generated even when the light amount of several hundred times of the saturated light amount is irradiated. Does not cause blooming phenomenon.

When the gate potential of the pixel MOSSIT is at an intermediate level, the pixel enters a read state. In this case, the channel potential is modulated by the holes accumulated immediately below the gate, and a current amplified inside the pixel between the drain and the source in proportion to the amount of incident light can flow.

When the gate potential of the pixel MOSSIT becomes a high level, holes accumulated immediately below the gate electrode are discharged toward the substrate. That is, a reset operation is performed.

In the solid-state imaging device as described above, when each pixel MOSSIT is in the accumulation state, the transfer control pulses φTS, φT
D is set to a high level, and the transfer MOSFET 107 is
a, 107b, 107c, 108a, 108b, 108
c are both brought into conduction. Also, the reset control signal φ
RSTV is set to a high level and the vertical reset transistor 10
By turning on 5a, 105b and 105c together,
Optical signal storage capacitors 109a, 109b, 109c (hereinafter, referred to as
CTS) and dark signal storage capacitors 110a, 110
b, 110c (hereinafter referred to as CTD) at VRS
Initialize to TV. Before starting the read operation, the transfer control pulses φTS and φTD are set to a low level, and the transfer MOSFETs 107a, 107b, 107c and 108 are transferred.
a, 108b, and 108c are turned off. further,
The reset control signal φRSTV is also at a low level, and the vertical reset transistors 105a, 105b, and 105c are also turned off.

In the read operation, the vertical drive circuit 10
3, a pixel in a certain row, for example, pixel 1 in the first row
A drive pulse of an intermediate level is applied to the gate electrodes 01a, 101b, and 101c, and these selected pixels enter a read state. In this state, the transfer control pulse φTS is set to a high level, and the MOSFETs 107a and 107
b and 107c are made conductive. As a result, the source follower operation of each pixel in the selected row starts, and signal charges corresponding to the amount of incident light are stored in the storage capacitors CTS109a and CTS109 for each column.
9b and 109c. After a certain transfer period, the transfer control pulse φTS is set to low level, and the optical signal transfer M
The source follower operation is completed by turning off the OSFETs 107a, 107b, and 107c. Thereafter, a high-level driving pulse is applied to the gate electrode of the pixel in the selected row where the optical signal readout operation is completed, and the pixel is reset.

After the reset operation is completed, an intermediate level driving pulse is applied again from the vertical driving circuit 103 to the gate electrode of the pixel on the selected row. Further, the transfer control pulse φTD is set to a high level to set the dark signal transfer MOSFETs 108a, 108
8b and 108c are made conductive. As a result, the source follower operation of each pixel in the selected row starts, and the pixel MOSS
The dark signal charge of IT is stored in the storage capacitor CTD110 for each column.
a, 110b, and 110c. After a predetermined transfer period, the transfer pulse φTD is set to the low level, and the dark signal transfer M
The dark signal read operation is completed by turning off the OSFETs 108a, 108b, and 108c.

The dark signal output immediately after this reset is applied to each pixel M
This is equivalent to the variation of the threshold voltage of OSSIT itself, and the variation in the threshold voltage of each pixel causes fixed pattern noise (hereinafter abbreviated as FPN).

Thus, the storage capacitors CTS, CTD
After the accumulation of the optical signal charge and the dark signal charge, respectively, the horizontal drive circuit 111 is operated to sequentially read the output from each pixel in the horizontal direction.

First, a high-level driving pulse is applied to the gate electrodes of the horizontal readout MOSFETs 112a and 112b by the horizontal drive circuit 111 to make these MOSFETs conductive. Thereby, the capacity (CTS)
The optical signal output accumulated in 109a is divided into the optical signal output line 115, and the dark signal output accumulated in the capacitance (CTD) 110a is divided into the dark signal output line 116 by the capacitance of the output lines 115 and 116 and the capacitance. Output as voltage outputs VOS and VOD.

A dark signal voltage output VOD is subtracted from the optical signal voltage output VOS by a circuit (not shown) external to the element, so that a variation in the threshold voltage of each pixel is caused.
PN can be suppressed and a true optical signal output can be obtained.

Thereafter, the horizontal reset pulse φRSTH is set to a high level to reset each horizontal read line reset MOSF.
The ETs 117a and 117b are turned on, and the potentials of the output lines 115 and 116 are initialized.

In this manner, each output line 115, 1
16 is completed, the horizontal drive circuit 111 is scanned, and the horizontal readout M is used to read out the pixel output of the next column.
The OSFETs 113a and 113b are turned on. Thus, the same operation as described above is performed, and the capacitors 109b, 1
From 10b, an optical signal output and a dark signal output are output to the outside of the element via output lines 115 and 116, respectively. Such an operation is sequentially repeated for the pixels in each column, so that reading in the horizontal scanning direction is performed. After reading of one row in the horizontal scanning direction is completed, the process proceeds to the next row, and reading is sequentially performed in the same manner.

Next, a method of manufacturing the solid-state imaging device as described above will be described. Generally, in a solid-state imaging device having a storage capacitor, a storage capacitor electrode formed of a MOS capacitor, a gate electrode of a MOSFET, and part of a wiring are formed using a polysilicon layer. When such a formation is performed, a well-known photolithography technique is used, but a reduction projection exposure apparatus is used for a solid-state imaging device having a miniaturized pattern.

FIG. 9 is a schematic view of an entire photomask or reticle used in an exposure process for forming a polysilicon layer. The reticle shown in the figure has a pixel portion 61 provided with a pattern for forming a pixel matrix. Around the pixel section 61, a vertical drive section 62a, which includes a vertical drive circuit for selecting a pixel row in the pixel matrix and supplying a drive pulse and a bias voltage for driving the pixels, is provided. 62b is the pixel portion 61
Are formed on both sides. On the bottom side of the pixel unit 61, a vertical reset unit 63 including a pattern such as a vertical reset transistor for resetting each pixel and a vertical source line connecting the pixels in the vertical direction is formed. A transfer M for transferring a signal photoelectrically converted by a pixel to a storage capacitor is provided on an upper side of the pixel unit 61.
A transfer section 64 including a pattern such as an OSFET, a storage capacitor section 65 including an electrode pattern of the storage capacitor (CTS, CTD), and pixel signals stored in the storage capacitor are sequentially selected in the horizontal direction and read out of the element. Drive unit 66 including a pattern such as a horizontal readout MOSFET for
Are formed. A light-shielding band 67 for defining the chip size is provided around each of these pattern portions.

In the reticle shown in FIG. 9, a circuit pattern corresponding to the polycrystalline silicon or polysilicon layer is formed in each circuit pattern portion.
In particular, FIG. 10 shows a pattern portion of the storage capacitor section 65 for forming a signal storage capacitor.

In the storage capacitor section shown in FIG. 10, two rectangular patterns are arranged as circuit patterns for each unit pixel. One of the rectangular patterns 71a, 72a, 73a,...
The other pattern 71 is used for forming the S electrode.
are used for forming the electrodes of the dark signal storage capacitor CTD. Incidentally, each storage capacitor is formed by forming a polysilicon electrode on a semiconductor substrate via an insulating film.
Each of the rectangular patterns 71a, 71 is an OS capacity.
are used for patterning a polysilicon layer which is one electrode of these MOS capacitors.

[0027]

When the circuit pattern of the prior art as shown in FIG. 10 is used, the following points cause variations in capacitance between each pair of storage capacitors CTS and CTD.

First, there is a reticle manufacturing error. Generally, in a reticle manufacturing process, a circuit pattern is printed using an electron beam lithography apparatus, so that a fine pattern can be formed. Also,
When such a circuit pattern is transferred onto a wafer, the projection is reduced to, for example, 1/5. Therefore, the influence of a reticle manufacturing error on the wafer is likely to be small.
However, in actuality, the line width of the circuit pattern on the reticle also has a finite error, and the capacitances CTS and CTD also vary. Although the value of the variation itself is small, it is reproduced on the wafer.

Second, there is variation in the chip surface of the reduction projection exposure apparatus. Due to distortion of the projection lens in the chip plane and uneven illumination of the illumination system, even if the reticle is not completely uneven, the pattern transferred onto the wafer will have unevenness. For example, in the peripheral portion of the projected image, distortion may occur in the projected pattern or the resolution of the projected image may be degraded due to image distortion caused by the projection lens, resulting in variations in the shape and dimensions of the formed electrodes.

In the above-described method of manufacturing a solid-state imaging device according to the prior art, in order to simplify the manufacturing process, a storage capacitor electrode, a MOSFET gate electrode and a polysilicon wiring of the same layer made of polysilicon are formed. Are formed simultaneously using the same reticle.

For this reason, when the capacitance varies between the storage capacitors CTS and CTD, the difference between the light voltage output VOS and the dark voltage output VOD is determined outside the device.

[Equation 1] Even if the calculation of VOS-VOD is performed, the fixed pattern noise (FPN) is not sufficiently removed, and the SN ratio of the FPN to the FPN deteriorates.

This will be described in some detail. Now, assume that the capacitance value of the optical signal storage capacitor CTS is the same CTS, the capacitance value of the dark signal storage capacitor CTD is the same CTD, the charge of only the signal components stored in these capacitors is QS, and the charge of the dark signal is QD. The wiring capacitances of the optical signal output line 115 and the dark signal output line 116 are assumed to be CHS and CHD, respectively. In this case, each output voltage VOS, VOD is represented by the following equation.

VOS = (QS + QD) ＱΔCTS / (CTS
+ CHS)｝

VOD = QD ｛{CTD / (CTD + CHD)}

The difference between the voltage outputs VOS and VOD is obtained as follows.

VOS-VOD = (QS + QD) ｛CTS /
(CTS + CHS)｝-QD ｛CTD / (CTD + C
HD)｝

If each storage capacitor CTS, CTD and CH
If the values of S and CHD are equal to each other, the following equation can be obtained by setting CTS = CTD = CT and CHS = CHD = CH in the above equation (4).

VOS−VOD = QS ｛CT / (CT + C
H)｝

That is, if the values of the capacitors CTS and CTD are equal, the dark signal component is removed, and thus the FPN is completely removed. However, if the values of the capacitances CTS and CTD are not equal, the above Expression 5 does not hold, and a dark signal component remains. In particular, the storage capacitors CTS,
If the variation of the CTD pair is different, the FPN suppression ratio varies for each pixel in the horizontal direction, and FPN that becomes vertical stripes on the display screen remains. In order to remove such remaining vertical stripes FPN, it is necessary to perform arithmetic processing by an external signal processing circuit.

Accordingly, an object of the present invention is to provide a solid-state imaging device having a storage capacitor for storing signal charges from a photoelectric conversion element, in which a variation in the capacitance value of each storage capacitor is almost completely eliminated and an external signal processing circuit is provided. It is an object of the present invention to accurately remove fixed pattern noise such as vertical stripes FPN without performing a special operation.

[0037]

In order to achieve the above object, according to a first aspect of the present invention, there is provided a method for manufacturing a solid-state imaging device having a plurality of storage capacitors for storing signal charges from photoelectric conversion elements. In the above, the formation of the electrode of the storage capacitor and the formation of a conductive layer other than the electrode of the storage capacitor formed of the same layer as the electrode of the storage capacitor are separately performed.

The formation of the electrode of the storage capacitor and the formation of another conductive layer formed of the same layer as the electrode of the storage capacitor are performed in separate steps, thereby forming the electrode of the storage capacitor. And under the optimum conditions. For example, the electrode of the storage capacitor can be formed using a place having a small distortion and a high resolution, such as a central portion of a screen of a reduction projection exposure apparatus for forming the electrode of the storage capacitor. As a result, variations in the dimensions of the electrodes of the storage capacitors can be reduced, and variations in the capacitance values of the storage capacitors can be reduced, so that a high-performance solid-state imaging device can be manufactured.

In this case, it is convenient to form the storage capacitor electrode and another conductive layer formed of the same layer as the storage capacitor electrode using different masks. By such a method, a dedicated mask can be used as a mask for the storage capacitor. For example, the mask can dispose the pattern of the electrode of the storage capacitor in an area with a small error in the central portion and can reduce the variation in the capacity. It becomes possible to form a storage capacitor.

According to a second aspect of the present invention, there are provided first and second groups of storage capacitors for storing dark signal charges and optical signal charges of a photoelectric conversion element, respectively. In a method for manufacturing a solid-state imaging device for performing a difference process of a signal corresponding to a charge stored in a storage capacitor, the storage capacitor of the first group and the storage capacitor of the second group are used in different steps and using the same mask. Formed.

By forming the storage capacitors of the first group and the storage capacitors of the second group in different steps and using the same mask, the same pattern on the mask is used and the exposure is performed. The same location in the projection area of the device can be used to form the first and second groups of storage capacitors. Therefore, since the storage capacitors of the first and second groups are formed in exactly the same pattern, mutual capacitance variation does not occur. Therefore, for example, the fixed pattern noise can be completely canceled by the difference processing of the signals corresponding to the charges stored in the storage capacitors of the first and second groups.

In this case, the formation of the electrodes of the first group of storage capacitors and the second group of storage capacitors is performed separately from the formation of a conductive layer other than the electrodes formed of the same layer as the electrodes. It is convenient to do so. by this,
Optimum manufacturing conditions such that the process for forming the storage capacitor can be separated from the process for forming other conductive layers, and the storage capacitor can be formed using a less distorted area in the projection screen of the exposure apparatus. Thus, it is possible to form a storage capacitor and eliminate the capacity variation.

According to a third aspect of the present invention, there are provided first and second groups of storage capacitors for storing dark signal charges and optical signal charges of the photoelectric conversion element, respectively. In a method for manufacturing a solid-state imaging device for performing a difference process of a signal corresponding to a charge stored in a storage capacitor, formation of each storage capacitor of the first and second groups of storage capacitors is separated into separate steps and the same. This is performed using a mask.

In this case, in addition to the advantages obtained by the method according to the second aspect of the present invention, each of the storage capacitors of the first and second groups is completely identical to each other. , And the variation in capacitance can be further reduced. In particular, in this case, since all the storage capacitors can be formed using the same pattern of the same mask and the same projection area of the exposure apparatus, variations between the capacitors are extremely reduced. The storage capacity of each group may be formed not by one but by, for example, a plurality of pieces using the same mask. In this case, the number of steps and time required for manufacturing can be reduced.

According to a fourth aspect of the present invention, a plurality of photoelectric conversion elements arranged in a matrix of rows and columns,
A plurality of vertical signal output lines each connected to the output of the photoelectric conversion element of each column, and each column connected to each vertical signal output line via a transfer switch element for storing dark signal charges and optical signal charges A first and second storage capacitors provided for each column, and a horizontal selection drive circuit for sequentially selecting the first and second storage capacitors in each column and connecting the first and second storage capacitors to a dark signal output line and an optical signal output line. In the method for manufacturing a solid-state imaging device, the first and second storage capacitors, the second storage capacitor, and the first and second storage capacitors are formed in the same layer as electrodes of the first and second storage capacitors. The conductive layer other than the storage capacitor is formed in a separate step, and the first storage capacitor and the second storage capacitor are formed using the same mask.

Also in this case, the electrodes of the first and second storage capacitors can be formed using the same mask and can be transferred onto the wafer using the same portion of the exposure apparatus.
There is no variation between the first and second storage capacitors, so that a solid-state imaging device capable of completely removing fixed pattern noise can be manufactured. In addition, since the first and second storage capacitors can be formed in a step different from that of the conductive layer other than these capacitors, the formation conditions of the storage capacitors can be optimized and the capacitance variation can be eliminated.

According to a fifth aspect of the present invention, a plurality of photoelectric conversion elements arranged in a matrix consisting of rows and columns,
A plurality of vertical signal output lines each connected to the output of the photoelectric conversion element of each column, and each column connected to each vertical signal output line via a transfer switch element for storing dark signal charges and optical signal charges A first and second storage capacitors provided for each column, and a horizontal selection drive circuit for sequentially selecting the first and second storage capacitors in each column and connecting the first and second storage capacitors to a dark signal output line and an optical signal output line. In the method for manufacturing a solid-state imaging device, the first storage capacitor, the second storage capacitor, and the first and second storage capacitors are formed in the same layer as the electrodes of the first and second storage capacitors. A conductive layer other than the first and second storage capacitors is formed in a separate step,
And the second storage capacitor are formed using the same mask.

In this case, the same advantages as those of the method according to the fourth embodiment can be obtained. In addition, each of the first storage capacitors and each of the second storage capacitors have the same pattern on the mask, Can be transferred onto the wafer using the same portion, so that the variation in capacitance can be further reduced. In this case, a pattern in which a plurality of the first storage capacitors and a plurality of the second storage capacitors are simultaneously formed can be used, whereby the number of exposures can be reduced and the manufacturing process can be further simplified.

[0049]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a solid-state imaging device according to a preferred embodiment of the present invention will be described below with reference to the drawings. 1 and 2 show a schematic configuration of a whole photomask or reticle used in a method for manufacturing a solid-state imaging device according to a first embodiment of the present invention. That is, in this embodiment, the first and second two reticles are used to separately form the electrode of the storage capacitor and another conductive layer in the same layer as the electrode. In the present embodiment, the electrodes of the storage capacitor formed of these reticles and the other conductive layers are formed of polycrystalline silicon using a reduced projection exposure apparatus.

The reticle shown in FIG. 1 includes a pixel section 11 including a pattern of pixels arranged in a matrix, and a circuit pattern including a vertical driving circuit for supplying a driving pulse and a bias voltage to the pixel matrix. The vertical driving units 12a and 12b are separately arranged on both sides of the pixel unit 11. Further, a transfer unit 14 including a pattern such as a transfer switch element for transferring the signal charges of the image light photoelectrically converted by the pixel matrix to the storage capacitor, and the charges of the optical output signal and the dark output signal stored in the storage capacitor Are horizontally arranged in parallel on one side of the pixel section 11, that is, on the upper side in the drawing, including a pattern such as a horizontal scanning circuit for sequentially discharging the pixels outside the element. The transfer unit 14
A pattern for forming a storage capacitor is not provided between the horizontal driving unit 15 and the horizontal driving unit 15.
A storage capacitor is formed in a region between the transfer unit 14 and the horizontal drive unit 15 using the reticle.

Further, a vertical reset unit 13 including a pattern for forming a vertical reset element, a constant current circuit, and the like is arranged on the other side of the pixel unit 11, that is, on the lower side in the figure. Further, a light-shielding band 16 for defining a chip size is provided on the outer periphery of each pattern portion as described above.

The reticle shown in FIG. 2 has a storage capacitor portion 21 including a pattern for forming a storage capacitor for storing an optical signal charge and a dark signal charge from a pixel, respectively, and a light-shielding band for defining a chip size. 21. In the present embodiment, the storage capacitor unit 21 is arranged at a substantially central portion of the reticle, and is configured so that the storage capacitor can be formed using a central portion of the projection screen of the reduced projection exposure apparatus with relatively little distortion. .

FIG. 3 shows the pattern of the storage capacitor section 21 shown in FIG. 2 in detail. As can be seen from FIG. 3, the storage capacitor section 21 has the same number of rectangular circuit patterns 31, 32, 33,... For forming the electrodes of the storage capacitor as the number of pixels in the horizontal direction of the pixel matrix.

The reticle having the structure shown in FIGS. 1 to 3 is different from the reticle of the conventional method shown in FIG. 9 in that the storage capacitor portion 21 is separated from the pattern of other circuit portions, and The point is that only one storage capacitor electrode is provided on the reticle for the pixel.

In the method of manufacturing the solid-state imaging device according to the first embodiment using the reticle having the above-described configuration, a process of forming an electrode and a conductive layer of polycrystalline silicon will be described. It is the same as the prior art until the photosensitive photoresist is applied after the polycrystalline silicon is formed. Thereafter, the first reticle shown in FIG. 1 is aligned with the underlying layer on the wafer and exposed using a reduction projection exposure apparatus.

Next, the reticle is exchanged with the second reticle shown in FIG. 2, alignment is performed with respect to the underlying layer on the wafer, and, for example, a region serving as an electrode of the optical signal storage capacitor CTS is exposed. Further, the wafer stage is moved by a certain offset amount, and an area to be an electrode of the dark signal charge storage capacitor CTD is exposed using the same second reticle. After such exposure, the polycrystalline silicon layer is patterned according to the pattern exposed by a known method to form electrodes of each storage capacitor and other conductive layers. In the above-described step of exposing the polycrystalline silicon layer, there is no limitation on the order of using the first and second reticles and the order of exposing the storage capacitors CTS and CTD.

In the method according to the first embodiment as described above, each of the storage capacitors CTS and CTD for one pixel is formed by exposure using the same reticle pattern and the same location in the projection screen of the reduction projection exposure apparatus. Therefore, the variation in capacitance between the storage capacitors CTS and CTD can be greatly reduced as compared with the method of the related art. Therefore, it is possible to obtain a solid-state imaging device capable of almost completely removing solid-state pattern noise.

As the pattern of the storage capacitor section 21 in the reticle of FIG. 2, a pattern in which only the pattern shown in FIG. 10 is independently provided may be used. In this case, 1
Although the storage capacitors CTS and CTD for one pixel are not exposed and formed by the same reticle pattern, the storage capacitors CTS and CTD
The TD exposure forming step and the other conductive layer forming step can be separated. Therefore, the storage capacitors CTS, CTD
Can be optimized. For example, the storage capacitors CTS and CTD can be formed by exposure using a central portion of the projection area of the reduction type projection exposure apparatus where the distortion is small. Therefore, as compared with the prior art, the error in the value of the storage capacitance can be reduced even by such a method, and a higher-performance solid-state imaging device can be obtained.

Next, the step of exposing the polycrystalline silicon layer in the method for manufacturing a solid-state imaging device according to the second embodiment of the present invention will be described. In this embodiment, the reticle shown in FIG. 1 and the reticle shown in FIG. 4 are used. The detailed configuration of the reticle shown in FIG. 1 is as described in the description of the first embodiment, and a description thereof will be omitted.

In the reticle shown in FIG. 4, a storage capacitor portion 41 is disposed substantially at the center of the reticle, and a light-shielding band 42 for defining a chip size is provided around the reticle. The storage capacitor section 41 has a single circuit pattern 51 as shown in FIG.
It consists only of:

The step of exposing the polycrystalline silicon layer in the method for manufacturing a solid-state imaging device using the reticle having the above structure will be described. It is the same as the related art until the photosensitive photoresist is applied after the formation of the polycrystalline silicon layer. Thereafter, the first reticle shown in FIG. 1 is aligned with the underlying layer on the wafer and exposed using a reduction projection exposure apparatus. Next, the reticle is replaced with the second reticle shown in FIG. 4, alignment is performed with respect to the underlying layer on the wafer, and for example, one electrode region of the optical signal storage capacitor CTS is exposed. Further, the wafer stage is moved by a predetermined pixel pitch in the horizontal direction, and the other electrode region of the optical signal storage capacitor CTS is exposed. In this manner, exposure is performed the same number of times as the number of pixels in the horizontal direction of the pixel matrix while sequentially moving the wafer stage.

Next, the wafer stage is moved by a certain offset amount, for example, in the vertical direction or the column direction of the pixel matrix to expose the electrode region of the dark signal storage capacitor CTD.
Further, the wafer stage is moved in the horizontal direction by a predetermined horizontal pixel pitch to expose the electrode area of another storage capacitor CTD. Similarly, exposure is performed while sequentially moving the wafer stage by the same number of times as the number of pixels in the horizontal direction. In this case, there is no particular limitation on the order in which the first reticle and the second reticle are used and the order in which the storage capacitors CTS and CTD are exposed.

In the method according to the second embodiment described above, all the electrodes of the storage capacitors CTS and CTD are exposed using the same pattern on the reticle, and further, using the same portion of the reduction projection exposure apparatus. Therefore, it is possible to completely eliminate factors that cause variations in capacitance in the exposure step, not only in the vertical direction but also in the horizontal direction. For this reason, according to this method, the fixed pattern noise such as the residual vertical stripes FPN can be further significantly suppressed as compared with the method according to the first embodiment.

FIG. 6 is a plan view schematically showing the arrangement of storage capacitors on a wafer formed by the method according to the first or second embodiment. The inside of the rectangle indicated by reference numeral 80 is the active area, in which the respective storage capacitors CTS and CTD are formed. The storage capacitor electrodes made of the polycrystalline silicon layer formed according to the present invention are 81a, 81
, 82a, 82b, 82c,..., for example, the electrodes 81a, 81b, 81c,.
Are electrodes of the dark signal storage capacitor CTD.

An interlayer insulating film (not shown) is formed on the entire surface of the electrodes, and the electrodes 81a, 81b, 81c,.
, 84a, 82a, 82b, 82c,... Through the interlayer insulating film.
, 84b, 84c,. Thereafter, metal wirings 85a, 85b, 85c,.
, 86c,... are patterned, and these metal wirings and polycrystalline silicon electrodes 81a, 81b, 81c,.
2a, 82b, 82c,...

The present invention is not limited to the solid-state image pickup device having the pixel structure shown in FIG. 8, and even if the solid-state image pickup device has a pixel structure as shown in FIG. The present invention can be similarly applied as long as it has a storage capacity for storing. As the pixels used in the solid-state imaging device of FIG. 7, so-called amplification type pixels are used similarly to the pixels used in the solid-state imaging device of FIG.

A solid-state imaging device having the pixel structure shown in FIG. 7 will be described. FIG. 7 shows a pixel matrix configuration of 2 rows × 2 columns for simplification of description and illustration. In practice, more pixels are used. Each pixel includes an embedded photodiode (hereinafter, referred to as BPD) 901 for performing photoelectric conversion, a junction field-effect transistor (hereinafter, referred to as JFET) 904, and a P-channel M
OSFET (hereinafter referred to as TG) 902, P-channel M
An OSFET (hereinafter referred to as RSG) 903 is used.

The cathode of the BPD 901 is connected to a predetermined power supply terminal 905. The TG 902 has a main current path connected between the anode of the BPD 901 and the gate of the JFET 904, and transfers the charge photoelectrically converted by the BPD 901 to the gate of the JFET 904. The RSG 903 is for initializing the gate of the JFET 904, and its main current path is connected between the gate of the JFET 904 and the line 909 from the vertical scanning circuit 906. The JFET 904 is a junction FET for amplifying the charge photoelectrically converted by the BPD 901.
The source is commonly connected to the vertical source line 910, and the drain is connected to the power supply 905.

The vertical scanning circuit 906 is a circuit for selecting a pixel for each row of the pixel matrix and supplying a desired driving pulse. The vertical scanning circuit 906 outputs the TG 902
And a gate line 907 for driving the TG 902, a gate line 908 connected to the gate of the RSG 903, and a JFET 904 via the RSG 903.
(Hereinafter, referred to as RSD) 909 for controlling the gate potential of each pixel, and these lines are commonly connected to the pixels in each row.

The vertical source line 910 is provided for each column, and the source of the JFET 904 in each column is commonly connected to each column. One of the vertical source lines 910 has a bias current source 912 and a vertical source line reset MOS.
It is connected to the FET 911. The vertical source line reset MOSFET 911 outputs a vertical reset pulse φRS
Driven by the TV, the vertical source line 910 is reset to a predetermined vertical reset voltage VRSTV.

The other of the vertical source lines 910 includes an optical signal, a transfer MOSFET 913 (hereinafter, referred to as QTS), and a dark signal transfer MOSFET 914 (hereinafter, QTD).
) Of the main current path. The gates of the QTS in each column are commonly connected to a gate line 915 and driven by a transfer control pulse φTS, while the QTS in each column is
The gates of the TDs 914 are commonly connected to a gate line 916 and driven by a transfer control pulse φTD.

The other ends of the main current paths of QTS 913 and QTD 914 are connected to an optical signal storage capacitor 917 (hereinafter, referred to as CTS) and a dark signal storage capacitor 918 (hereinafter, referred to as CTD). Also, CTS917 and C
TD918 is a MOSFET 919 for horizontal selection,
920 (hereinafter referred to as QTS and QTD) are connected to an optical signal read line 924 and a dark signal read line 925, respectively. QTS and QTD are controlled by the horizontal scanning circuit 923.

In the solid-state imaging device shown in FIG.
The optical signal and the dark signal amplified by the FET 904 pass through the vertical source line 910 and
CTS917 and CTD respectively via TD914
918. The signals accumulated in the CTS 917 and the CTD 918 are capacitance-divided and output to the optical signal read line 924 and the dark signal read line 925 via QTS 919 and QTD 920 which are turned on under the control of the horizontal scanning circuit 923.

Each of the capacitance-divided signals is supplied to an output amplifier 92.
8, 929, the light signal output VOS and the dark signal output VOD are output to the outside of the device. Optical output signal VOS
The dark signal output VOD is subjected to a difference process by a subtraction circuit or the like (not shown) to obtain an image signal in which fixed pattern noise is suppressed. The potentials of the optical signal readout line 924 and the dark signal readout line 925 are set such that the horizontal reset MOSFETs 926, 9
Reset by 27.

[0075]

As described above, according to the present invention, in a solid-state imaging device having a plurality of storage capacitors for storing signal charges from a photoelectric conversion element, it is possible to almost completely eliminate variations in storage capacitors. it can. Therefore, fixed pattern noise such as vertical stripes FPN generated due to the variation in the storage capacity is almost completely suppressed, and a high-quality captured image can be obtained. That is, the present invention has an excellent effect in suppressing fixed pattern noise by performing differential processing on signals corresponding to signal charges stored in a storage capacitor in a solid-state imaging device or the like using an amplification type photoelectric conversion element. Obtainable.

[Brief description of the drawings]

FIG. 1 is a schematic plan view showing a configuration of a first reticle used in a method for manufacturing a solid-state imaging device according to first and third embodiments of the present invention.

FIG. 2 is a diagram illustrating a second example of the method for manufacturing the solid-state imaging device according to the first embodiment of the present invention, which is used together with the reticle of FIG.
FIG. 3 is a schematic plan view showing a configuration of a reticle.

FIG. 3 is an enlarged plan view showing details of a circuit pattern portion of a second reticle shown in FIG. 2;

FIG. 4 is a schematic plan view illustrating a configuration of a second reticle used in a method for manufacturing a solid-state imaging device according to a second embodiment of the present invention.

5 is an enlarged plan view showing a circuit pattern of a second reticle shown in FIG.

FIG. 6 is a schematic plan view showing a configuration of a storage capacitor portion formed on a wafer.

FIG. 7 is a schematic electric circuit diagram showing a circuit configuration of a solid-state imaging device that can be manufactured by a method according to the present invention.

FIG. 8 is an electric circuit diagram showing a circuit configuration of a general solid-state imaging device.

FIG. 9 is a schematic plan view showing a circuit pattern of a reticle used in a method of manufacturing a solid-state imaging device according to the related art.

10 is a schematic plan view showing a circuit pattern of a storage capacitor section of the reticle shown in FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 Pixel part 12a, 12b Vertical drive part 13 Vertical reset part 14 Transfer part 15 Horizontal drive part 16, 22, 42 Light-shielding band 21, 41 Storage capacitance part 31, 32, 33, ..., 51 Storage capacitance circuit pattern 80 Active area 81a , 81b, 81c, ..., 82a, 82b, 82
c,... storage capacitor electrodes 83a, 83b, 83c,.
c, through holes 85a, 85b, 85c, ..., 86a, 86b, 86
c, ... metal wiring

Claims (7)

[Claims] 1. A method of manufacturing a solid-state imaging device including a plurality of storage capacitors each storing a signal charge from a photoelectric conversion element, comprising: forming an electrode of the storage capacitor; Forming a conductive layer other than the electrode of the storage capacitor, the method being separated into separate steps. 2. The semiconductor device according to claim 1, wherein the electrode of the storage capacitor and a conductive layer other than the electrode of the storage capacitor formed of the same layer as the electrode of the storage capacitor are formed using a different mask. 2. The method for manufacturing a solid-state imaging device according to item 1. 3. A storage device comprising first and second groups of storage capacitors for storing dark signal charges and optical signal charges of a photoelectric conversion element, respectively, wherein the charges stored in the first and second groups of storage capacitors are provided. A method of manufacturing a solid-state imaging device that performs a differential processing of a corresponding signal, wherein the storage capacitor of the first group and the storage capacitor of the second group are formed in different steps and using the same mask. A method for manufacturing a solid-state imaging device. 4. The formation of the electrodes of the first group of storage capacitors and the second group of storage capacitors is performed in a separate step from the formation of a conductive layer other than the electrodes formed of the same layer as the electrodes. The method for manufacturing a solid-state imaging device according to claim 3. 5. A storage device comprising first and second groups of storage capacitors for storing dark signal charges and optical signal charges of a photoelectric conversion element, respectively, wherein the charges stored in the first and second groups of storage capacitors are provided. A method for manufacturing a solid-state imaging device that performs differential processing of corresponding signals, wherein the formation of each storage capacitor of the first and second groups of storage capacitors is performed in a separate process and using the same mask. A method for manufacturing a solid-state imaging device, comprising: 6. A plurality of photoelectric conversion elements arranged in a matrix composed of rows and columns, a plurality of vertical signal output lines to which outputs of the photoelectric conversion elements of each column are connected, and a respective vertical signal output line. And first and second storage capacitors provided for each column for storing dark signal charges and optical signal charges, the first and second storage capacitors being provided for each column. And a horizontal selection drive circuit for sequentially selecting and connecting to the dark signal output line and the optical signal output line, wherein the first storage capacitor and the second storage capacitor are connected to each other. Forming a conductive layer other than the first and second storage capacitors in the same layer as the electrodes of the first and second storage capacitors in a separate step; Storage capacity using the same mask Method for manufacturing a solid-state imaging device and forming. 7. A plurality of photoelectric conversion elements arranged in a matrix consisting of rows and columns, a plurality of vertical signal output lines to which outputs of the photoelectric conversion elements in each column are connected, and each vertical signal output line. And first and second storage capacitors provided for each column for storing dark signal charges and optical signal charges, the first and second storage capacitors being provided for each column. And a horizontal selection drive circuit for sequentially selecting the first storage capacitor and connecting to the dark signal output line and the optical signal output line, wherein each of the first storage capacitors and the second storage Forming each of the capacitors and a conductive layer other than the first and second storage capacitors in the same layer as the electrodes of the first and second storage capacitors in separate steps; The capacity and the second storage capacity are the same Method for manufacturing a solid-state imaging device, and forming using click.