JPH1039958A - Reset device - Google Patents

Abstract

(57) [Problem] To provide a reset device which can cope with a plurality of types of reset input signals and executes different reset operations according to the types of these reset input signals. I do. Kind Code: A1 A reset device for causing a microcomputer application device to perform a reset operation, a type storage means for storing a correspondence between a plurality of types of reset operations and a plurality of types of reset input signals, A reset execution unit for instructing the microcomputer application apparatus to execute a reset operation of a pattern corresponding to the type of the input reset input signal based on the relationship;

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reset device for stopping and restarting processing operations (hereinafter, referred to as reset operations) in a microcomputer (hereinafter abbreviated as a microcomputer) application device.

[0002]

2. Description of the Related Art A reset device is mounted on, for example, a microcomputer application device such as a personal computer or a workstation, and performs a reset operation for the microcomputer application device. The microcomputer here is an LSI (Larg) called a microprocessor.
e Scale Integration), ROM (Read OnlyM)
emory) and RAM (Random Access Memory)
It is an ultracompact computer made using SI and IC (Integrated Circuit).

Conventionally, in a reset device, when an external reset input signal is input to the reset device,
The reset operation is forcibly executed regardless of the state of the microcomputer application device in which the reset device is mounted. Separately from this, for example, an operation of writing a program, data, or the like (hereinafter, simply referred to as information) (hereinafter, referred to as a write) is performed on storage means that the microcomputer application device has as a main memory or a cache memory. In some reset devices, even if a reset input signal is input, the reset operation is postponed until the write is completed, and the reset operation is performed after the write is completed.

[0004]

In the above-mentioned reset device for forcibly executing a reset operation, for example, a reset input signal is input to a microcomputer application device while information is being written to storage means. , The reset operation is executed even during the writing. Therefore, in this case, the information may not be correctly written to the storage unit. Therefore, when the processing operation in the microcomputer application device is restarted after the reset operation, it must be performed from the initialization of the storage unit. Therefore, much time is required until the processing operation is restarted.

In a reset device that executes a reset operation after the end of writing, the reset operation is not executed until the end of the writing. Therefore, the writing does not end or the end of the writing is detected due to a trouble during the writing. If not, the reset operation will not be performed. That is, in these conventional reset devices,
Since only one type of reset input signal is input and one type of reset operation for the reset input signal, a long time is required to resume the processing operation after the reset operation, or the reset operation is not performed. Such a problem occurs. for that reason,
The reset device and the microcomputer application device equipped with the reset device may be inconvenient for the user (user).

Accordingly, the present invention has been made in view of the above problems,
It is an object of the present invention to provide a reset device that can respond to a plurality of types of reset input signals and executes different reset operations according to the types of these reset input signals.

[0007]

SUMMARY OF THE INVENTION The present invention is a reset device devised to achieve the above-mentioned object, comprising a storage means capable of writing and reading information, and a storage device based on the information in the storage means. And a control unit for performing a predetermined processing operation. The processing unit is configured to cause the processing device to stop and restart the processing operation as a reset operation. Receiving signal input means, type storage means for storing a correspondence relationship between a plurality of preset reset operations and the plurality of types of reset input signals, and storing the type when the signal input means receives a reset input signal. Instructing the processing device to execute a reset operation of a pattern corresponding to the type of the received reset input signal based on the correspondence stored in the means. Comprising a reset execution unit.

According to the configuration of the reset device having the above configuration,
When the signal input unit receives the reset input signal, the reset execution unit instructs the processing device equipped with the reset device to execute a reset operation. At this time, the reset execution unit determines a reset operation pattern corresponding to the type of the reset input signal from a plurality of preset patterns based on the correspondence stored in the type storage unit. Therefore, if the type storage means stores the correspondence between the plurality of types of reset operation and the plurality of types of reset input signals, the reset execution means respectively sets the type of the reset input signal received by the signal input means. This causes the processing device to execute a reset operation of a different pattern.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a reset device according to the present invention will be described with reference to the drawings. The reset device according to the present embodiment is mounted on the microcomputer application device 1 as shown in FIG. However, the microcomputer application device 1 includes a storage unit 2 and a control unit 3 in addition to the reset device 10.

The storage section 2 functions as storage means in the present invention, and comprises, for example, a RAM. That is, the storage unit 2 stores information necessary for processing operations performed by the microcomputer application device 1. In the storage unit 2, information can be written and read at any time (hereinafter, referred to as read), and information is written according to a write signal 3a from the control unit 3, which will be described later. ing.

The control section 3 functions as control means in the present invention, and includes, for example, a microprocessor and its peripheral circuits. That is, the control unit 3
Controls the entire microcomputer application device 1 and performs a predetermined processing operation based on information stored in the storage unit 2. In addition, the control unit 3 writes information necessary for performing a predetermined processing operation to the storage unit 2 in order to retrieve the information from, for example, a program ROM (not shown) and store the information in the storage unit 2. (Hereinafter, outputting a signal is referred to as an assertion).

The reset device 10 mounted on such a microcomputer application device 1 includes a light monitoring unit 11 and a reset input execution unit 12. The write monitoring unit 11 functions as a monitoring unit in the present invention, and when information is written to the storage unit 2 of the microcomputer application device 1, determines whether or not the writing has been completed. For this purpose, the write monitoring unit 11 writes the write signal 3a asserted from the control unit 3 to the storage unit 2.
When the write signal 3a is asserted, a write-in-progress signal 11a is asserted to the reset input execution unit 12, and the output of the write signal 3a ends (hereinafter, negating that the output of the signal ends). Then, the in-write signal 11a is negated. That is,
The write monitoring unit 11 notifies the reset input execution unit 12 that the storage unit 2 is currently writing and that the writing has ended by the writing-in-progress signal 11a.

The reset input execution section 12 has functions as signal input means and reset execution means in the present invention. That is, the reset input execution unit 1
2 receives the reset input signal 12a sent from an external circuit (not shown) (for example, a reset switch circuit), and receives the control unit 3 and the light monitoring unit 11 of the microcomputer application device 1.
The reset output signal 12b is asserted to instruct the microcomputer application apparatus 1 to execute a reset operation.

However, the reset input execution section 12 can instruct a reset operation of a plurality of patterns. Examples of the plurality of patterns include a pattern in which the reset operation is executed after the write is completed by the write monitoring unit 11 when the write monitoring unit 11 is writing, and a pattern in which the reset operation is executed even in the middle of the write.
Further, there are some patterns depending on the difference in the assertion destination of the reset output signal 12b. The reset input execution unit 12 includes, for example, “RESET0” to “RESE”.
Tn ", a plurality of types of reset input signals 12
a can be input.

Further, the reset input execution section 12 is provided with a reset type storage section 13. The reset type storage unit 13 functions as a type storage unit in the present invention, and corresponds to a relationship between a preset plurality of reset operations and the type of the reset input signal 12a input to the reset input execution unit 12. Is stored.

For example, according to the correspondence stored in the reset type storage unit 13, "RESET0" to "RESETm"
As a reset operation pattern for (0 ≦ m ≦ n), a pattern in which the reset output signal 12b is asserted to each unit regardless of the writing signal 11a corresponds to “RESETm”.
A pattern in which the reset output signal 12b is asserted after the writing signal 11a is negated corresponds to the reset operation pattern for "+1" to "RESETn". The reset type storage unit 13 stores “RESET0” to “RESE”.
The assertion destination of the reset output signal 12b is stored as a correspondence for each type of “Tn”.

An example of the operation when the reset device 10 thus configured instructs the microcomputer application device 1 to perform a reset operation will be described with reference to the flowchart of FIG. In the reset device 10, when an external circuit outputs a reset input signal 12a, the reset input execution unit 12 receives the reset input signal 12a (Step 101; hereinafter, step is abbreviated as S).

At this time, the reset input execution unit 12 identifies the type of the received reset input signal 12a (S102), and refers to the correspondence stored in the reset type storage unit 13 to refer to the correspondence. It is determined whether or not the type of the identified reset input signal 12a is present (S103). If any of the correspondences are applicable,
The reset input execution unit 12 determines a reset operation pattern corresponding to the type of the received reset input signal 12a based on the correspondence (S104). If there is no corresponding one, an alarm or the like is issued without processing the reset operation instruction.

After determining the reset operation pattern, the reset input execution unit 12 sends a reset output signal 12b to the control unit 3 and the write monitoring unit 11 of the microcomputer application device 1 according to the determined reset operation pattern. Assert (S105). Then, the microcomputer application device 1 executes a reset operation according to the reset output signal 12b asserted from the reset input execution unit 12.

As described above, the reset device 10 instructs the microcomputer application device 1 to perform different reset operations in accordance with the type of the reset input signal 12a. Thus, in the reset device 10, for example, if the storage unit 2 is performing a write operation, the reset operation is performed after the end of the write operation, or the reset operation is performed even during the write operation. It can be changed depending on the type of the input signal 12a. Further, for example, depending on the type of the reset input signal 12a, it is possible to instruct the reset operation only to a specific block among the functional blocks in the microcomputer application device 1. Furthermore, if the reset input execution unit 12 asserts different types of reset output signals 12b, the control unit 3 of the microcomputer application device 1 executes different types of reset processing depending on the types of the reset input signals 12a. Become like

Next, as a more specific embodiment,
A case will be described in which the reset device according to the present invention is mounted on an electronic switching device for performing a telephone line switching business. As shown in FIG. 3, the electronic switching device equipped with the reset device of the present invention includes a static RAM 21, a microprocessor 22, a function realizing circuit 23, a peripheral circuit 24, and a reset input executing circuit 25. Is what it is.

The static RAM 21 corresponds to the storage unit 2 of the microcomputer application device 1 described above. The microprocessor 22, the function realizing circuit 23, and the peripheral circuit 24 correspond to the control unit 2 of the microcomputer application device 1 described above. The microprocessor 22 includes, for example, MC68030 or MC68040 manufactured by Motorola of the United States, and controls the entire electronic exchange. Also, the function realizing circuit 23
Is for realizing, for example, a switch function for connecting a telephone line and a signal processing function of a layer. Further, the peripheral circuit 24 is a circuit necessary for the operation of the microprocessor 22 and the function realizing circuit 23. The write signal 3a, information read from the static RAM 21, and the like are used as control signals between the peripheral circuit 24 and the static RAM 21. It is designed to interact.

The peripheral circuit 24 corresponds to the write monitoring unit 11 of the reset device 10 described above.
The reset input execution circuit 25 is notified that the static RAM 21 is currently writing or that the writing is completed. Reset input execution circuit 25
Is the reset input execution unit 1 of the reset device 10 described above.
This is equivalent to 2.

However, the reset input execution circuit 25 has a power-on reset (hereinafter abbreviated as PONRST) signal and a maintenance reset (hereinafter abbreviated as MRST) 0 as the reset input signal 12a. A signal and an MRST1 signal are input. In response to these inputs, the reset input execution circuit 25 inputs the PONRST signal, the MRST
0 signal input, MRST1 signal input, MRST0 signal and MRST1
Four types of simultaneous input with a signal are identified, and this is indicated by a flag.

Further, in the reset input execution circuit 25, a reset (hereinafter, referred to as a reset output signal 12b) is performed.
RESET) signal and an all reset (hereinafter called ALLRST)
) Signal and a part reset (hereinafter, referred to as PRTRST) signal are respectively asserted. The RESET signal is a reset output signal 12b for causing the microprocessor 22 and the peripheral circuit 24 to execute a reset operation. The ALLRST signal is a reset output signal 12b for executing a reset operation on a specific part set in advance in the function realizing circuit 23. The PRTRST signal is sent to the ALLR
This is a reset output signal 12b for causing a reset operation to be performed on a portion where the reset operation is not performed by the ST signal.

The PONRST signal, the MRST0 signal, and the MRST1 signal, the RESET signal, the ALLRST signal, and the PRTRST signal
Each signal has a correspondence as shown in FIG. Note that this correspondence is determined by the reset input execution circuit 2
5 is stored. According to this correspondence, when the PONRST signal is input and when the MRST0 signal is input, regardless of the assertion / negation of the writing signal 11a, the RESET signal, ALLRST signal, PR
The TRST signal is unconditionally asserted. If the write signal 11a is asserted when the MRST1 signal is input, the RESET signal and the ALLRST signal are not asserted, and the RESET signal and the ALLRST signal are asserted after the write signal 11a is negated. When the MRST0 signal and the MRST1 signal are input simultaneously, the MRST0 signal
Assume that the RESET signal, ALLRST signal, and PRTRST signal are asserted in the same manner as when the signal is input.

Here, the PONRST signal input, the MRST0 signal input, the MRST1 signal input, or the simultaneous input of the MRST0 signal and the MRST1 signal is performed on the reset input execution circuit 25 by the electronic exchange. Will be described.

When the PONRST signal is input to the reset input execution circuit 25, the RESET signal, the ALLRST signal, and the PRTRST signal are asserted from the reset input execution circuit 25 regardless of the assertion / negation of the writing signal 11a. The microprocessor 22, the function realizing circuit 23, and the peripheral circuit 24 stop the processing operation being performed at that time. Thereafter, the microprocessor 22 reads information from a program ROM or the like (not shown) based on the flag when the reset input execution circuit 25 identifies the PONRST signal, and writes the information to the static RAM 21. Then, based on the information written in the static RAM 21, the microprocessor 22 diagnoses each unit in the electronic exchange, and then restarts the electronic exchange. That is, this is the same reset operation as when the power is turned on.

When the MRST0 signal is input to the reset input execution circuit 25, the microprocessor 22, the function realizing circuit 23, and the peripheral circuit 24 stop the processing operation as in the case where the PONRST signal is input. Then, the microprocessor 22 writes the information read from the program ROM or the like into the static RAM 21 based on the flag when the reset input execution circuit 25 identifies the MRST0 signal, and restarts the electronic exchange. However, in this case, the microprocessor 22 does not diagnose each unit in the electronic exchange.

When the MRST1 signal is input to the reset input execution circuit 25, the RESET signal and the ALLRST signal are asserted after the writing signal 11a is negated.
The microprocessor 22, the specific part of the function realizing circuit 23, and the peripheral circuit 24 stop the processing operation after the writing to the static RAM 21 is completed. Then, the microprocessor 22 determines that the reset input execution circuit 25
The electronic exchange device is restarted based on the information already written in the static RAM 21 based on the flag when the MRST1 signal is identified.

That is, when the MRST1 signal is input,
Since the PRTRST signal is not asserted, the function realizing circuit 23
The reset operation is not executed in the part other than the specific part of the above. Therefore, for example, if the reset operation for the switch function for connecting the telephone line is set so as to be executed by the PRTRST signal, the function realizing circuit 23 can execute the reset input executing circuit 25 even if the MRST1 signal is input to the reset input executing circuit 25. This eliminates the possibility of disconnecting the connected telephone line without performing the reset operation for the switch function. Therefore, when the MRST1 signal is input, the restart of the electronic exchange can be performed in a shorter time.

MRST0 for the reset input execution circuit 25
When the signal and the MRST1 signal are input simultaneously, the microprocessor 22, the function realizing circuit 23, and the peripheral circuit 24
Stops the processing operation as in the case where only the MRST0 signal is input. Then, the microprocessor 22 executes the program RO based on the flag when the reset input execution circuit 25 identifies the simultaneous input of the MRST0 signal and the MRST1 signal.
The maintenance program stored in the M or the like is read, and the system waits for an instruction from a higher-level device connected to the electronic exchange.

As described above, when the reset device according to the present invention is mounted on the electronic exchange, the electronic exchange performs reset operations of different patterns according to the type of the reset input signal 12a. It has become. Thereby, in this electronic exchange device, for example,
It takes a lot of time to restart the processing operation after the reset operation,
Alternatively, the problem that the reset operation is not executed can be solved. In other words, even when the electronic exchange device is mounted on the electronic exchange device, the electronic exchange device can cause the electronic exchange device to execute the reset operation in a shorter time, and can reliably execute the reset operation.
As a result, the usability can be improved as compared with the related art.

In the above embodiment, the case where the reset device is mounted on the electronic exchange has been described in detail, but the present invention is not limited to this. That is, the reset device according to the present invention may be mounted on, for example, a personal computer or a workstation, and even in this case, the same effect as when mounted on an electronic exchange device can be obtained.

In the above-described embodiment, the PONRST signal, the MRST0 signal, and the MRST1 signal are input as the reset input signal 12a, and the RESET signal, the ALLRST signal, and the PRTRST signal are asserted as the reset output signal 12b. Although the case has been described, for example, the present invention can be applied to a case in which signals corresponding to different types are used or the above-described signals are arbitrarily combined.

[0036]

As described above, the reset device according to the present invention is based on the correspondence stored in the type storage means.
According to the type of the reset input signal received by the signal input unit, the reset execution unit causes the processing device to execute a reset operation of a different pattern. Therefore, in this reset device, when a reset operation is performed on a processing device equipped with the reset device,
It takes a lot of time to restart the processing operation after the reset operation,
Alternatively, it does not occur that the reset operation is not reliably executed. That is, it is possible to cause the processing device to execute the reset operation in a shorter time or to execute the reset operation reliably, and as a result, there is an effect that the usability is improved as compared with the related art.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a functional configuration of an example of an embodiment of a reset device according to the present invention.

FIG. 2 is a flowchart showing an operation example when the reset device of FIG. 1 instructs a microcomputer application device equipped with the reset device to perform a reset operation.

FIG. 3 is a block diagram showing a schematic configuration when a reset device according to the present invention is mounted on an electronic exchange.

FIG. 4 is an explanatory diagram showing a correspondence relationship between types of reset input signals stored in the reset device of FIG. 3 and patterns of a reset operation.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 microcomputer application device (processing device) 2 storage unit (storage unit) 3 control unit (control unit) 10 reset device 11 write monitoring unit (monitoring unit) 12 reset input execution unit (signal input unit, reset execution unit) 13 reset type Storage unit (type storage means)

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Ken Takeshi 3-192-2 Nishi-Shinjuku, Shinjuku-ku, Tokyo Inside Nippon Telegraph and Telephone Corporation (72) Inventor Naoya Ozawa 3-192, Nishi-Shinjuku, Shinjuku-ku, Tokyo No. Japan Telegraph and Telephone Corporation

Claims (2)

[Claims] An information processing apparatus comprising: a storage unit capable of writing and reading information; and a control unit configured to perform a predetermined processing operation based on information in the storage unit. What is claimed is: 1. A reset device for stopping and restarting an operation as a reset operation, comprising: signal input means for receiving a plurality of types of reset input signals; and a reset operation of a plurality of preset patterns and the plurality of types of reset input signals. A type storage unit for storing a correspondence relationship; and a reset operation of a pattern corresponding to the type of the received reset input signal based on the correspondence relationship stored in the type storage unit when the signal input unit receives a reset input signal. And a reset executing means for instructing the processing device to execute the processing. 2. A monitoring means for determining whether or not the writing has been completed when information has been written to the storage means, and a pattern of the reset operation instructed by the reset execution means may be used as the reset operation pattern. A pattern instructing execution of a reset operation after the monitoring means determines that the writing has been completed when information has been written to the means,
2. The reset device according to claim 1, wherein a pattern instructing execution of a reset operation regardless of a result of the determination by the monitoring unit is set in advance.