JPH1039329A - Matrix type array substrate of liquid crystal display device and its production - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to suppress the occurrence of the defect which arises during the course of an array forming stage by forming gate wirings by using transparent conductive materials, then connecting these gate wirings and shorting rings to each other by nonlinear elements. SOLUTION: Resistors consisting of the transparent conductive materials and resistors consisting of the nonlinear elements 5 as first conductive thin films 4 are formed on shorting terminals 3a for electrically connecting the respective wirings of the source wirings and the gate wirings and the shorting rings. Namely, the first conductive thin films 4 are so formed as to connect the shorting ring terminals 3a to the ends of the gate wirings 2. Further, the nonlinear elements 5 are so formed as to connect the shorting ring terminals 3a to the ends of the source wirings 1. The source wrings and the gate wirings are conducted to the shorting rings disposed in the outer peripheral parts of the display section juxtaposed with both wirings so as to be respectively paralleled with each other.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a matrix type array substrate used for a matrix type liquid crystal display device and a method of manufacturing the same.

[0002]

2. Description of the Related Art A matrix type liquid crystal display device generally has
A display material such as liquid crystal is sandwiched between two opposing substrates, and a voltage is selectively applied to the display material. At least one of the substrates is called a matrix type array substrate (hereinafter, may be simply referred to as an array substrate). On this array substrate, a switching element such as a thin film transistor and a source wiring for supplying a signal to the switching element are provided. And gate wirings are formed in an array. However, since the array substrate is often an insulating substrate such as glass, a defect relating to the source wiring and the gate wiring caused by static electricity generated during the process, for example, insulation between the source wiring and the gate wiring due to static electricity. It had a disadvantage that a destructive short circuit or the like was easily generated.

Usually, as a means for overcoming these drawbacks, a low-resistance wiring called a short ring wiring (hereinafter, also simply referred to as a short ring) is arranged around the array substrate, and the low-resistance wiring is provided. By using a low-resistance body made of chromium, aluminum, or the like, electrical continuity is provided between the source wiring and the source wiring and between the low-resistance wiring and the gate wiring, respectively, so that the wiring of the source wiring and the gate wiring are connected via the short ring. The potential is suppressed. Here, the low resistance means 0.1 to 1
It means a resistance of about 00Ω.

However, the source wiring and the gate wiring are
As described above, since the same potential is intentionally set by the low-resistance short ring, sufficient inspection sensitivity is required for the inspection between the source wiring and the gate wiring, particularly for the short-circuit inspection because the short ring has a low resistance. Was difficult to obtain.

As a method for overcoming these problems, there is, for example, a method disclosed in Japanese Patent Application Laid-Open No. 3-296725. FIG. 8 is a schematic plan view showing the configuration of a wiring on a conventional matrix type array substrate disclosed in the above publication. In FIG. 8, 1 is a source wiring, 2 is a gate wiring, 3 is a short ring, and 5 is a resistor made of a nonlinear element. According to the method disclosed in the above publication, both the source wiring and the gate wiring, and the short ring wiring disposed on the outer periphery are formed of a resistor such as a diode, which is a non-linear element having a non-linear resistance characteristic. Connected by Therefore, this non-linearity is not affected by a voltage of several to several tens of volts applied when performing a short circuit test between each of the source line and the gate line and the short ring line (hereinafter, simply referred to as a short circuit test between the lines). Since the element exhibits a resistance of about several hundred MΩ to several GΩ, that is, shows an almost insulated state, good inspection sensitivity can be obtained in the short-circuit inspection.
However, when a voltage of several hundred volts or more that causes a failure due to static electricity, for example, a breakdown short circuit occurs between source wirings and gate wirings, the nonlinear element acts as a resistor of several tens KΩ or less. At this time, such a resistance of several tens KΩ is a resistance sufficient for discharging static electricity.

On the other hand, as a more detailed inspection method than the conventional short circuit inspection between wirings, there is a charge sensing method, for example, which is an inspection method capable of inspecting a switching element level associated with a pixel. According to this charge sensing method, the connection between the gate wiring and the short ring may be connected with a resistor of several tens of kilohms, but between the source wiring and the short ring is a resistor of several MΩ or more having a higher resistance. It is necessary to connect. Therefore, according to the conventional forming method as described in the above-mentioned publication in which a resistor is formed by a non-linear element, a resistance of several hundred K to several MΩ is applied to a voltage applied during inspection within a range of several to several tens of volts. This is an effective method for carrying out a detailed inspection such as a charge sensing method.

However, a thin film transistor and a diode are usually used as such a non-linear element. Therefore, according to the method of forming a resistor by using such a non-linear element, the non-linear element is formed in a step of forming an array substrate ( Since it is completed as a nonlinear element only near the end of the array forming step), it has a function as a resistor from that time on, but has only a function as an insulator until that time.

Therefore, there is no path for discharging the static electricity generated on the source wiring and the gate wiring in the initial and intermediate stages of the array forming process. The electric charge is accumulated on the upper portion, which causes a failure such as a failure of the switching element and a short circuit between the source wiring and the gate wiring.

Japanese Patent Application Laid-Open No. 3-116117 discloses that
A method has been suggested in which a resistor for connecting each of the source wiring and the gate wiring to the short ring is formed by using a relatively high-resistance material to secure a resistance of several KΩ to several tens KΩ. According to this method of securing a resistance of several kΩ to several tens of kΩ, a necessary resistance value is secured for the above-described short circuit inspection between wirings, but it is required for performing an inspection such as a charge sensing method. Resistance value
Although the resistance value on the gate side is good, the level required for the resistance value on the source side is still small and inadequate because there is still an opening of about one to two digits.

[0010]

As described above, among the conventional matrix type liquid crystal display devices, one in which each of the source wiring and the gate wiring and the short ring wiring are connected by a non-linear element, respectively. There has been a problem that it is not possible to suppress the occurrence of defects due to static electricity generated in a step before the step in which the nonlinear element functions as a resistor. In particular, on the side of the region of the array substrate where the ends of the gate wirings are present (hereinafter simply referred to as the gate side), the gate wirings are often formed at the beginning of the array formation process, and thus are exposed to an insulating state. The length of the period is longer than the side of the region where the end portion of the source wiring exists (hereinafter, simply referred to as the source side), and the rate of occurrence of defects with respect to static electricity is relatively large.

In the case where a resistor is formed of a material having a relatively high resistance such as ITO (Indium Tin Oxide), a detailed array inspection such as a charge sensing method is performed, and particularly, a resistor is formed on the source side. The connected resistance value was insufficient.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and it is possible to reduce the occurrence of defects due to static electricity in the course of a process, particularly the occurrence of defects due to static electricity generated on a gate wiring, and to perform a detailed array inspection. It is an object of the present invention to provide a liquid crystal display device comprising a matrix type array substrate using a resistor having a sufficient resistance value, particularly a source side, having a sufficient resistance value.

[0013]

In a matrix type liquid crystal display device according to the present invention, a resistor for connecting a gate wiring and a short ring is formed of a first conductive material using the same transparent conductive material as a material for forming a pixel electrode. Is formed at the beginning of the array forming process, while the source wiring formed at the end of the array forming process is formed with a short ring by a resistor made of a nonlinear element.

Further, as for the resistor for connecting the gate wiring and the short ring, in addition to the resistor formed from the beginning of the array forming process, a nonlinear element is also formed in the same manner as on the source side. The resistive element existing from the beginning of the array forming step can be eliminated by etching or the like.

In the matrix type array substrate configured as described above, not only the occurrence of defects due to static electricity during the process can be reduced, but also the resistance value for connecting the gate wiring and the short ring is variously set. (Hereinafter simply referred to as “array inspection”), the sensitivity can be increased to a level at which sufficient sensitivity can be given, which leads to improvement in inspection sensitivity.

The matrix type array substrate of the liquid crystal display device according to the present invention comprises: a transparent insulating substrate; a plurality of gate wirings arranged in parallel on the insulating substrate; a gate insulating film covering the gate wirings; A plurality of source wirings arranged side by side so as to intersect the plurality of gate wirings via the gate insulating film, thin film transistors provided at intersections of the source wirings and the gate wirings, and connection to the thin film transistors A pixel electrode made of a transparent conductive material, and a short ring wiring provided at an outer portion of a region where the source wiring and the gate wiring are respectively arranged in parallel to make the source wiring and the gate wiring have the same potential; A non-doped amorphous silicon layer covering the upper part of the region where the short ring wiring is formed, an etching stopper insulating film and And a phosphorus-doped amorphous silicon layer, and an extension of the source wiring and a drain electrode line provided on the phosphorus-doped amorphous silicon layer. Short ring wiring and first
And the source wiring and the short ring wiring are connected via a non-linear element having a non-linear resistance characteristic.

Further, it is preferable that the first conductive thin film is made of the transparent conductive material, since the resistance required for inspection can be secured without increasing the number of manufacturing steps.

Also, the same first conductive thin film as the first conductive thin film may be used.
A conductive thin film is further arranged in parallel with the non-linear element to connect the source wiring and the short ring wiring,
It is preferable that at least a portion of the first conductive thin-film resistor be removed in the step of manufacturing the matrix-type array substrate in that the sensitivity of the inspection can be improved.

Further, the short ring wiring on the side connected to the gate wiring and the short ring wiring on the side connected to the source wiring may be connected by a second conductive thin film. This is preferable in that the influence of the gate potential on the source side can be reduced and the sensitivity of inspection can be increased.

Further, it is preferable that the second conductive thin film is made of the transparent conductive material in that the number of manufacturing steps is not increased.

The short ring wiring connected to the gate wiring and the short ring wiring connected to the source wiring are connected by the same nonlinear element as the nonlinear element. Is preferable in that the wraparound of the gate potential can be minimized and the inspection sensitivity can be extremely increased.

In the matrix type liquid crystal display device according to the present invention, a transparent insulating substrate, a plurality of gate wirings juxtaposed on the insulating substrate, a gate insulating film covering the gate wirings, A plurality of source wirings arranged side by side so as to intersect with the gate wiring via the gate insulating film, thin film transistors respectively provided at intersections of the source wirings and the gate wirings, and connected to the thin film transistors; A pixel electrode made of a transparent conductive material, a short ring wire provided outside the region where the source wire and the gate wire are arranged side by side to make the source wire and the gate wire have the same potential; Non-doped amorphous silicon layer and phosphorus-doped amorphous silicon A matrix type array substrate of a liquid crystal display device, comprising: a source layer provided on the phosphorus-doped amorphous silicon layer; and an extension of the source wiring and a drain electrode line, wherein the gate wiring, the short ring wiring, Are connected via a first conductive thin film, and the source wiring and the short ring wiring are connected via a non-linear element having a non-linear resistance characteristic.

According to the method of manufacturing a matrix type array substrate of a liquid crystal display device according to the present invention, a transparent insulating substrate, a plurality of gate wirings juxtaposed on the insulating substrate, and a gate insulating film covering the gate wirings A plurality of source lines arranged in parallel so as to intersect the plurality of gate lines with the gate insulating film interposed therebetween; a thin film transistor provided at an intersection of the source line and the gate line; A pixel electrode made of a transparent conductive material, and a short ring wiring provided at an outer portion of a region where the source wiring and the gate wiring are arranged in parallel so that the source wiring and the gate wiring have the same potential. A first conductive thin film formed to connect the short ring wiring and the source wiring; and a first conductive thin film. Forming a non-linear element having a non-linear resistance characteristic and formed to connect the short ring wiring and the source wiring, and the first conductive thin film and the non-linear element. A non-doped amorphous silicon layer covering the region,
An etching stopper insulating film and a phosphorus-doped amorphous silicon layer, an extension of the source wiring and a drain electrode line provided on the phosphorus-doped amorphous silicon layer, the phosphorus-doped amorphous silicon layer, the non-doped amorphous silicon layer, and the gate A method for manufacturing a matrix type array substrate of a liquid crystal display device, comprising a contact hole formed in an insulating film,
(A) forming the gate wiring and the short ring wiring on the transparent insulating substrate; (b) forming the first conductive thin film and the non-linear element to form an end of the gate wiring; Connecting a short ring wiring, (c) sequentially forming the gate insulating film, the non-doped amorphous silicon layer, and the etching stopper insulating film, and (d) forming the phosphorus-doped amorphous silicon layer and then forming the phosphorus-doped amorphous silicon layer. Selectively etching the amorphous silicon layer, the non-doped amorphous silicon layer, and the gate insulating film to form the contact hole; and (e) forming the source line, an extension of the source line, and the drain electrode line. (F) an extension of the source line and the drain electrode line Etching a part of the non-doped amorphous silicon layer and a part of the phosphorus-doped amorphous silicon layer as a mask; and (g) forming the pixel electrode. In any one of the steps, the contact hole is formed by etching including at least a part of the first conductive thin film.

According to the method of manufacturing a matrix type array substrate of a liquid crystal display device according to the present invention, a transparent insulating substrate, a plurality of gate wirings juxtaposed on the insulating substrate, and a gate insulating film covering the gate wirings A plurality of source lines arranged in parallel so as to intersect the plurality of gate lines with the gate insulating film interposed therebetween; a thin film transistor provided at an intersection of the source line and the gate line; A pixel electrode made of a transparent conductive material, and a short ring wiring provided at an outer portion of a region where the source wiring and the gate wiring are arranged in parallel so that the source wiring and the gate wiring have the same potential. A first conductive thin film formed to connect the short ring wiring and the source wiring; and a first conductive thin film. Forming a non-linear element having a non-linear resistance characteristic and formed to connect the short ring wiring and the source wiring, and the first conductive thin film and the non-linear element. A non-doped amorphous silicon layer and a phosphorus-doped amorphous silicon layer covering a region; an extension of the source wiring and a drain electrode line provided on the phosphorus-doped amorphous silicon layer; the phosphorus-doped amorphous silicon layer and the non-doped amorphous silicon layer And a contact hole formed in the gate insulating film, comprising: (a) forming the gate wiring and the short ring wiring on the transparent insulating substrate. (B) the first conductive thin film The step of connecting the short ring line and the end portion of the gate line to form a pre said non-linear element, (c) the gate insulating film,
Forming the non-doped amorphous silicon layer in order, (d) forming the phosphorus-doped amorphous silicon layer, and then selectively etching the phosphorus-doped amorphous silicon layer, the non-doped amorphous silicon layer, and the gate insulating film to form the non-doped amorphous silicon layer. Forming a contact hole, (e) forming the source wiring and an extension of the source wiring and the drain electrode line, and (f) forming the non-doped amorphous material using the extension of the source wiring and the drain electrode line as a mask. A step of etching away a part of the silicon layer and a part of the phosphorus-doped amorphous silicon layer; and (g) a step of forming the pixel electrode, wherein any of the steps (d) to (g) is performed. The first conductive thin film in one step of By etching, including at least a portion of, and forming the contact hole.

[0025]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

Embodiment 1 Embodiment 1 of the present invention will be described with reference to FIG. 1 and FIG. FIG. 1 is an explanatory plan view schematically illustrating a matrix-type array substrate according to the first embodiment. FIG. 2 is a diagram illustrating a non-linear element connected to an end of a source wiring shown in FIG. FIG. 2 is an explanatory cross-sectional view showing a contact hole (not shown in FIG. 1) provided for electrically connecting a drain electrode line to a short ring terminal. FIG. 2 is an explanatory cross-sectional view showing a cross section taken along line BB of a region A and a cross section taken along line DD of a region C shown in FIG.
FIG. 2 shows a cross section taken along the line BB on the right side of the broken portion, and a cross section taken on the left side of the broken portion.

In FIG. 1, reference numeral 1 denotes a source wiring;
Is a gate wiring. Reference numeral 3 denotes a short ring formed so as to surround these wirings. Reference numeral 4 denotes a first conductive thin film that connects the gate wiring and the short ring, and the first conductive thin film is a resistor made of a transparent conductive material. Numeral 5 is a non-linear element for connecting the source wiring and the short ring, and is a resistor composed of an element having a non-linear resistance characteristic. In the present embodiment, the short ring and the resistor are connected via the short ring terminal. In FIG. 2, the same parts as those shown in FIG. 1 are denoted by the same reference numerals, 1a is an extension of the source wiring, 3a is a short ring terminal,
6 is a gate insulating film, 7 is a non-doped amorphous silicon layer, 8 is a phosphorus-doped amorphous silicon layer, 9 is a drain electrode line, 10 is an etching stopper insulating film, and 11 is a pixel electrode. , 1
3 is a contact hole. The short ring terminal 3a is extended from the short ring wiring so as to protrude corresponding to each gate wiring and each source wiring.

In the matrix type array substrate according to the present invention, a display material such as a liquid crystal is usually sandwiched between two opposing substrates and a voltage is selectively applied to the display material as in the conventional case. It is configured to
Among them, a transparent insulating substrate as one substrate, a plurality of gate wirings arranged in parallel on the insulating substrate at regular intervals, an insulating film covering the plurality of gate wirings, and a gate via the insulating film A plurality of source wirings each intersecting with the wirings and arranged in parallel and at regular intervals; thin film transistors which are switching elements provided at intersections of the gate wirings and the source wirings; and a transparent conductive material connected to the thin film transistors And a short ring wiring provided on an outer peripheral portion of a region where the gate wiring and the source wiring are juxtaposed so that they are parallel to each other, a non-doped amorphous silicon layer described later, and an etching stopper insulating layer. Film, phosphorus doped amorphous silicon layer, extension of source wiring, drain electrode line And it consists of such as a contact hole. The transparent insulating substrate can be made of borosilicate glass, quartz glass, or the like. In this embodiment, borosilicate glass is used.

As shown in FIG. 1, the first conductive thin film 4 includes a resistor made of a transparent conductive material and a nonlinear element 5.
Is provided on the short ring terminal 3a (not shown in FIG. 1) to electrically connect each of the source wiring and the gate wiring to the short ring. That is, the first conductive thin film 4 is formed at the end of the gate wiring 2 so as to be connected to the short ring terminal 3a, and is connected to the short ring terminal 3a (see FIG. 2) at the end of the source wiring 1. The non-linear element 5 is formed. In this way, the source wiring and the gate wiring are electrically connected to the short ring provided on the outer peripheral portion of the display unit in which the source wiring and the gate wiring are juxtaposed so as to be parallel to each other.

Such an array substrate is manufactured by the following array forming process (see FIG. 2). First, a film made of chromium or the like is formed on a transparent insulating substrate (not shown), and is patterned to form a metal thin film serving as the gate wiring 2, the short ring 3, and the short ring terminal 3a. Next, after forming a film made of a transparent conductive material such as ITO, the pixel electrode is patterned by photolithography using a photomask.

A resistor made of a transparent conductive material is formed as a first conductive thin film 4 at an end of the gate wiring 2 (not shown in FIG. 2). The resistor made of this transparent conductive material needs to have a resistance value of about ten to several tens KΩ. This can be dealt with by a method of forming a transparent conductive film in a meandering shape using the same transparent conductive material as ITO or tin oxide or the like, and therefore, it may be formed simultaneously with the above-described patterning of the pixel electrode. Therefore, an increase in the number of steps can be suppressed.

After forming the first conductive thin film 4 and the pixel electrode 11 made of the transparent conductive material, as shown in FIG. 2, a film made of silicon nitride, a non-doped amorphous silicon (i- a-Si) layer 7,
After the etching stopper insulating film 10 made of silicon nitride, silicon oxide, or the like is sequentially formed by a CVD method or a sputtering method, the etching stopper insulating film 10 is patterned.

Next, after the phosphorus-doped amorphous silicon layer 8 is formed, the pixel electrode 11 is formed by patterning.
And a contact hole 13 between the drain electrode line 9 is formed.

Further, chromium, tantalum and the like for forming the source wiring 1 and the extension 1a of the source wiring and the drain electrode line 9 are formed by sputtering or electrodeposition, and then patterned. Further, unnecessary portions of the non-doped amorphous silicon layer 7 and the phosphorus-doped amorphous silicon layer 8 are removed using the extension 1a of the source wiring and the drain electrode line 9 as a mask.
The non-doped amorphous silicon layer and the phosphorus-doped amorphous silicon layer thus formed constitute a nonlinear element. Finally, a protective film made of silicon oxide or silicon nitride is formed, and a matrix array substrate is completed.

In the above-described steps, a resistor composed of the nonlinear element 5 formed simultaneously with the switching element, which is a thin film transistor, provided in the display section is also provided in the extension of the source line. With the resistor composed of the nonlinear element 5, the source line and the short ring are conducted.

The above-described array forming step is an array forming step when a thin film transistor including an etching stopper insulating film is used as a switching element. If a thin film transistor not including an etching stopper insulating film is used as a switching element, It is not necessary to form and pattern the etching stopper insulating film.

In the array substrate thus formed, the gate wiring is connected to the short ring by the first conductive thin film 4 which is a resistor made of a transparent conductive material. Since the connection by the first conductive thin film 4 is performed immediately after the formation of the gate wiring, it is possible to suppress the occurrence of the dielectric breakdown short-circuit due to the static electricity generated during the subsequent array formation step for the gate wiring.

On the other hand, since the source wiring is formed at the last stage of the array forming step, little consideration should be given to static electricity during the array forming step. Therefore, the source wiring is connected to the short ring using the nonlinear element 5. This makes it possible to avoid the adverse effects of static electricity generated during the array formation process as much as possible and to provide an acceptable sensitivity to inspections such as a charge sensing method.

Second Embodiment Next, a second embodiment according to the present invention will be described. FIG. 3 is an explanatory plan view of the configuration of the matrix type array substrate according to the second embodiment. FIG. 4 shows a pixel electrode (not shown in FIG. 3) related to a certain pixel, and a first electrode connected in parallel at an extension of the source wiring shown in FIG.
Of the conductive thin film and the nonlinear element shown in FIG. 3, the nonlinear element portion and a portion of the pixel electrode (FIG. 4A) and the portion including the first conductive thin film and a portion of the pixel electrode (FIG. It is an enlarged sectional explanatory view of b)). FIG. 4A is a cross-sectional explanatory view showing a cross section taken along line FF of a region E shown in FIG. FIG. 4B is an explanatory cross-sectional view showing a cross section taken along line HH of the region E and the region G shown in FIG. FIG. 4 (b)
Shows a cross section taken along the line HH of the region E on the right side of the broken portion, and a cross section taken along the line HH of the region G on the left side of the broken portion. 3 and 4, the same reference numerals are used for the same parts as those shown in FIGS. 1 and 2, and 15 is a first conductive thin film.

A configuration according to the second embodiment will be described. As shown in FIG. 3, also in the present embodiment, as in the first embodiment, a gate wiring 2 and a short ring 3 are formed on a transparent insulating substrate. After that, a resistor made of a transparent conductive material is formed on the short ring terminal 3a as a first conductive thin film 4 connecting between the gate wiring 2 and the short ring 3. Here, in the second embodiment, the first conductive thin film 4 is formed between the gate wiring and the short ring, and the first conductive thin film 4 is formed between the source wiring and the short ring in parallel with the nonlinear element 5. One conductive thin film 15 is further formed. Further, with respect to the connection between the source wiring and the short ring, after the non-linear element has a function as a resistor, it is exposed because the contact hole 13 is formed in the first conductive thin film 15. The first conductive thin film 15 is partially or entirely etched off by etching off including the region where the first conductive thin film 15 is formed.

Such a TFT array substrate is manufactured by the following steps. First, a film is formed on a transparent insulating substrate using chromium or tantalum or the like, and is patterned to form a metal thin film serving as the gate wiring 2, the short ring 3, and the short ring terminal 3a.
Further, after a film is formed of a transparent conductive material such as ITO, the first conductive thin film 4 made of a transparent conductive material and the first conductive film 4 made of the transparent conductive material are formed by photolithography using a photomask. The conductive thin film 15 is formed.
Next, as shown in FIG. 4A, a film made of silicon nitride or tantalum oxide, a non-doped amorphous silicon (ia-Si) layer 7, an etching stopper made of silicon nitride or silicon oxide, etc., as the gate insulating film 6 After the insulating film 10 is sequentially formed by a CVD method or a sputtering method, the etching stopper insulating film 10 is patterned.

Next, a phosphorus-doped amorphous silicon layer 8 is formed. As a result, the source side and the drain side of the array substrate are electrically connected via the phosphorus-doped amorphous silicon layer 8. Further, a contact hole 13 (see FIG. 4A) for establishing conduction with the source wiring is formed. At this time, FIG. 3 and FIG.
A contact hole 13 shown in FIG. The contact hole 13 is formed by etching at least a part of the gate insulating film 6 on the first conductive thin film 15.

Further, chromium and tantalum for forming the source wiring and the extension 1a of the source wiring and the wiring as the drain electrode, that is, the drain wiring 9, are formed by sputtering or electrodeposition, and are patterned. Further, the unnecessary non-doped amorphous silicon layer 7 and unnecessary phosphorus-doped amorphous silicon layer 8 are removed by using the extension 1a of the source wiring and the drain wiring 9 as a mask.

After that, a transparent conductive film is formed, and the pixel electrode 11 is formed by etching after photolithography. At this time, part or all of the first conductive thin film 15 is etched due to the presence of the previously formed contact hole 13 (see FIG. 4B). Thus, the first conductive thin film 15 becomes useless for connection between the source wiring and the short ring. However, at this stage, since the connection between the source wiring and the short ring is made by the non-linear element 5, there is no problem with respect to measures against generation of static electricity. Finally, a protective film made of silicon nitride or silicon oxide is formed, and a matrix array substrate is completed.

In the matrix type array substrate thus formed, the first conductive thin film 15 made of a transparent conductive material until the middle of the array forming step, and then the non-linear element 5 such as a transistor. Make a connection between the gate wiring and the short ring. By taking the two-stage connection in this way, measures against static electricity in the middle of the array formation process are taken, and in the inspection stage, a connection is made with a higher resistance non-linear element, so that the inspection sensitivity is higher. Can be provided.

In the present embodiment, the first conductive thin film 1 is made of the same material as the transparent conductive material forming the pixel electrode.
Although the first conductive thin film 15 is formed, the first conductive thin film 15 can be formed of the same material as that of the source wiring or the drain wiring.

In this case, the first conductive thin film 15 is removed by etching when forming the source wiring or the drain wiring. However, even in this case, at the stage where the first conductive thin film 15 is removed, since the resistor including the nonlinear element 5 is completed, there is no problem in terms of measures against generation of static electricity.

Embodiment 3 In Embodiment 1, the connection between the gate wiring and the short ring is made by a resistor of about 10 KΩ made of a transparent conductive material. Even in the configuration of the first embodiment, the sensitivity of the inspection is practically no problem, but in order to further increase the sensitivity, it is necessary to reduce the wraparound of the gate signal from the gate wiring to the source wiring.

As means for reducing such a wraparound of the gate signal, the source-side short ring and the gate-side short ring are once separated, and the separated portion is used as a second conductive thin film as a second conductive thin film. A method of forming a resistor of several tens KΩ using the same type of transparent conductive material as the transparent conductive material to which the short ring is connected, and connecting using the resistor of several tens KΩ is conceivable. An example is shown in FIG. FIG. 5 is an explanatory plan view showing a configuration of a matrix array substrate according to Embodiment 3 of the present invention. In FIG. 5, the other configuration on the array substrate is the same as that of the first embodiment. Reference numeral 20 denotes a second conductive thin film, which is a resistor made of the transparent conductive material. By the connection using the second conductive thin film 20, it is possible to improve the sensitivity of the inspection while taking measures against the generation of static electricity.

Fourth Embodiment In the third embodiment, the source-side short ring and the gate-side short ring are connected by the second conductive thin film, that is, a resistor formed using a transparent conductive material. It is also possible to connect using the same nonlinear element as the above-mentioned nonlinear element such as a TFT as shown in FIG. FIG.
FIG. 9 is an explanatory plan view showing a configuration of a matrix array substrate according to Embodiment 4 of the present invention. In FIG.
Other configurations on the array substrate are the same as those in the first embodiment, and reference numeral 5 denotes a non-linear element. Connect this TF to the tangent line between the source-side short ring and the gate-side short ring.
By using the non-linear element 5 such as T, the source-side short ring and the gate-side short ring are connected with higher resistance, so that it is possible to suppress the gate signal from flowing into the source wiring. This allows
It is possible to further increase the sensitivity of the test.

Embodiment 5 Further, as in Embodiment 2, the source wiring and the short ring are connected by using both the first conductive thin film and the nonlinear element, and the nonlinear element has a function as a resistor. At the time when the first conductive thin film is removed at the
As shown in the figure, the short ring on the source side and the short ring on the gate side are connected by the nonlinear element 5. Other configurations on the array substrate are the same as those in the first embodiment. By connecting the non-linear elements in this manner, it is possible to substantially prevent the gate signal from flowing into the source wiring, and it is possible to extremely increase the inspection sensitivity.

[0052]

As described above, according to the present invention, the gate wiring and the short ring are connected immediately after the gate wiring is formed using the transparent conductive material, and the connection between the source wiring and the short ring is formed. By using a non-linear element for connection, it was possible to suppress the occurrence of defects caused by static electricity generated during the array formation process. In addition, there is an effect that sufficient sensitivity is given to an inspection such as a charge sensing method. Further, by connecting the source-side short ring and the gate-side short ring with a high-resistance body, it is possible to further increase the sensitivity of the inspection.

[Brief description of the drawings]

FIG. 1 is an explanatory plan view showing a configuration of a matrix type array substrate according to an embodiment of the present invention.

FIG. 2 is an explanatory cross-sectional view of a nonlinear element in an extension of a source wiring shown in FIG. 1;

FIG. 3 is an explanatory plan view showing a configuration of a matrix type array substrate according to another embodiment of the present invention.

4 is an enlarged cross-sectional explanatory view of a portion including a non-linear element connected to an extension of the source wiring shown in FIG. 3 and a portion including a first conductive thin film.

FIG. 5 is an explanatory plan view showing a configuration of a matrix type array substrate according to another embodiment of the present invention.

FIG. 6 is an explanatory plan view showing a configuration of a matrix type array substrate according to another embodiment of the present invention.

FIG. 7 is an explanatory plan view showing a configuration of a matrix type array substrate according to another embodiment of the present invention.

FIG. 8 is an explanatory plan view showing a configuration of a conventional matrix type array substrate.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Source wiring 1a Extension part of source wiring 2 Gate wiring 3 Short ring 3a Short ring terminal 4 First conductive thin film 5 Nonlinear element 6 Gate insulating film 7 Non-doped amorphous silicon layer 8 Phosphorus doped amorphous silicon layer 9 Drain electrode line 10 Etching Stopper insulating film 13 Contact hole 15 First conductive thin film 20 Second conductive thin film

Claims (9)

[Claims] 1. A transparent insulating substrate, a plurality of gate wirings juxtaposed on the insulating substrate, a gate insulating film covering the gate wirings, and a plurality of the gate wirings via the gate insulating film. A plurality of source wirings arranged side by side so as to intersect with each other, a thin film transistor provided at an intersection of the source wiring and the gate wiring, and a pixel electrode made of a transparent conductive material connected to the thin film transistor, A short ring wiring provided to make the source wiring and the gate wiring have the same potential outside a region where the source wiring and the gate wiring are juxtaposed, and an upper part of a region where the short ring wiring is formed. A non-doped amorphous silicon layer to cover, an etching stopper insulating film, a phosphorus-doped amorphous silicon layer, and the phosphorus-doped amorphous silicon layer. A matrix type array substrate for a liquid crystal display device comprising an extension of the source line and a drain electrode line provided on a silicon layer, wherein the gate line and the short ring line are connected to each other by a first line.
Wherein the source wiring and the short ring wiring are connected via a non-linear element having a non-linear resistance characteristic. . 2. The matrix type array substrate according to claim 1, wherein said first conductive thin film is made of said transparent conductive material. 3. The non-linear element is further provided with a first conductive thin film identical to the first conductive thin film, and the first wiring is connected to the source wiring and the short ring wiring. A matrix array substrate for a liquid crystal display device, wherein at least a part of the conductive thin film is removed in a step of manufacturing the matrix array substrate. 4. A connection between the short ring wiring connected to the gate wiring and the short ring wiring connected to the source wiring by a second conductive thin film. 4. A matrix type array substrate of the liquid crystal display device according to 1, 2, or 3. 5. The matrix type array substrate according to claim 4, wherein said second conductive thin film is made of said transparent conductive material. 6. The non-linear element which is connected between the short ring wiring on the side connected to the gate wiring and the short ring wiring on the side connected to the source wiring. Item 7. A matrix type array substrate for a liquid crystal display device according to item 1, 2 or 3. 7. A transparent insulating substrate, a plurality of gate wirings juxtaposed on the insulating substrate, a gate insulating film covering the gate wiring, and a plurality of the gate wirings via the gate insulating film. A plurality of source wirings arranged side by side so as to intersect with each other, a thin film transistor provided at an intersection of the source wiring and the gate wiring, and a pixel electrode made of a transparent conductive material connected to the thin film transistor, A short ring wiring provided to make the source wiring and the gate wiring have the same potential outside a region where the source wiring and the gate wiring are juxtaposed, and an upper part of a region where the short ring wiring is formed. A non-doped amorphous silicon layer and a phosphorus-doped amorphous silicon layer to cover, and A matrix-type array substrate for a liquid crystal display device, comprising: an extended portion of the source line and a drain electrode line, wherein the gate line and the short ring line are connected via a first conductive thin film; A matrix type array substrate for a liquid crystal display device, wherein the source wiring and the short ring wiring are connected via a non-linear element having a non-linear resistance characteristic. 8. A transparent insulating substrate, a plurality of gate wirings juxtaposed on the insulating substrate, a gate insulating film covering the gate wiring, and a plurality of the gate wirings via the gate insulating film. A plurality of source wirings arranged side by side so as to intersect with each other, a thin film transistor provided at each intersection of the source wiring and the gate wiring, a pixel electrode made of a transparent conductive material attached to the thin film transistor, A short ring wiring provided at an outer portion of a region where the source wiring and the gate wiring are respectively arranged in parallel to make the source wiring and the gate wiring have the same potential, and the short ring wiring and the source wiring are connected. A first conductive thin film to be formed, and the short ring wiring and the source arranged in parallel with the first conductive thin film. A non-linear element having a non-linear resistance characteristic formed to connect wiring, a non-doped amorphous silicon layer covering an area where the first conductive thin film and the non-linear element are formed, an etching stopper insulating film, and a phosphorus A doped amorphous silicon layer, an extension of the source wiring and a drain electrode line provided on the phosphorus-doped amorphous silicon layer,
A method for producing a matrix-type array substrate for a liquid crystal display device, comprising: the phosphorus-doped amorphous silicon layer, the non-doped amorphous silicon layer, and a contact hole formed in the gate insulating film, wherein (a) the transparent insulating substrate (B) forming the first conductive thin film and the nonlinear element and connecting an end of the gate wiring to the short ring wiring; c) a step of sequentially forming the gate insulating film, the non-doped amorphous silicon layer, and the etching stopper insulating film; (d) forming the phosphorus-doped amorphous silicon layer, and then forming the phosphorus-doped amorphous silicon layer;
Selectively etching the non-doped amorphous silicon layer and the gate insulating film to form the contact hole; (e) forming the source line, an extension of the source line, and the drain electrode line; A) a step of etching away a part of the non-doped amorphous silicon layer and a part of the phosphorus-doped amorphous silicon layer by using the extension of the source wiring and the drain electrode line as a mask; and (g) forming the pixel electrode Forming the contact hole by etching at least one part of the first conductive thin film in any one of the steps (d) to (g). Of manufacturing a matrix type array substrate for a liquid crystal display device. 9. A transparent insulating substrate, a plurality of gate wirings juxtaposed on the insulating substrate, a gate insulating film covering the gate wiring, and a plurality of the gate wirings via the gate insulating film. A plurality of source wirings arranged side by side so as to intersect with each other, a thin film transistor provided at each intersection of the source wiring and the gate wiring, a pixel electrode made of a transparent conductive material attached to the thin film transistor, A short ring wiring provided at an outer portion of a region where the source wiring and the gate wiring are respectively arranged in parallel to make the source wiring and the gate wiring have the same potential, and the short ring wiring and the source wiring are connected. A first conductive thin film to be formed, and the short ring wiring and the source arranged in parallel with the first conductive thin film. A non-linear element formed so as to connect wirings and having a non-linear resistance characteristic; a non-doped amorphous silicon layer and a phosphorus-doped amorphous silicon layer covering a region where the first conductive thin film and the non-linear element are formed; An extension of the source wiring and a drain electrode line provided on the phosphorus-doped amorphous silicon layer, and contact holes formed in the phosphorus-doped amorphous silicon layer, the non-doped amorphous silicon layer, and the gate insulating film. A method of manufacturing a matrix type array substrate of a liquid crystal display device, wherein (a) forming the gate wiring and the short ring wiring on the transparent insulating substrate;
(B) forming the first conductive thin film and the non-linear element and connecting an end of the gate wiring to the short ring wiring; (c) sequentially forming the gate insulating film and the non-doped amorphous silicon layer Process,
(D) forming the contact hole by selectively etching the phosphorus-doped amorphous silicon layer, the non-doped amorphous silicon layer, and the gate insulating film after forming the phosphorus-doped amorphous silicon layer; Forming a source wiring, an extension of the source wiring, and the drain electrode line; (f) using the extension of the source wiring and the drain electrode line as a mask, a part of the non-doped amorphous silicon layer; (G) removing a portion of the silicon layer by etching;
Forming the pixel electrode;
(G) in any one of the steps, the contact hole is formed by etching at least a part of the first conductive thin film to form the contact hole. Manufacturing method.