JPH1038662A - Level detector - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electrostatic level detector which requires no zero adjustment. SOLUTION: In a level detector, a capacitance-frequency (C/F) converter 11 outputs a frequency signal that is reversely proportional to the capacitance between a housing container 6 and a main electrode 2 and a first counter 12 counts the cycle number of the output signal of the converter 11 during first counting time T1 and holds the count value C1. Then a second counter 13 successively counts the cycle number of the output signal of the converter 11 during every second counting time T2 set to be longer than the first count time T1 by ΔT and a comparator 16 compares the second count value C2 with the first count value C1 and, when the count values become C1>=C2, outputs a level detecting signal (a).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitance type level detecting device for detecting that a stored material such as powder or liquid stored in a storage container has reached a predetermined level.

[0002]

2. Description of the Related Art Conventionally, this type of capacitance type level detecting device requires an operation of zero point adjustment and sensitivity adjustment when the container is first installed in a storage container with the container being empty. , Installation work is troublesome. Therefore, the detected capacitance is converted to digital and stored by a microprocessor.
It is conceivable to output a detection signal when the capacitance reaches a certain value due to an increase in the amount of stored items. However, this requires a CPU and increases costs.

[0003]

SUMMARY OF THE INVENTION According to the present invention, there is provided an inexpensive electrostatic capacitance type level detector which eliminates the need for on-site adjustment work in which the level detector is installed in a storage container, and has a simple circuit configuration. The purpose is to:

[0004]

A level detecting device according to the present invention comprises a main electrode and a ground electrode which are mounted so as to protrude into a storage container, and a frequency output corresponding to a change in capacitance between the two electrodes. A capacity-frequency converter for generating a signal; first and second counters for counting the number of cycles of an output signal of the converter; and a first counting time when the storage container is empty. Control means for operating the first counter value only to hold the first count value, and operating the second counter at predetermined time intervals and for a second count time set longer than the first count time, and A comparator that outputs the detection signal when the count value of the two counters is equal to or smaller than the first count value.

According to the present invention, when the level detector is installed in an empty container and the operation is started, the first counter indicates the number of cycles of the output signal of the capacitance-frequency converter when the container is empty. Is counted for the first count time,
The first count value corresponding to the capacitance when the container is empty is held in, for example, an attached memory or its own latch circuit. On the other hand, the second counter sequentially counts the number of cycles of the output signal of the capacitance-frequency converter by a second count time set at a predetermined time interval longer than the first count time. Therefore, the first count value when the storage container is empty is smaller than the second count value. The capacity between the main electrode and the storage container increases as the amount of storage in the storage container increases, and the frequency of the output signal of the capacitance-frequency converter decreases accordingly. The second count value output from the counter also decreases. The comparator 16 outputs a detection signal when the amount of the stored item reaches a predetermined level and the first count value is equal to or smaller than the second count value.

Further, the first and second counters are constituted by a single counter, and the control means first counts the first count time and holds the first count value. It is also possible to adopt a configuration in which control is performed so as to obtain a second count value by sequentially counting with time. According to this, the number of counters can be reduced.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a partially cutaway side view showing a state in which a level detecting device according to an embodiment of the present invention is mounted on a storage container. The level detecting device 1 has a round bar-shaped main electrode 2 and a main electrode 2 having a round rod shape. It has a cylindrical ground electrode 4 that covers the outer circumference via an insulator 3 and a main body 10 that supports these electrodes 2, 4, and a flange 21 of the main body 10 is located above the side wall surface of the storage container 6. , The two electrodes 2, 4 protrude into the storage container 6. The ground electrode 4
Are kept in contact with the storage container 6 via the main body 10 at the ground potential.

The detection circuit 5 is built in the housing 22 of the main body 10. As shown in FIG. 2, the detection circuit 5 includes a main electrode 2 and a ground electrode 4 (that is, a storage container 6).
And a capacitance-frequency converter (hereinafter referred to as “C / F conversion”) unit 11 for converting the capacitance C between the first and second signals into a signal having a frequency inversely proportional to the capacitance C. It has two counters 12 and 13, a memory 14, and control means 15 for controlling the counters 11 and 12 and the memory 14.

The control means 15 causes the first counter 12 to count the number of cycles of the input signal for a first count time T1 (for example, 0.2 seconds) from the start of the operation of the level detection device 1, The count value C1 is set to the first
The second counter 13 is stored in the memory 14 and the second counter 13 is set to a time ΔT (for example, ΔT =
The count is sequentially performed at predetermined time intervals by a second count time T2 that is set to be longer by 0.005T1).

The detection circuit 5 further compares the first count value C1 stored in the memory 14 with the second count value C2 which is sequentially counted by the second counter 13, and C1 ≧ C2. Comparator 1 that outputs a detection signal
6. The detection signal a from the comparator 16 is
Input to the relay circuit 17.

Except for the counters 12 and 13 and the relay circuit 17, the C / F converter 11, the memory 14,
The control means 15 and the comparator 16 are generally constituted by CMOS ICs called timer ICs. That is, CP
U is not used. This IC is backed up by a large capacity capacitor (not shown) or a storage battery such as a lithium battery, and stores a count value up to that time for a certain time even when a power failure occurs.

Reference numeral 7 denotes a supply means comprising a belt conveyor for supplying a storage material such as powder into the storage container 6. Reference numeral 8 denotes a drive controller of the supply controller. The drive controller 8 is operated by turning on the relay circuit 17. Then, the supply means 7 is stopped.

FIG. 3 is a timing chart for explaining the control operation of the detection circuit 5. Now, when the operation of the level detection device 1 starts at time t0, the C / F converter 11 outputs a signal of the frequency f0 corresponding to the capacity C0 when the storage container 6 is empty, to the first and second counters 12, 13. Output to The control means 15 causes the first counter 12 to start counting at time t1, stop counting after the first count time T1, and causes the memory 16 to store the first count value C1.

The control means 15 causes the second counter 13 to start counting at the time t1, and the second counting time T
Stop counting after 2 = (T1 + ΔT). The second
The count value C2 is larger than C1 because T2> T1. Thereafter, control is performed so as to repeat the operation of counting by the second count time T2 from time t2 at a fixed time interval. Since the capacity between the main electrode 2 and the storage container 6 increases as the amount of the storage items in the storage container 6 increases, the frequency of the output signal of the C / F converter 11 decreases accordingly. The second count value C2 output from the second counter 13 also decreases.

The comparator 16 sends a detection signal a to the relay circuit 17 when the n-th second count value C2 counted from the time tn satisfies C1 ≧ C2, and the relay circuit 17 activates the drive controller 8. To stop the supply means 7.

As described above, when the level detecting device 1 is operated when the storage container is empty, the first count value C is automatically set.
Since 1 is updated, zero adjustment is automatically performed.

The timing when C1 ≧ C2 is
It is determined by the time difference ΔT between the first count time T1 and the second count time T2. The time difference ΔT determines the second count time T2 such that the second count value C2 when the stored items in the storage container 6 reach the level to be detected at the first operation becomes C1 = C2. Can be set.

Further, when the second count time T2 is set, the time difference ΔT
By changing the minute, the detection level can be almost changed proportionally. Therefore, when the level detection device 1 is shipped,
Set the detection level by the manufacturer (second count time T
2) can be performed, and it is not necessary to perform this at the site where the level detection device 1 is incorporated in the storage container 6.

In the above embodiment, two counters are provided. However, as in the second embodiment shown in FIG. 4, the first and second counters are constituted by one counter 32, The first time, the frequency of the output signal of the C / F converter 11 is counted by the first count time T1, the first count value C1 is stored in the memory 14, and the second and subsequent times are switched to the second count time T2. Thus, the comparator 16 may compare the first count value C1 with the second count value C2.

According to this configuration, since only one counter is required, the apparatus can be simplified.

In each of the above embodiments, the first and second count values C1 and C2 are set to one count value. However, if the average value of the count values is set to a plurality of times, the detection accuracy can be improved. . Further, the memory 14 is omitted, and the first counter 12 (FIG. 2) or the counter 32 (FIG. 4)
A latch function for holding the count value C1 may be provided.

[0022]

As described above, according to the present invention, C /
Since the change in the frequency of the output signal of the F converter is measured using the count value obtained by counting the number of cycles within a predetermined count time by the counter, the zero point can be automatically adjusted. In addition, the present invention can be applied to various storage items having a capacitance in a wide range of 32 to 1000 pF, and furthermore, a change in the capacitance can be determined by a count value, so that the detection accuracy is high. Moreover, since the detection circuit can be constituted by the IC and the counter without using the CPU, the circuit configuration is simple,
Become cheap.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view showing a state where a level detecting device according to an embodiment of the present invention is mounted on a storage container.

FIG. 2 is a block diagram illustrating a configuration of a detection circuit according to the first embodiment.

FIG. 3 is a timing chart for explaining the operation of the detection circuit of the embodiment.

FIG. 4 is a block diagram illustrating a configuration of a detection circuit according to a second embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Level detection device, 2 ... Main electrode, 3 ... Insulator, 4 ... Ground electrode, 5 ... Detection circuit, 6 ... Storage container, 11 ... Capacitance-frequency converter, 12 ... First counter, 13 ... Second counter , 14 ... memory, 15 ... control means, 16 ... comparator, 1
7: relay, a: detection signal, C1: first count value, C
2: second count value, T1: first count time, T2 ...
Second count time.

Claims (2)

[Claims] 1. A level detecting device for detecting when a level of a storage item in a storage container reaches a predetermined level and outputting a detection signal, the detection device being mounted so as to protrude into the storage container. A main electrode and a ground electrode; a capacitance-frequency converter for generating an output signal having a frequency corresponding to a capacitance change between the two electrodes; and a first counting the number of cycles of the output signal of the converter.
And a second counter, when the storage container is empty, operating the first counter for a first count time to hold the first count value, and setting the second counter at a predetermined time interval,
And control means for operating a second count time set for a time longer than the first count time, and when the count value of the second counter is equal to or smaller than the first count value, A level detection device comprising: a comparator that outputs a detection signal. 2. The device according to claim 1, wherein the first and second counters are formed of a single counter, and the control means first counts in the first count time and holds the first count value. Then, a level detection device that controls so as to sequentially count in the second count time to obtain a second count value.