JPH1038548A - Displacement measuring instrument - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a displacement measuring instrument to internally count original counting-pulses at a high speed by using a buffer counter which operates at a first high-speed clock by outputting the counting-pulses by the number corresponding to the count value of the buffer counter while counting the counting-pulses and, at the same time, to count the pulses with a low-frequency low-speed external counter. SOLUTION: Original counting-pulses PUEN and up/down pulses U/D obtained from an original counting-pulse generating circuit 2 are sent to a buffer counter 3 and the counter 3 counts the width of the pulses PUEN in accordance with a first clock CK0. A counting-pulse outputting circuit 8 outputs the counting pulses by the number equal to the count value of the counter 3. The output value of the counter 3 is outputted in real time. In order to decide the outputting frequency of the counting-pulses, an outputting period counter 5 is provided. The counter 5 outputs a second clock CK1 by dividing the first clock K0 at a prescribed frequency dividing ratio. The frequency of the second clock CK1 can be set variably within the same range as that of the first clock CK0 or lower.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a displacement measuring device of a type in which a counting pulse corresponding to a displacement amount is counted by an external counter.

[0002]

2. Description of the Related Art In displacement measuring devices such as linear gauges and linear scales, the amount of movement of a head or spindle is output as a counting pulse, and this is often counted and displayed by an external counter. In this method, f is between the output frequency f OUT of the count pulse and the count frequency f CNT of the external counter.
Unless the relationship of OUT ≦ fCNT is established, normal operation cannot be guaranteed. Accordingly, if the speed of the displacement measuring device is increased and the counting pulse is increased, there is a problem that the conventional external counter having a low fCNT cannot be used.

In the case where the output counting pulse frequency changes in accordance with the moving speed of the displacement detector, when a low-speed external counter is used, the moving speed of the displacement detector is limited by the external counter, and the high-speed counting is performed. Can not. Further, in the case of using a servo circuit such as a capacitance type displacement detector,
Some output a high-speed burst-like counting pulse regardless of the moving speed of the detector. If a low-speed external counter is connected to such a measuring device, errors such as erroneous counting and overspeed may occur even when the moving speed of the detector is low.

[0004]

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above circumstances, and uses a counting pulse capable of performing high-speed counting internally and also capable of performing counting by a low-speed external counter. It is intended to provide a displacement measuring device for outputting.

[0005]

SUMMARY OF THE INVENTION The present invention relates to a displacement measuring device for outputting a number of count pulses corresponding to a displacement amount to be counted by an external counter based on an output of a displacement detector. Source count pulse generating circuit that operates in synchronization with the above and outputs a source count pulse having a width corresponding to the amount of displacement detected by the displacement detector and an up / down pulse instructing up / down in accordance with the direction of displacement. A buffer counter that counts up / down the source count pulse with the first clock; and a count value of the buffer counter that operates with a second clock having a frequency equal to or lower than the first clock. And a pulse output circuit for generating the same number of counting pulses.

According to the present invention, in addition to the above configuration, an output cycle counter for generating the second clock for determining the frequency of the count pulse to be output by dividing the first clock, and the buffer counter When the count value is not zero, the pulse output is obtained by a combination of a clock gate which takes out the second clock as an output enable signal and supplies it to the pulse output circuit, and a combination of the source count pulse, up / down pulse and output enable signal. A counter control gate for performing control to increase or decrease the count value of the buffer counter in real time according to the count pulse output from the circuit. Preferably, in the present invention, the output cycle counter is configured such that the frequency of the second clock can be set to be equal to or lower than the frequency of the first clock by switching a frequency division ratio under control from an external terminal. Is done. More preferably, the overflow terminal of the buffer counter is led out as an overspeed terminal.

According to the present invention, in the buffer counter operated by the high-speed clock, the source counter pulse is counted and, at the same time, the count pulse corresponding to the count value is output by the low-speed clock. Therefore, counting by a low-speed external counter is possible. If the number of digits of the buffer counter can cover the moving range of the displacement detector, no matter how low the frequency of the output counting pulse, the moving speed of the displacement detector is not limited. Also, by controlling the count value of the buffer counter to increase or decrease in real time simultaneously with the output of the count pulse, the number of digits of the buffer counter can be made smaller than the moving range of the displacement detector, thereby reducing the circuit scale. The moving speed of the displacement detector can be secured without being limited by the counting frequency of the external counter. Also,
If the output cycle counter for generating the second clock for determining the frequency of the output count pulse is externally made variable in frequency division ratio, the count pulse frequency can be switched according to the external counter. For example, when the external counter can perform high-speed counting, the division ratio 1, that is, the second clock frequency can be made the same as the first clock frequency, and therefore, the system adaptability can be high.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of a displacement measuring device according to an embodiment of the present invention. The displacement detector 1 may be of a capacitance type, a photoelectric type, or any other type. The source count pulse generation circuit 2 operates in synchronization with the first clock CK0, and performs up / down in accordance with the source count pulse PUEN having a width corresponding to the displacement detected by the displacement detector 1 and the displacement direction. Instructed up / down pulse U / D
Is output. The source counting pulse PEUN is output from the displacement detector 2
May be a burst-like pulse including the clock CK0 inside, or a pulse obtained by envelope-detecting the same. Conventionally, the source count pulse PUEN is an up / down pulse It is transferred directly to the counting pulse output circuit that operates with the same clock together with the U / D to generate a counting pulse output in a predetermined format (for example, a counting pulse and a U / D signal or a two-phase square wave signal). Was.

In this embodiment, a source count pulse PUEN and an up / down pulse U / D obtained from a source count pulse generating circuit 2 are sent to a buffer counter 3, and
Here, the width of the source count pulse PEUN is equal to the first clock CK.
Counted by zero. The count value of the buffer counter 3 corresponds to the displacement amount to be obtained. It is the count pulse output circuit 8 that outputs count pulses equal in number to the count value of the buffer counter 3. In this embodiment, as described later, the count value of the buffer counter 3 is increased or decreased in real time. The count pulse output circuit 8 outputs a count output pulse. An overflow terminal OF of the buffer counter 3 is led out as an overspeed terminal OS.

An output cycle counter 5 is provided to determine the frequency of the count pulse output by the count pulse output circuit 8. The output cycle counter 5 generates a second clock CK1 obtained by dividing the first clock CK0 by a predetermined dividing ratio.
In this embodiment, an external terminal for switching the frequency division ratio is provided, and as shown in FIG. 3, the frequency of the second clock CK1 is changed to the first clock C
It can be variably set in a range equal to or lower than K0. Then, the second clock CK1 obtained from the output cycle counter 5 is used as a synchronous clock of the count pulse output circuit 8.

In the buffer counter 3, simultaneously with the counting of the source count pulse PUEN, the control of increasing or decreasing the count value in accordance with the output from the count pulse output circuit 8 is performed in real time. And a clock gate 6 which is controlled by the output AZ of the detection circuit 4 and takes out the second clock CK1 from the output cycle counter 5 as an output enable signal OUTEN. A counter control gate 7 for controlling the counting operation is provided. The counter control gate 7 includes a source count pulse PUEN, an up / down pulse U / D, an output enable signal OUTEN, and a buffer counter 3.
A control signal is sent to the buffer counter 3 by the combinational logic of the sign bit output MINUS, and the buffer counter 3 performs control of ± 1 count, ± 2 count or count stop.

Before explaining a detailed circuit of each part, the count operation of the buffer counter 3 is summarized in a truth table.
Table 1 below. The sign MINUS of the buffer counter 3 indicates which of the up / down directions of the source count pulse has been output, thereby determining the count pulse output direction.

[0013]

[Table 1]

In Table 1, x means that "0" or "1" is not considered. The operation based on the logic of Table 1 will be described. If the source count pulse PUEN = 0 and the output enable signal OUTEN = 0, the buffer counter 3 does not need to be moved, so that the operation is STOP. Source counting pulse PU
EN down count instruction (PUEN = 1, U / D =
0) and an up-count instruction by a count pulse output when the count value is negative (OUTEN = 1, MINUS = 0)
If they overlap, it means that the number of pulses input to the buffer counter and the number of pulses output are the same,
The buffer counter 3 is STOP. Similarly, an up-count instruction of the source count pulse PUEN (PUEN = 1, PUEN = 1)
U / D = 1) and a down-counting instruction (OUTEN = 1, MIN) by outputting a count pulse when the count value is positive.
STOP is also set when US = 1) overlaps.

Further, there is no input of the source count pulse (PUE
N = 0), when there is a count pulse output (OUTEN =
In 1), since the value to be buffered increases or decreases due to the output of the counting pulse, −1 and +1 are counted according to the positive or negative count value. Conversely, PUEN = 1, O
In the case of UTEN = 0, +1, -1 is counted in accordance with the up / down instruction. Further, an up-count instruction by a source count pulse (PUEN = 1, U / D = 1)
If the count value overlaps with the up-count instruction (OUTEN = 1, MINUS = 0) based on the count pulse output when the count value is negative, the direction of the count pulse output and the source count pulse are reversed, and the buffer counter increases / decreases. Since the value needs to be doubled, +2 is counted. Conversely, a down count instruction by a source count pulse (PUEN = 1, U / D = 0)
When a countdown instruction (OUTEN = 1, MINUS = 1) by counting pulse output in a state where the count value is positive overlaps, -2 is counted.

By the above-described count control by the buffer counter 3, the pulse output circuit 8 operated by the second clock CK1 while increasing or decreasing the count value of the buffer counter 3 operated by the first clock CK0 in real time.
Can output a counting pulse output. In the pulse output circuit 8, the usual format processing is performed to obtain output pulses φA and φB which are, for example, a count pulse signal and a U / D signal or a two-phase square wave signal.

FIG. 2 shows a specific circuit configuration of the buffer counter 3 and its surroundings. In FIG. 2, the buffer counter 3 has three 16 bits (1 as a sign bit).
Up / down counters 31a to 31b (including bits)
The example shown in FIG. Each of the second and third stages is an up / down counter capable of ± 2047 counts as a whole, with the output enable ENOUT, which is the overflow output of the previous stage, as the input enable ENIN. Counters 31a, 31
In order to ensure the carry between b and 31c, the first clock CK0 is input to each stage clock terminal CKB with a slight delay through the buffer delay circuits 32 and 33.

The most significant digit Q3 of the third-stage counter 31c is used as the sign bit MINUS. The all-zero detection circuit 4 is a NOR gate G4 that detects that each digit output of each stage counter 31a to 31c is all zero.
1, G42 and G43, and a NAND gate G44 for detecting a match between these outputs. Thus, the all-zero detection circuit 4 outputs AZ = 0 when the count value of the buffer counter 3 is zero, and outputs AZ = 1 otherwise.

The clock gate 6 receives the second clock CK
It comprises a NAND gate G61 for detecting a match between 1 and the output AZ of the all-zero detection circuit 4, and an inverter gate G62. As a result, when AZ = 0, the clock gate 6 is turned off, and while the buffer counter 3 has a count value (AZ = 1), the second clock CK1 passes through the clock gate 6 and outputs the output enable signal OUTEN. Is taken out as

The first stage counter 31a is provided with three mode control terminals, that is, terminals for selection signals SEL1 and SEL2 for selecting whether to count 1 or 2 and terminals for an up / down selection signal UP. I have. Table 2 below summarizes the combinations of the inputs of these three control terminals and the count mode.

[0021]

[Table 2]

The counter control gate 7 receives the source count pulse P
It is configured as shown in FIG. 2 to generate a control signal of Table 2 by a combination of UEN, up / down pulse U / D, output enable signal OUTEN, and sign bit MINUS. EX / NOR gate G71 is PUE
The selection signal SEL1 is generated by detecting a match between N and U / D. EX NOR gate G712 and NAND gate G7
Reference numeral 3 detects a match between MINUS and U / D, detects a match between the detection result and PUEN and OUTEN, and generates a selection signal SEL2. Also, an AND gate G7
4, G75, NOR gate G76, inverter G77,
G78 generates an up / down signal UP by a combination of MINUS, PUEN, and U / D.

As described above, according to this embodiment, while counting the source count pulse by the buffer counter 3 operated by the high-speed first clock CK0, the count pulse is simultaneously output by the low-speed second clock CK1. Buffer counter 3 in real time by counting pulse output
Is controlled to increase or decrease, and count pulses corresponding to the count value of the buffer counter 3 corresponding to the displacement amount are obtained. Therefore, even if the external counter has a low frequency, a high-speed moving speed of the displacement detector can be secured without being limited to this. The output cycle counter 5 for generating the second clock CK1 for determining the frequency of the output count pulse is made variable in frequency division ratio from the outside. For example, when the external counter can perform high-speed counting, the second clock C
Assuming that the frequency of K1 is the same as the first clock CK0, it can be connected to an external counter.

In this embodiment, the buffer counter 3
Is determined based on a balance between the movement range of the displacement detector 1 and the frequency of the output counting pulse. For example, if the number of digits is larger than the moving range, the output frequency can be lowered no matter how much, and the internal counting is performed by the buffer counter 3 operated by a high-speed clock. The detector movement speed is not limited to a low range. Even if the number of digits is smaller than the displacement detector movement range, the count value of the buffer counter 3 is added or subtracted for each count pulse output in real time, so that the output frequency is set high within the countable frequency range of the external counter. Then there is no problem. Thereby, the circuit scale can be reduced.

FIG. 4 shows a configuration example of the counting pulse output circuit 8, and FIG. 5 shows an operation timing chart thereof. Detailed description is omitted, but two D-type flip-flops FF1 and FF
2 and gates G81 and G82 for determining inputs to the flip-flops FF1 and FF2 based on these outputs, the OUTEN signal and the MINUS signal, thereby outputting two-phase square wave outputs φA and φB. .

[0026]

As described above, according to the present invention, the source counter pulse is counted using the buffer counter operated by the first clock, and at the same time, the count pulse corresponding to the count value is generated by the second counter. It is possible to provide a displacement measuring device that outputs a clock and enables counting by a low-frequency external counter.

[Brief description of the drawings]

FIG. 1 shows a block configuration of a displacement measuring device according to an embodiment of the present invention.

FIG. 2 shows a specific configuration example of a main part of the embodiment.

FIG. 3 shows a relationship between first and second clocks in the embodiment.

FIG. 4 shows a specific configuration example of a pulse output circuit of the embodiment.

FIG. 5 shows an operation timing of the pulse output circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Displacement detector, 2 ... Source count pulse generation circuit, 3 ... Buffer counter, 4 ... All zero detection circuit, 5 ... Output cycle counter, 6 ... Clock gate, 7 ... Counter control gate, 8 ... Count pulse output circuit.

Claims (4)

[Claims] 1. A displacement measuring device for outputting a number of count pulses corresponding to a displacement amount to be counted by an external counter based on an output of a displacement detector, wherein the displacement measuring device operates in synchronization with a first clock, and A source count pulse generating circuit that outputs a source count pulse having a width corresponding to the amount of displacement detected by the displacement detector and an up / down pulse for instructing up / down in accordance with the displacement direction; A buffer counter that counts up / down with a first clock; and operates with a second clock having a frequency equal to or lower than the first clock to generate the same number of count pulses as the count value of the buffer counter. A displacement measuring device comprising a pulse output circuit. 2. An output cycle counter for generating a second clock for dividing a frequency of the first clock to determine a frequency of a count pulse to be output; A combination of a source count pulse, an up / down pulse, and an output enable signal, which fetches a second clock as an output enable signal and supplies it to the pulse output circuit, in response to a count pulse output from the pulse output circuit 2. The displacement measuring device according to claim 1, further comprising a counter control gate for performing control to increase or decrease the count value of the buffer counter in real time. 3. The output cycle counter is configured such that the frequency of the second clock can be set to be equal to or lower than the frequency of the first clock by switching the frequency division ratio under the control of an external terminal. The displacement measuring device according to claim 2, wherein 4. The displacement measuring device according to claim 1, wherein an overflow terminal of the buffer counter is led out as an overspeed terminal.