JPH10340960A - Semiconductor device, hybrid semiconductor device and fabrication thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the size without increasing the region for arranging a repair link by arranging the repair link for switching from a detective circuit to a redundant circuit on an active region. SOLUTION: A repair link has interconnection width and pitch identical to those of normal interconnection wherein a first layer repair link 33 has one end connected through a second layer interconnection 31 with a normal memory cell and the other end connected through a second layer interconnection 32 with a common decoder and an interconnection 34 connected with a redundant memory cell is formed on the second layer. When a defective cell is specified, a liquid crystal mask is irradiated with a high output pulse laser light and a rectangular pattern luminous flux is projected to a part 38 which is thereby cut off to disconnect the detective cell. Subsequently, the liquid crystal mask is irradiated with a low output pulse laser light and a rectangular pattern luminous flux is projected to an intersecting part 39. Consequently, an interlayer insulation film between the repair link and the interconnection 34 is fused to connect the repair link with the interconnection 34 and the common decoder is switched to the redundant memory cell.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having a memory or a memory and a logic, a hybrid semiconductor device, and a method of manufacturing a semiconductor device.

[0002]

2. Description of the Related Art A first prior art is disclosed in
As described in Japanese Patent Application Laid-Open No. 69942, there is known a technique in which a laser beam is applied to a cutting link guided from an external wiring into a guard ring for preventing contamination from entering on a Si substrate and cut. .

[0003] As a second prior art, there is disclosed a "method of configuring a redundant circuit using a laser diffusion type porogram element" Transactions of the Institute of Electronics, Communication and Communication, '83 / 12 Vol.J66-C No.12 pp.903-910
According to the third prior art, a laser diffusion type program element is developed in which a high-resistance polysilicon in an electrically insulated state is irradiated with a laser beam from above to make an electrically short-circuited state. Using this, a redundant circuit composed of a latch circuit and a switch for switching wiring is formed, and this redundant circuit is applied to a 64K bit static RAM of 8K words × 8 bits, and a column decoder output signal is used for a normal decoder line selection. It is described for use in a decoder output replacement circuit for switching between a signal and a spare data line selection signal. Also, as a third prior art,
"Laser Diffusion Connection Technology for VLSI Programming (Laser Diffusio
n Connection Technology for VLSI Programming) A
nnals of the CIRP Vol. 32/1/1983, pp. 141-144. In this fourth prior art, a laser diffusion technique for connecting a polysilicon conductor has been developed for programming a VLSI memory. It is described that it was done.
A fourth prior art is disclosed in Japanese Patent Application Laid-Open No. Hei 4-23453.
As described in Japanese Patent Application Laid-Open No. H10-157, there is known a technique in which a desired portion of a link for repairing a defective bit in an LSI memory is irradiated with a laser beam having a pulse width of 1 ns or less to damage a lower layer without damaging the lower layer. .

[0004]

According to the first to third prior arts described above, in a LSI memory, a defective memory cell is cut by irradiating a rescue link with a laser beam or a high-resistance LSI is reduced to reduce a defective memory cell to a redundant memory. Techniques for switching to cells have been known. However, in the first to third prior arts,
Since the spot diameter for irradiating the laser beam is made larger than the width of the rescue link, the pitch of the rescue link must be about 10 to 12 μm. Therefore, the rescue link has to be provided on a region where no active element exists, since the light passes through the insulating film existing below and reaches the lower portion. On the other hand, the LSI memory is also highly integrated, and has a wiring width of about 0.35 μm and 256 MDRA for 64 MDRAM.
M is about 0.25 μm, and 1GDRAM is about 0.15 μm, which is closer to a crystal defect of Si, and the number of links for bit rescue is increased to about 2,000 to 20,000.

As a result, in the semiconductor device, the area where the rescue link is installed occupies a large proportion, so that the size of the entire semiconductor device must be increased. By the way, according to the fourth prior art, a rescue link can be cut by irradiating a desired portion of a defect bit rescue link in an LSI memory with a laser beam having a pulse width of 1 ns or less. It is also known that the lower layer is not damaged by the non-irradiation of laser light, but even if a semiconductor device such as an LSI is highly integrated,
No consideration has been given to an attempt to construct a semiconductor device without increasing the proportion of the area where the rescue link is provided.

[0006] An object of the present invention is to solve the above problems.
Even if a semiconductor device such as an LSI is highly integrated, the area occupied by the area for installing a rescue link for switching a defective circuit such as a defective memory cell to a redundant circuit such as a redundant memory cell can be reduced without increasing the size. It is an object of the present invention to provide a semiconductor device and a method of manufacturing the same, which can realize the semiconductor device. It is another object of the present invention to provide a semiconductor device and a method of manufacturing the same, which can improve short-circuit failure by relieving the necessary minimum number of bits.

It is another object of the present invention to reduce the size of a semiconductor device such as an LSI without increasing the proportion of a region where a programming element for adjusting electric characteristics is occupied even if the semiconductor device such as an LSI is highly integrated. An object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can be realized.

It is still another object of the present invention to reduce the size of a semiconductor memory device by eliminating a decoder provided to reduce the number of relief links and reducing the area occupied by redundant circuits. It is an object of the present invention to provide an improved semiconductor device. Still another object of the present invention is to provide a hybrid semiconductor device capable of realizing miniaturization.

[0009]

In order to achieve the above object, according to the present invention, in a semiconductor device, a rescue link for switching from a defective circuit to a redundant circuit is provided on an active area (active element area). It is characterized by having. According to the present invention, in a semiconductor memory device having a redundant memory cell and a memory cell, a rescue link for switching a desired bit in a defective memory cell to the redundant memory cell is provided in an active region (active area) of a memory including a peripheral circuit. Element area)
A semiconductor device provided above.

Further, according to the present invention, in a semiconductor memory device having a redundant memory cell and a memory cell, a repair link for switching a desired bit in a defective memory cell to the redundant memory cell is provided on a peripheral circuit of the memory. A semiconductor device.

According to another aspect of the present invention, there is provided a semiconductor memory device having a redundant memory cell and a memory cell, wherein a defective memory cell is separated by directly cutting a signal line of the defective memory cell. Device.

Further, the present invention is characterized in that in a semiconductor memory device having a redundant memory cell and a memory cell, a signal line of a defective memory cell is directly cut and a protective film is coated thereon. Semiconductor device.

According to the present invention, a memory and a logic are juxtaposed on a substrate, and a link for memory rescue is provided on an active area of the memory (an area in which an active element is provided), and programming for adjusting a logic characteristic is performed. A hybrid semiconductor device in which an element (a thin film resistor, a capacitor, an inductance, or the like) is provided on an active area of the logic (an area in which the active element is provided). Further, the present invention is a hybrid semiconductor device, wherein a logic and a memory are juxtaposed on a substrate, and the memory is constituted by a plurality of layers.

According to the present invention, in a semiconductor device, a rescue link for switching a defective circuit to a redundant circuit is provided on a region having an active element, and a pulse width of 1 ns or less with respect to the desired rescue link. A method of manufacturing the semiconductor device, wherein the defective circuit is switched to a redundant circuit by performing processing by aligning and irradiating the laser beam.

Further, according to the present invention, in a semiconductor memory device having a redundant memory cell and a memory cell, an active area of a memory including a peripheral circuit includes a rescue link for switching a desired bit in a defective memory cell to the redundant memory cell. A desired bit in a defective memory cell is switched to a redundant memory cell by performing processing by aligning and irradiating a laser beam having a pulse width of 1 ns or less with respect to the desired rescue link. This is a method for manufacturing a semiconductor device.

According to the present invention, in a semiconductor memory device having a redundant memory cell and a memory cell, a rescue link for switching a desired bit in a defective memory cell to the redundant memory cell is provided on a peripheral circuit of the memory. A desired bit in a defective memory cell is switched to a redundant memory cell by performing processing by aligning and irradiating a laser beam having a pulse width of 1 ns or less to the desired rescue link. It is a manufacturing method. Further, according to the present invention, in a semiconductor memory device having a redundant memory cell and a memory cell, a defective memory cell is irradiated with a laser beam having a pulse width of 1 ns or less directly by aligning and irradiating the signal line to cut the defective memory cell. A method for manufacturing a semiconductor device, comprising separating a cell.

Further, according to the present invention, in a semiconductor memory device having a redundant memory cell and a memory cell, a laser beam having a pulse width of 1 ns or less is directly aligned and irradiated to a signal line of a defective memory cell and cut. A method for manufacturing a semiconductor device, comprising separating a defective memory cell by using the method, and covering the defective memory cell with a protective film. The present invention also provides
In a semiconductor device, a programming element for characteristic adjustment is provided on an active region of a circuit, and the characteristic is adjusted by aligning and irradiating a laser beam having a pulse width of 1 ns or less to the desired programming element. This is a method for manufacturing a semiconductor device.

As described above, according to the above configuration,
Even if the degree of integration is increased, the size of the semiconductor memory device can be reduced without increasing the ratio of the area where the repair link for switching the defective memory cell to the redundant memory cell is occupied. Further, according to the configuration,
If a short-circuit defect, which is the cause of defective memory cells, occurs, the required minimum signal line is directly irradiated with a picosecond pulsed laser beam to separate it and eliminate the short-circuit defect. In addition, it is possible to prevent the temperature from rising locally, and to achieve reliable bit relief. That is, it is possible to remedy or correct the short-circuit failure with the minimum necessary number of bits.

Further, according to the above configuration, even if the semiconductor device is highly integrated, the size of the semiconductor device such as a microcomputer can be reduced without increasing the ratio of the area where the programming element for adjusting the electric characteristics is installed. can do. Further, according to the above configuration, in the semiconductor memory device, a decoder provided for reducing the number of relief links can be eliminated, and the area occupied by the redundant circuit can be reduced, thereby realizing miniaturization. Further, according to the above configuration, it is possible to realize a miniaturized hybrid semiconductor device having a logic and a memory juxtaposed on a substrate.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments according to the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a schematic configuration of a laser processing apparatus for processing by irradiating a picosecond pulse laser beam according to the present invention. This laser processing apparatus is disclosed in Japanese Patent Laid-Open No. 4-234.
As described in JP-A-53-53, a laser light source 2 that oscillates a picosecond pulsed laser beam 23 having a pulse width of 1 ns or less (100 to 300 ps) with a few mjoules, a half mirror 3, and an arbitrary pattern to be projected A XY table 7 on which the semiconductor device 1 is placed;
A control device 8 for controlling the XY table 7, an illumination light source 9 for a projection pattern, an illumination light source 10 for an object, a half mirror 11, an optical image of the pattern projected on the workpiece 1, An imaging device 12 that captures an optical image on the object 1,
Image determination processing device 13 and display means 1 such as a display
And a liquid crystal pattern control device 1 for controlling the liquid crystal mask 4
5 and a laser light source controller 16 for controlling the laser light source 2
Input means 17 for inputting a command signal for finely moving the XY table 7 or for inputting information on a rectangular pattern to be generated in the transmissive liquid crystal mask 4;
And a displacement meter 18 constituted by a laser length measuring device or the like for detecting the amount of displacement in the X and Y directions with high accuracy. The input means 17 is a CAD system 19 for designing a semiconductor device.
And a tester 20 for inspecting electrical characteristics of the semiconductor device.

First, a semiconductor device 1 such as a memory is positioned and mounted on an XY table 7. The transmissive liquid crystal mask 4 is CAD-based based on, for example, a defective bit in a memory inspected by the tester 20 by the input means 17.
It is controlled by the liquid crystal pattern control device 15 on the basis of information on the rectangular pattern input based on the shape and size and position information of the defective bit rescue link and the defective bit obtained from the system 19 and the defective bit, and the like. Is generated. The liquid crystal mask 4 on which the desired rectangular pattern has been generated is illuminated with illumination light emitted from the projection pattern illumination light source 9, and the generated desired rectangular pattern is projected by the projection processing lens 6 into the semiconductor device 1. Projected above. Further, the semiconductor device 1 is illuminated by illumination light emitted from the illumination light source 10 for the object via the half mirror 11 and the observation half mirror 5. An imaging device 12 installed behind the half mirror 11 captures an optical image obtained from the semiconductor device 1 and inputs the image signal to an image determination processing device 13. The image determination processing device 13 pattern-recognizes an optical image of a desired rectangular pattern (a region to be irradiated with a picosecond pulsed laser beam) projected based on the input image signal, and An optical image of the pattern (a region to be irradiated with a picosecond pulsed laser beam) 22 is displayed on the screen of the display unit 14. Then, in response to a matching start command input from the input means 17, a defective bit rescue link obtained from the CAD system 19 based on a defective bit in a memory, for example, which is inspected by the tester 20 by the input means 17, and a data line connected to the defective bit Control device 8 that receives feedback from displacement meter 18 based on the position information of the vehicle
The XY stage 7 is moved by the control of (1), and a light image of a desired rectangular pattern (a region to be irradiated with a picosecond laser beam)
Reference numeral 22 is positioned substantially on the defective bit relief link or the data line connected to the defective bit. Next, the image determination processing device 13 performs the desired rectangular pattern so that the image 22 of the optical image of the desired rectangular pattern detected from the imaging device 12 does not protrude from the data line leading to the defective bit relief link or the defective bit. The image 22 of the light image is calculated with respect to the shift amount of the image of the data line leading to the defective bit relief link or the defective bit, and the calculated shift amount is input to the control device 8. The control device 8 controls the XY stage 7 so that the input shift amount is detected from the displacement meter 18 so that the image 22 of the optical image of the desired rectangular pattern is connected to the defective bit relief link and the defective bit. The matching is performed so as not to protrude from the data line, and the matching state can be confirmed by displaying the result on the display unit 14.

When the matching state is confirmed by inputting using the input means 17 as described above, a start command signal for irradiating a picosecond pulse laser beam is transmitted from the image determination processing unit 13 to the laser light source control unit 16. The laser light source 2 oscillates and outputs a picosecond pulsed laser light 23,
The liquid crystal mask 4 is irradiated. Then, a picosecond pulsed laser beam 24 shaped into a desired rectangular pattern
Is projected onto the defective bit rescue link and the data line leading to the defective bit on the semiconductor device 1 to be processed.

By the way, in the wiring cutting process using a pulse laser beam, scattering removal as a thermal phenomenon occurs.
It takes more than 1 ns. Therefore, the pulse width is 1 ns
If the high-power laser light of the following pulse is slightly narrower than the wiring width and is irradiated with high accuracy at a desired position on the wiring on the semiconductor device 1, the pulsed laser light is used when the wiring material is used up. Is not irradiated, so that the wiring can be cut without the laser light penetrating below the wiring. That is, if the pulse laser beam has a pulse width of 1 ns or less, even if the power of the irradiation laser is increased so that the wiring can be cut, the laser pulse continues (1).
ns or less), the wiring material does not scatter and exists in the original place,
All the laser energy is received by the wiring material. For this reason, in a semiconductor device, S
The lower layer sandwiching the insulating film such as iO ₂ is not exposed to laser light, and does not cause damage. The peak power P required for cutting the wiring is approximately equal to the pulse width S.
Is inversely proportional to the double root of P = K (√ (So / S)) Po (Equation 1) where Po is the original peak power, So is the original pulse width, and K is a proportional constant. Therefore, if the pulse width is shortened by about two digits, for example, from about 100 ns to about 100 ps to 300 ps as in the present invention, the peak power P needs to be increased by about 10 to 20 times as compared with the conventional case. However, the required energy E is the product of the peak power P and the pulse width S, that is, E = P · S. Therefore, when K is around 1, it is proportional to the double root of the pulse width S, and is one digit larger than the conventional one. Only a small amount is required. However, since the wiring material receives all the energy from the laser beam, the wiring can be cut without damaging the lower layer.

Laser light having a short pulse width of 1 ns or less is
For example, when irradiating the wiring surface of Al or the like, the absorption of the energy is performed in a short time of about 10 to ¹⁵ sec, while the energy is converted into heat in the wiring of Al or the like.
A time of about 1 ns is required. Therefore, no matter how intense the pulse laser light is, if the pulse laser light is shorter than 1 ns, the laser pulse irradiation ends before the irradiated wiring changes due to the thermal phenomenon. It is unlikely that laser light enters after the removal, and a desired portion of the wiring can be cut without damaging the lower layer of the wiring. Semiconductor device 1
In the case where the laser light is slightly narrower than the width of the wiring and the irradiation is performed with high precision matching and the resistance is lowered to the wiring formed of high-resistance polysilicon or the like as a material, the lower layer may be damaged. Can be eliminated.

FIG. 2A shows an embodiment of a desired rectangular pattern generated in the liquid crystal mask 4 and projected on the semiconductor device 1. FIG.
1 shows an embodiment of a light image picked up from a camera.

FIG. 3, FIG. 4, and FIG. 5 show relief links provided corresponding to normal memory cells, respectively. In the case of the first embodiment shown in FIG. 3, the wiring width is substantially the same as the normal wiring (about 0.35 μm,
RAM has a pitch of about 0.25 μm, and 1GDRAM has a pitch of about 0.15 μm), one of which is connected to a normal memory cell through a second-layer wiring 31 such as Al, and the other is a common decoder. A rescue link 33 made of, for example, Al on the first layer connected to a wiring 32 made of, for example, Al on the second layer is formed on the second layer, and a wiring 34 made of Al or the like connected to the redundant memory cell on the second layer. Are formed.
Therefore, when a defective memory cell is specified in the tester 20, the rescue link 33 connected to the memory cell is determined.
At 38, the projection light flux 24 of the rectangular pattern generated on the liquid crystal mask 4 is slightly narrower than the wiring width and is matched with high accuracy, and is 1 ns or less (for example, 100 to 300 p).
s) A high-output pulsed laser beam having a pulse width of irradiating the liquid crystal mask 4 and irradiating the projection light flux 24 shaped into a rectangular pattern to the portion indicated by 38 to cut it, and a common decoder to send a defective memory Disconnect the connection to the cell.
Next, the repair link and the A connected to the redundant memory cell are connected.
The liquid crystal mask 4 is provided at a place 39 where the wiring 34 such as l intersects.
The projection light flux 24 shaped into a rectangular pattern generated at a time is slightly narrower than the wiring width and is matched with high precision, and a low-output pulse laser beam having a pulse width of 1 ns or less (for example, 100 to 300 ps) is supplied to the liquid crystal mask. 4, the projection light flux 24 shaped into a rectangular pattern is applied to the intersecting point 39 to melt the interlayer insulating film such as SiO ₂ existing between the rescue link and the wiring 34 to rescue the link. And the wiring 34, and a switching connection from the common decoder to the redundant memory cell is performed. Even in this embodiment, 1n
Using a pulsed laser beam having a pulse width of s or less, and configured to cut and connect by slightly narrower than the wiring width and irradiating with high precision alignment, without damaging the lower layer, Switching from a defective memory cell to a redundant memory cell can be performed.

In the case of the second embodiment shown in FIG. 4, the wiring width is substantially the same as that of a normal wiring (approximately 0.
35 μm, about 0.25 μm for 256 MDRAM, 1
About 0.15 μm in the case of a GDRAM) and a pitch,
One is connected to a normal memory cell through a wiring 31 of the second layer, such as Al, and the other is connected to a common decoder.
The first layer connected through a wiring 32 of, for example, Al
One of the layers is a relief link 33 made of, for example, Al, and one is connected to the redundant memory cell through a wiring 34 made of, for example, Al in the second layer and a wiring 35 made of, for example, Al in the first layer,
The other is connected to each of the rescue links 33, for example, Al.
Are formed. Therefore, when a defective memory cell is specified in the tester 20,
4 in the rescue link 33 connected to the memory cell
At a position indicated by 0, the projection light flux 24 shaped into a rectangular pattern generated on the liquid crystal mask 4 is slightly narrower than the wiring width and highly accurately matched, and is 1 ns or less (for example, 100 to 300 p).
s) A high-output pulsed laser beam having a pulse width of irradiating the liquid crystal mask 4 and irradiating a projection light beam 24 shaped into a rectangular pattern to the portion indicated by 40 to cut it, and a common decoder to send a defective memory Disconnect the connection to the cell.
Next, a wiring 34 made of Al or the like connected to a rescue link different from the rescue link and connected to the redundant memory cell.
41 in the rescue link 36 connected to
45, the projection light flux 24 shaped into a rectangular pattern generated in the liquid crystal mask 4 is slightly narrower than the wiring width, and is matched with high precision, and 1 ns or less (for example, 100 to 30).
By irradiating the liquid crystal mask 4 with a high-power pulse laser beam having a pulse width of 0 ps) and irradiating the projected light flux 24 shaped into a rectangular pattern onto the portions 41 to 45 and cutting the same, redundancy from a common decoder is achieved. Switching to a memory cell is performed. In the case of this embodiment as well, the pulse laser light having a pulse width of 1 ns or less is used, and the width is slightly narrower than the wiring width. The switching from the defective memory cell to the redundant memory cell can be performed without affecting the operation.

In the case of the third embodiment shown in FIG. 5, the wiring width is substantially the same as that of a normal wiring (approximately 0.
35 μm, about 0.25 μm for 256 MDRAM, 1
About 0.15 μm in the case of a GDRAM) and a pitch,
One is connected to a normal memory cell through a wiring 31 of the second layer, such as Al, and the other is connected to a common decoder.
The first layer connected through a wiring 32 of, for example, Al
One of the layers is a relief link 33 made of, for example, Al, and one is connected to the redundant memory cell through a wiring 34 made of, for example, Al in the second layer and a wiring 35 made of, for example, Al in the first layer,
The other is formed with a rescue link 37 made of, for example, high-resistance polysilicon connected to each of the rescue links 33. Therefore, when a defective memory cell is specified by the tester 20, a projection light beam 24 shaped into a rectangular pattern generated on the liquid crystal mask 4 is provided at a location indicated by 40 in the rescue link 33 connected to the memory cell. Is slightly narrower than the wiring width, and is matched with high accuracy.
The liquid crystal mask 4 is irradiated with a high-output pulse laser beam having a pulse width of (00 to 300 ps), and the projection light beam 24 shaped into a rectangular pattern is irradiated and cut at the position indicated by 38 to be cut off from a common decoder. Disconnect the connection to the defective memory cell. Next, the liquid crystal mask 4 is generated at a location indicated by 47 in the rescue link 37 such as a high-resistance polysilicon connected to the rescue link and the wirings 34 and 35 of Al or the like connected to the redundant memory cell. The projection light beam 24 shaped into a rectangular pattern is slightly narrower than the wiring width to match with high accuracy, and is 1 ns or less (for example, 100 to 30).
The liquid crystal mask 4 is irradiated with a low-output pulse laser beam having a pulse width of 0 ps), and the projection light beam 24 shaped into a rectangular pattern is irradiated on the spot 47 to rescue the link 3.
By lowering the resistance of the wiring 7, the wiring 32 and the wiring 35 are connected, and a switching connection from the common decoder to the redundant memory cell is performed. Also in the case of this embodiment, the pulse laser light having a pulse width of 1 ns or less is used to cut and connect by irradiating with a narrower width than the wiring width and matching with high precision, so that the lower layer is formed. It is possible to switch from a defective memory cell to a redundant memory cell without causing damage.

As described above, the switching from the defective memory cell to the redundant memory cell can be performed without damaging the lower layer, so that as shown in FIGS. 6 and 7, the rescue links 33, 36, The memory cell is highly integrated by arranging the region 49 provided with 37 at an arbitrary position on the region where the active elements 51, 52, and 53 formed of, for example, memory elements in the semiconductor memory device 1a are formed. Even when a normal memory cell or a redundant memory cell is connected to a rescue link, the routing distance of the wiring can be minimized to relieve a defective memory cell without losing high speed. Can be realized. FIG. 6 shows that, in the semiconductor memory device 1a, an area 49 provided with the rescue links 33, 36, 37 is provided on an area in which active elements (active areas) 51, 52, 53 formed of, for example, memory elements are formed. It is a sectional view showing an embodiment. MOSLS
In I, 51 indicates a source / drain formed of a pMOS region, 52 indicates a source / drain formed of an nMOS region, and 53 indicates a source / drain formed of an nMOS region. Thus, the rescue links 33, 36, 37
Is provided at an arbitrary position on a region in which active elements (active regions) 51, 52, 53 formed of, for example, memory elements are formed, so that even if memory cells are highly integrated, a high level is obtained. Miniaturization can be realized corresponding to integration.

FIG. 7 shows the memory area 61 and the peripheral circuit area 6.
2 is a plan view showing an embodiment in which a region 49 provided with relief links 33, 36, and 37 is arranged on a memory region 61 in a semiconductor memory device 1a in which a common decoder region 63 and a common decoder region 63 are formed. . By arranging the area 49 provided with the rescue links 33, 36, and 37 at an arbitrary position in the memory area 61 and the peripheral circuit area 62, even if the memory cells are highly integrated, high integration is achieved. Therefore, miniaturization can be realized in correspondence with the above. However, when the area 49 provided with the rescue links 33, 36, and 37 is disposed on the memory area 61, naturally, the process such as film formation and etching for providing the rescue links 33, 36, and 37 on the memory area 61 is performed. Is required, and a uniform process is not performed over the entire area of the memory.
Since the memory cell characteristics may be non-uniform, it is desirable to provide the rescue links 33, 36, 37 on the peripheral circuit area 62. Also in the peripheral circuit region 62, it is preferable that the wiring is shortened by providing it directly on a peripheral circuit such as a decoder other than the switch circuit 83 to reduce the resistance. FIG.
FIG. 3 is a diagram showing a circuit configuration in a semiconductor memory device 1a having a rescue link. 81 indicates a normal memory cell. 82 indicates a redundant memory cell. Reference numeral 83 denotes a switch circuit connected to the memory cells in each column. Reference numeral 84 denotes a rescue link that is connected to each switch circuit and switches from a defective memory cell to a redundant memory cell. 8
Reference numeral 5 denotes a common decoder that generates a signal for selecting a data signal input to each switch circuit. Reference numeral 86 denotes a word line to the memory cells in each row, 87 denotes a common line, and 88 denotes a data line.

In the above, the embodiment in which the switching from the defective memory cell to the redundant memory cell is performed by using the repair link has been described. However, since the switching can be performed without damaging the lower layer, FIG. In this way, instead of the rescue link, the points 90 and 91 of the crosses of the signal lines such as data lines and bit lines connected to the respective memory cells are irradiated with picosecond pulse laser light similarly to the rescue link. As a result, direct disconnection eliminates the input of data to the defective memory cell, and instead, it is possible to switch to the redundant memory cell by software processing to the common decoder 85. FIG. 9 is a diagram showing a circuit configuration in a semiconductor memory device 1a having no rescue link. 81 indicates a normal memory cell. 82 indicates a redundant memory cell.
Reference numeral 83 denotes a switch circuit connected to the memory cells in each column. A common decoder 85 generates a signal for selecting a data signal input to each switch circuit. 86 denotes a word line to the memory cells in each row, 87 denotes a common line, 88 denotes a data line, and 89 denotes a complementary data line (complementary bit line).
In addition, since a signal line such as a complementary data line (complementary bit line) 89 or the like may be short-circuited as a defective memory cell, a short-circuit failure may cause another memory only by switching to the redundant memory cell 82 as it is. It is not possible to improve the badness of the cell, the increase in power consumption, and the increase in the local temperature. By the way, one of the signal lines such as the complementary data line 89 is connected to the switch circuit 83, and the other is connected to the load circuit (LAOD). A cross-section of a signal line such as a complementary data line connected to a memory cell adjacent to the defective memory cell is directly cut by irradiating a picosecond pulsed laser beam similarly to the above-described rescue link, thereby forming a load circuit. By separating, short-circuit failure can be eliminated. As described above, the signal line such as the complementary data line or the like can be directly irradiated with the picosecond pulse laser beam and cut, so that the defective bit can be relieved or corrected at a minimum. Further, a power supply line which is also a signal line connected to a defective memory cell can be cut and separated by directly irradiating a picosecond pulsed laser beam.

In the embodiment described above, a guard ring for preventing corrosion and intrusion cannot be formed around the rescue link with the increase in the degree of integration, and therefore, as shown in FIG. After irradiating a picosecond pulse laser beam to the wiring 101 such as a relief link or a data line to perform a cutting process or the like, protection is performed by applying a final passivation film of, for example, P-Si ₃ N ₄ to about 0.2 μm. can do. That is, also for the hybrid semiconductor device 1b to be described later, the programming element 113 for adjusting the logic characteristics in the logic circuit 111 is irradiated with a picosecond pulse laser beam to perform trimming processing, etc. After irradiating picosecond pulse laser light to the wiring 49b such as a cutting process, for example, P-Si
The ₃ N ₄ become final Paji coacervation film can be protected by applying about 0.2 [mu] m.

As described above, the semiconductor memory device 1
7A, it is not necessary to arrange the area provided with the rescue link outside the active area (the area where the active elements are installed) composed of the memory area 61 and the peripheral circuit area 62. As a result, the memory cells are highly integrated. Even if the number of wirings such as a rescue link for switching a defective memory cell to a redundant memory cell is increased, the size can be reduced in response to high integration without being greatly affected by the increase.

Further, in the semiconductor memory device 1a, the signal line connected to the defective memory cell is directly irradiated with the picosecond pulsed laser beam to be separated, whereby the short-circuit defect can be eliminated. Inconvenience due to short-circuit can be improved by the limited bit relief. Next, an embodiment of a hybrid semiconductor device having both a logic circuit and a memory circuit will be described. FIG. 11 is a plan view showing an embodiment of a hybrid semiconductor device having both a logic circuit including a microcomputer and a memory circuit. FIG. 12 is a partial side sectional view of FIG. The hybrid semiconductor device 1b includes a logic circuit 111 including a microcomputer and a memory circuit 121 having a plurality of stages (a plurality of layers).
Reference numeral 131 denotes an electrode for connection to the outside. As shown in FIG. 12, a logic circuit 111 composed of a microcomputer
A logic element and a wiring layer 112 composed of, for example, seven or more layers are formed on a substrate 110 such as the above.
i, a memory element, a plurality of wiring layers 122 thereon, and a plate member 123 such as Si thereon.
And a memory element formed on the plate member 123 and a wiring layer 124 composed of a plurality of layers formed thereon. Especially S
The plate member 123 such as i is formed by forming Si or the like on the wiring layer 122.

In the logic circuit 111, a programming element (such as a thin film resistor or a capacitor or an inductance) 113 for adjusting the logic characteristics is provided on the uppermost layer of the wiring layer 112 on the active region of the logic.
Are formed. In the memory circuit 121,
In the uppermost layer of the wiring layers 122 and 124 of each stage, regions 49a and 49b in which wiring such as a rescue link for switching a defective memory cell to a redundant memory cell are formed.
In addition, a programming element (such as a thin film resistor, a capacitor, or an inductance) for adjusting the logic characteristics 11
Trimming to 3 involves projecting and irradiating the picosecond pulsed laser light to a desired portion of the thin metal film with the liquid crystal mask 4 shaping it into a desired rectangular pattern and matching the position and pattern shape. Done by As a result, it is possible to perform trimming to the programming element 113 for adjusting the logic characteristics without allowing the laser light to penetrate into the lower layer, and to optimize the electrical characteristics of the logic.

In addition, at a desired position of a wiring such as a rescue link for switching a defective memory cell formed on the uppermost layer of the wiring layers 122 and 124 of each stage, which are stacked and manufactured in the memory circuit 121, to a redundant memory cell. On the other hand, the above-mentioned picosecond pulsed laser light is shaped into a desired rectangular pattern by the liquid crystal mask 4 and projected and irradiated in a state where the position and the shape of the pattern (pattern width) are matched, so that the laser light is formed in the lower layer. It is possible to switch a defective memory cell to a redundant memory cell without invading the memory cell. As described above, in a hybrid semiconductor device having both a logic circuit and a memory circuit, miniaturization can be realized by configuring the memory circuit in a plurality of layers. Further, in a hybrid semiconductor device having both a logic circuit and a memory circuit, an area where a programming element for adjusting a logic characteristic and an area where a rescue link are provided are changed to an active area of the logic and the memory (the logic and the memory). Area where active elements are installed)
It is not necessary to place it outside the device, and as a result, to optimize the electrical characteristics of the logic and relieve the defective memory cell,
And miniaturization can be realized. In the above, the embodiment of the hybrid semiconductor device 1b has been described.
Obviously, the present invention can be applied to a case where the semiconductor device is configured only with a logic circuit.

Next, another embodiment of the semiconductor memory device 1a 'will be described with reference to FIGS. Specifically, it is described in JP-A-5-189996. FIG. 13 is a diagram showing the overall circuit configuration of the semiconductor memory device 1a '. The external terminal BP has a power supply voltage V
cc and the reference voltage Vss are applied. Power supply voltage V
cc is, for example, an operation voltage 5 [V] of the circuit and a reference voltage Vs.
s is, for example, the circuit ground voltage 0 [V]. And
The semiconductor memory device 1a 'includes a power supply voltage conversion circuit (step-down power supply circuit or regulator) VRC. The power supply voltage conversion circuit VRC is provided with a power supply voltage Vc supplied from the outside.
For the purpose of lowering the power internally,
A step-down power supply voltage Vdd is supplied to a part of the peripheral circuit. As the power supply voltage Vdd, for example, 4 [V] or less is used. In each of the upper and lower regions of the external terminal BP, a part RC of an indirect peripheral circuit among peripheral circuits such as an address buffer circuit and a predecoder circuit is arranged. This indirect peripheral circuit RC includes a power supply voltage conversion circuit VR
A step-down power supply voltage Vdd stepped down at C is supplied. Peripheral circuits including indirect peripheral circuits other than the indirect peripheral circuit RC and direct peripheral circuits, specifically, decoder circuits (X decoder circuit XDEC, Y decoder circuit YDEC), control circuit CC, sense amplifier circuit SA, output / input buffer circuit Each of the DOB, DIB, and memory cell array MM has:
An external power supply voltage Vcc is supplied.

FIG. 14 is a plan view of a chip showing one embodiment of the semiconductor memory device 1a 'according to the present invention. Four memory arrays MA1 to MA4 are located above a number of bonding pads BP arranged in the center of the semiconductor substrate SB, and four memory arrays MA are located below the bonding pads BP.
5 to MA8 are arranged. Each memory array MA1
In MA8 to MA8, the area closer to the BP is the redundant memory array areas MAR1 to MAR8, and the area outside the area is the memory array areas MAN1 to MAN8. Each of the memory arrays MA1 to MA8 is divided into 64 memory mats, although not particularly limited. Here, the redundant memory array regions MAR1 to MAR8 are regions in which, when a memory cell included in the memory array regions MAN1 to MAN8 has a defect, a redundant memory cell for replacing the defective memory cell exists. .
The semiconductor memory device 1a 'of the present embodiment employs a divided word line structure having a main word line common to all memory mats of the individual memory arrays MA1,..., MA8 and a subword line wired for each memory mat. Is done. M
WDEC / DRv is the memory array area MAN1,.
A main word line driver and address decoder corresponding to AN8, and MWRDRV is a main word line selection drive circuit corresponding to the redundant memory array areas MAR1,..., MAR8. In the memory array MA1, S
WDEC DRV101 to SWDEC DRV164
Are drivers and decoders for the sub-word lines, and are SWDEC / DRVs 501 to S in the memory array MA5.
The WDEC / DRV 564 is a sub-word line driver and decoder, and other memory arrays also have a sub-word line driver and decoder. PER denotes various peripheral circuits in units of a memory array, such as an address input buffer (DIB) and a column address decoder (YDE).
C), a column selection circuit (CSW), a data input / output buffer (DOB), a redundancy program circuit (RPGM), and the like. MBR is a redundant memory cell area provided with redundant line bit lines.

In the arrangement configuration of the memory arrays arranged vertically above and below the BP, the memory array areas MAN1 to MA4 of the memory arrays MA1 to MA4 arranged above are arranged.
When a defective memory cell is present in N4, the redundant memory cell for replacing the defective memory cell and repairing the defective memory cell is B
The lower redundant memory array area MAR5 to M
AR8 is assigned. Similarly, memory array area MAN5 of memory arrays MA5 to MA8 arranged on the lower side
The redundant memory cells for repairing the defective memory cells existing in MAN8 to MAN8 are assigned to the upper redundant memory array regions MAR1 to MAR4 sandwiching the BP. That is, the memory cells to be rescued by the redundant memory cells and the redundant memory cells to be rescued there are arranged in different memory arrays or memory mats across the BP. FIG. 15 is a schematic block diagram focusing on the connection relation of the circuit blocks shown in the chip plan view shown in FIG. In the figure, in a block denoted by 151, memory cells and redundant memory cells included in the memory arrays MA1 to MA8 are arranged in a matrix. The block indicated by 152 is an address signal x0.
To x9, y0 to y9, a circuit block (decoder / driver (DEC / DRV) for forming a signal for selecting a memory cell and a redundant memory cell, and for driving a main word line, a sub word line, and the like. A block 152A included in the block 152 is a redundant program circuit (RPGM) for programming an address of a defective memory cell to be replaced with a redundant memory cell, and 153 is a column selection circuit including a column selection switch circuit CSW and the like. Block 152 in the circuit (CSW)
The data line is selected according to the column selection signal generated in step (1). Reference numeral 154 denotes an ATD pulse circuit, which is a control timing signal φDE, φ for controlling the switch circuit CSW for pre-equalizing data lines and common data lines included in the circuit block 151 to a desired level for its operation.
This is a circuit block that forms CD, φSA, φDB, and φMA in synchronization with a change in an address signal. The timing signals φDE, φCD, φSA, φDB, and φMA are used to equalize predetermined nodes such as data lines, common data lines, sense amplifiers, and data output buffers during non-operation and initialize the nodes to a desirable level for operation. Used.
The address signals x0 to x9 and y0 to y9 are supplied to circuit blocks 152 and 154 via an address buffer 155. The column selection circuit 153 is connected to a sense amplifier circuit 156 and a write amplifier circuit 157.
The read data amplified by the sense amplifier circuit 156 is
Data output to the outside via the output buffer circuit 158 and externally applied to the input buffer circuit 159 is written to a predetermined memory cell via the write amplifier circuit 157. In the figure, reference numeral 160 denotes a control circuit (CC).
Although not particularly limited, the chip select signal cs * (symbol * means a signal line to which the chip select signal cs * is not attached, an inverted signal line or an inverted signal of the signal, or a low enable signal as an external access control signal. Signal), a write enable signal we * and an output enable signal oe * are supplied, and the internal operation mode is determined according to the signals. The chip select signal cs * indicates chip selection by its high level. The write enable signal we * instructs a write operation by a high level. The output enable signal oe * indicates a read operation by its high level.

FIG. 16 shows a detailed circuit in the vicinity of the memory mats MM101 and MM501. In the figure, a memory mat MM101 representatively shown includes a memory cell region MMN101 (included in a memory array region MAN1) and a redundant memory cell region MMR101 (included in a redundant memory array region MAR1). . Memory mat MM51 representatively shown includes memory cell region MMN501 (included in memory array region MAN5) and redundant memory cell region MMR501 (included in redundant memory array region MAR5). The redundant memory cell region MMR101 is provided with a redundant memory cell RM for replacing and repairing a defective memory cell existing due to a defect in the memory cell region MMN501.
This is a region where C is formed. Similarly, the redundant memory cell region MMR501 is a formation region of a redundant memory cell RMC for replacing and repairing a defective memory cell existing in the memory cell region MMN101 due to a defect. Typically, one main word line MWL11 is shown in memory cell region MMN101 of memory mat MM101.
In the memory cell area MMN101, there are actually four sub-word lines (corresponding to the word lines 86 connected to the normal memory cells 81 in FIG. 8) corresponding to one main word line. However, the figure typically shows two sub-word lines SWL11 and SWL14. Representatively, one redundant main word line MWLR11 is shown in redundant memory cell region MMR101. In the redundant memory cell region MMR101, there are actually four sub-word lines corresponding to one redundant main word line, but in the figure, two redundant sub-word lines SWLR1 are representatively shown.
1, SWLR 14 (in FIG. 8, redundant memory cell 8
2 corresponds to the word line 86. ). The main word line is formed of a metal wiring such as tungsten, and the sub-word line is formed of, for example, a polysilicon wiring also serving as a gate of a selection MOSFET constituting a memory cell. Each sub-word line is coupled to a select terminal of a memory cell MC, and each redundant sub-word line is coupled to a select terminal of a redundant memory cell RMC, and the memory cells MC and RMC arranged in the same column are connected.
Data input / output terminals are complementary bit lines (complementary data lines)
BL11, BL11 * (in FIG. 8, complementary data lines 89 connected to normal memory cells 81 and redundant memory cells 82 correspond to each other). One ends of the complementary bit lines (complementary data lines) BL11 and BL11 * are connected to a representative column selection switch circuit CSW1.
1 (corresponding to a switch circuit 83 provided in a normal memory cell 81 and a redundant memory cell 82 in FIG. 8) (in FIG. 8, a common line 87 and a data line And a complementary bit line (complementary data line) BL
11, the other end of BL11 * is connected to a load circuit (LOAD). The common data lines CD11 and CD11 *
The input terminal of the sense amplifier SA1 is coupled, and the output terminal of the write amplifier WA1 is coupled. The write amplifier WA1 is supplied with write data from the input buffer DIB1. The output of the sense amplifier SA1 is provided to an output buffer DOB1. The input buffer DI
The output operation of the B1 and the output buffer DOB1 is controlled by setting the selection signal XS to a high level.

In the figure, one main word line MWL51 and one sub word line SWL51 are typically shown in the memory cell area MMN501 of the memory mat MM51. The redundant memory cell region MMR501 typically shows one redundant main word line MWLR51 and one redundant sub-word line SWLR5. The main word line is formed of, for example, a metal wiring such as tungsten, and the sub-word line is a selection MOS constituting a memory cell.
It is formed of, for example, a polysilicon wiring also serving as a gate of the FET. Each sub-word line is coupled to a select terminal of a memory cell MC, and each redundant sub-word line is coupled to a select terminal of a redundant memory cell RMC, and data of a memory cell MC and a redundant memory cell RMC arranged in the same column. The input / output terminals are connected to complementary bit lines BL11 and BL11 * (FIG. 8).
Corresponds to the complementary bit line 89 connected to the normal memory cell 81 and the redundant memory cell 82. )
Connected in common. Complementary bit lines BL11, BL11 *
Is a column selection switch circuit CSW5 representatively shown.
1 (corresponding to the switch circuit 83 provided in the normal memory cell 81 and the redundant memory cell 82 in FIG. 8) (in FIG. 8, the common line 87 and the data line Line 88 corresponds). Common data lines CD51, CD51
To *, the input terminal of the sense amplifier SA5 is coupled and the output terminal of the write amplifier WA5 is coupled.
Write data is supplied from the input buffer DIB5 to the write amplifier WA5. The output of the sense amplifier SA5 is provided to an output buffer DOB5. The input buffer DIB5 and the output buffer DOB5 output a selection signal X
The output operation is controlled by setting S * to a high level. The output terminals of the output buffers DOB1 and DOB5 and the output terminals of the input buffers DIB1 and DIB5 are commonly connected to one predetermined bonding pad BP. The memory cell MC and the redundant memory cell RMC are, although not particularly limited, 6-transistor static storage elements of a complementary MOS circuit type, and one input of a pair of CMOS inverters is cross-coupled to the other output. And an N-channel type selection MOSFET connected to both input / output terminals. The data input / output terminal of the memory cell MC is
For example, it is a drain electrode of both selection MOSFETs,
The selection terminal of the memory cell MC is used as the gate electrode of the selection MOSFET.

In one memory mat MM101,
Four sub word lines SWL11 to SWL14 are connected to the one main word line MWL11. The driver for driving the sub-word line is a NAND inverter gate S
One of the input terminals is coupled to the main word line MWL11, and the other input terminal is supplied with a selection control signal. The selection control signal supplied to the NAND inverter gate SWDRV11 is x0.x1. (Y4.y5.y6.y7.y8.y
9) Negated inverter gate SWDR
The selection control signal supplied to V12 is x0 * .x1.
(Y4 · y5 · y6 · y7 · y8 · y9) · CS, and the selection control signal supplied to the NAND inverter gate SWDRV13 is x0 · x1 * · (y4 · y5 · y
6 · y7 · y8 · y9) · CS, and the selection control signal supplied to the NAND inverter gate SWDRV14 is x0 * · x1 * · (y4 · y5 · y6 · y7 · y8
• y9) · CS. In these selection control signals, two bits x0 and x1 are regarded as bits indicating which of the four sub-word lines is to be selected. y
The six bits of 4, y5, y6, y7, y8, and y9 are regarded as a memory mat selection signal, and (y4, y5, y6,
y7, y8, y9) are used as y-address predecode signals for memory mat selection. CS is an internal control signal indicating chip selection.

A driver MWDRV for driving one main word line MWL11 is constituted by, for example, a NAND inverter gate, and has x-system address bits x2 and x.
An 8-bit signal obtained by pre-decoding 3, x4, an 8-bit signal obtained by pre-decoding x-system address bits x5, x6, and x7, and a 4-bit signal obtained by pre-decoding x-system address bits x8, x9, and signal CS. , A predetermined signal selected bit by bit is supplied. The redundant main word line selection drive circuit MWRDRV is an example of a level forcing means for forcing a main word line for a redundant memory cell to be associated with a relief means described later to a selection level irrespective of an output of the relief means. Figure 1
6 shows the details. The circuit MWRDRV includes, although not particularly limited, an n-channel MOSFET Q1 and a fuse (repair link) FUS1 that are switch-controlled by receiving the chip select signal CS at a gate between a power supply terminal Vdd and a ground terminal GND. An inverter INV1 connected in series to obtain an inverted output by inputting the level of the coupling node is provided.
TQ2 is connected to the input of the inverter INV1 and the ground terminal GN.
D. Further, inverters INV2 and INV2 functioning as drivers for amplifying the output of the inverter INV1.
3, and the redundant main word line MWLR11 is driven by the output of the inverter INV3. When the fuse (rescue link) FUS1 is not cut, the redundant main word line is forced to a non-selection level such as a low level. Therefore, if the chip select signal CS is set to a chip select level such as a high level, the redundant main word line to be used for the relief is set to the select level without requiring a logic operation such as an x-address decoding operation. Driven.

For memory cell regions MMN101 and MMN501 included in memory mats MM101 and MM501 corresponding to the upper and lower portions of the chip, signals for selecting sub-word lines (SWL11-SWL51-) included therein are provided. , The (y4.y5.y6.
y7, y8, y9) and the decode signals (x0.x1), (x0 * .x1), (x0.x) regarded as the subword line select signals.
1 *) and (x0 * .x1 *) are commonly used. These signals are ANDed by the NAND inverters AG11, AG14, AG51 shown as representatives,
Drivers SWDRV11, SWDRV14, SW representatively shown with the corresponding NAND inverter gates
DRV 51 is provided as a selection control signal. The most significant bit x9 included in the x-system address signal for selecting the main word line MWL11 indicates whether to select the upper side or the lower side of the memory array arranged above and below the BP. Considered a bit. Therefore, the y-system memory mat selection signal (y4.y5.y6.y7.y)
Even if 8 · y9) is commonly applied to the upper and lower pairs of memory mats, one of the main word lines is driven to the selected level only by the memory mats.

On the other hand, in FIG. 16, for the redundant memory cell regions MMR101 and MMR501 included in the memory mats MM101 and MM501 corresponding to the upper and lower portions of the chip, the sub-word lines (SWLR11) included therein are included.
, SWLR51 ...,)
The y-system memory mat select signal (y4
, Y5, y6, y7, y8, y9), and redundant selection signals SIG1 to SIG4 and SIG5 to SIG8 which are regarded as signals indicating whether to select a redundant memory cell region or which redundant sub-word line is used. Is done. These signals are ANDed by representatively shown NAND inverter gates AGR11, AGR14, and AGR51, and the representatively shown driver SWRDRV1 composed of the corresponding NAND inverter gates is obtained.
1, SWRDRV14 and SWRDRV51 are provided as selection control signals. FIG. 17 shows a redundant selection signal SIG.
As an example of a redundant program circuit for forming 1 to SIG8, redundant memory cell regions MMR101 and MMR101
A configuration example focusing on 501 is shown. Redundant program circuit R
PGM1 to RPGM8 are based on the same circuit configuration. FIG. 18 typically shows a redundant program circuit RPG
The detailed example of M1 is shown. Redundant program circuit RPGM1
Is an x-system 10-bit internal complementary address signal (x0,
x0 *) to (x9, x9 *) in units of 10 bits, and program units PGM for programming which of the non-inverting and inverting complementary address bits are to be selected.
U. Each program unit PGMU includes, but is not limited to, a CMOS transfer gate TG1 arranged on a transmission path of a non-inverting bit (for example, x0);
C arranged in the transmission path of the inverted bit (for example, x0 *)
MOS transfer gate TG2, and a fuse program circuit for complementary switch control of CMOS transfer gates TG1 and TG2. This fuse program circuit is not particularly limited, but includes an n-channel MOSFET Q3, which is switch-controlled by receiving the chip select signal CS at its gate, between a power supply terminal Vdd and a ground terminal GND, and a fuse (rescue link) FU2 Are connected in series, and an inverter INV4 for inputting the level of the coupling node to obtain an inverted output is provided.
Are disposed between the input of the inverter INV4 and the ground terminal GND, and an inverter INV5 that receives the output of the inverter INV4 and obtains an inverted output is provided. The output of the inverter INV4 is the p-channel MOSFET of the CMOS transfer gate TG1 and the n-channel MOSFET of the CMOS transfer gate TG2.
It is supplied to the gate of the OSFET. The inverter IN
The output of V5 is n of the CMOS transfer gate TG1.
It is supplied to the gates of the channel type MOSFET and the p-channel type MOSFET of the CMOS transfer gate TG2.

The fuse (link for rescue) FUS2
In the non-cut state, the transfer gate TG1 is turned on, the transfer gate TG2 is turned off, and a non-inverting bit represented by x0 is selected and transmitted to the subsequent stage. When the fuse FUS2 is cut, an inverted bit represented by x0 * is selected and transmitted to the subsequent stage. Redundant program circuit R
In the PGM1, a circuit indicated by RSEL is a redundancy selection circuit, like the program unit PGMU, a fuse (repair link) FUS3 and an n-channel type MO.
SFETs Q5 and Q6, inverters INV6 and INV7,
It is constituted by INV8. This redundancy selection circuit RSE
L outputs a high-level signal by cutting the fuse FUS3 when a defective memory cell is rescued by a redundant memory cell. As shown in FIG.
The outputs of the program units PGMU and the output of the redundancy selection circuit RSEL are supplied to a NAND inverter gate AND, and the selection signal SIG1 is formed by the logical product of the input signals. Therefore, the fuses FUS2 and FUS2 are set so that all inputs of the NAND inverter gate AMD become high level for the x-system address signal to be relieved.
By programming the disconnected / non-disconnected state of US3, the x-system address to be relieved is programmed.
The other redundant program circuits RPGM2 to RPGM8 are similarly configured and form the selection signals SIG2 to SIG8. As shown in FIG. 17, the selection signals SIG1 to SI
G4 is supplied to the NOR gate NOR1, and similarly, the selection signals SIG5 to SIG8 are supplied to the NOR gate NOR2. Outputs of the NOR gates NOR1 and NOR2 are supplied to an AND gate AND composed of a NAND gate and an inverter, and form a relief signal INH *. The rescue signal INH * is used for generating the signals XS and XS *. As is apparent from the generation logic of the rescue signal INH *, the rescue signal INH * is set to a high level during an access operation in which the redundant memory cell RMC is not selected at the time of memory access (redundant memory cell non-selective access).
At the time of the access operation in which the redundant memory cell RMC is selected (at the time of the redundant memory cell selective access), the relief signal INH *
Is driven low.

FIG. 19 shows an example of a switching control circuit for generating the signals XS and XS *. The switching control circuit includes an inverter INV9 and CMOS transfer gates TG3, TG4, TG5, TG6,
The most significant bits x9 and x9 * of the x-system address signal and the rescue signal INH * are input. At the time of the non-selective access of the redundant memory cell, the relief signal INH * is set to a high level.
At this time, transfer gates TG3 and TG5 are turned on, whereby selection signal XS is set to the same logic level as bit x9, and selection signal XS * is set to the same logic level as bit x9 *. According to the present embodiment, x9 is regarded as a bit indicating the selection of the upper memory array shown in FIGS. 14 and 16 by its high level, and x9 * is determined by its high level in FIGS. It is regarded as a bit indicating that the lower memory array shown is selected. Therefore, at the time of the non-selective access of the redundant memory cell, data output buffer DO typically shown in FIG. 16 is typically set in accordance with the logic level of internal complementary address bits x9 and x9 * according to an externally supplied address signal.
Either B1 or DOB2 operation is selected. At the time of redundant memory cell selection access, the relief signal INH * is set to low level. At this time, the transfer gate T
G4 and TG6 are turned on, thereby causing the selection signal XS to be opposite to the case of the redundant memory cell non-selective access.
Is set to the same logic level as bit x9 *, and selection signal XS
* Is set to the same logic level as bit x9. Therefore, at the time of the redundant memory cell selective access corresponding to the case where the access address is the address to be relieved by the redundant memory cell, the data output buffer DOB2 or DOB on the opposite side from the case of the redundant memory cell non-selective access.
Operation 1 is selected.

The data output buffer DOB1 is activated and controlled by a select signal XS and a data output control signal DOC in response to an instruction to read data from the outside. Activation of data output buffer DOB2 is controlled by selection signal XS * and data output control signal DOC in response to an instruction to read data from the outside. Also, the data input buffers DIB1,
DIB2 includes a data input control signal activated in accordance with a write operation instructed from the outside and select signals XS and XS *.
Activation control is performed based on this. In the configuration described above, for example, if there is a defect in the memory cell MC (memory cell marked with a cross in FIG. 16) shown in the memory cell area MMN501 in the memory mat MM501 shown in FIG. Represents a redundant memory cell region MMR1 included in the memory mat MM101 on the opposite side.
01 redundant memory cells RMC (redundant memory cells blacked out in the figure) are allocated. for that purpose,
The redundant main word line MWLR11 shown in FIG.
The fuse (repair link) FUS1 included in the selection drive circuit MWRDRV for the fuse is cut off, and the fuse FUS1 included in the redundant program circuit RPGM1 shown in FIG.
Fuse (rescue link) FUS2 in the program units PGMU is cut in accordance with the address of the defective memory cell to be rescued, and fuse (rescue link) FUS3 is cut in advance.

Incidentally, also in the semiconductor memory device 1a ', the number of fuses (rescue links) FUS2 and FUS3 increases to, for example, about 5,000 or more with the increase in integration and density. ,as a result,
These fuses (links for rescue) FUS1, FUS
2 and the area for installing the FUS3 needs to be increased. However, as described above, by irradiating a picosecond laser beam with these fuses (rescue links) FUS1, FUS2, and FUS3 accurately aligned so as not to protrude from these fuses, The fuses (rescue links) FUS1, FUS2, and FU are not exposed to this laser beam to the lower layer.
Programming can be performed by cutting only S3. Therefore, the fuses (rescue links) FUS2 and FUS3 whose number increases are connected to the programming circuit RP.
By arranging them in the area (upper layer) of the direct peripheral circuit in the peripheral circuit PER close to the GM, as in the related art,
The fuses (links for relief) FUS1, FUS2,
In addition, the semiconductor memory device 1a 'can be downsized in a planar manner as compared with the case where the FUS3 is provided between the bonding pad BP and the peripheral circuit PER shown in FIG. The fuse (link for rescue) FUS2
And a predetermined number of the FUS3 may be provided between the bonding pad BP and the peripheral circuit PER as in the related art. Further, the fuse (link for rescue) F
As for US1, the area of the redundant main word line selection drive circuit MWRDRV (upper layer) or the area of the direct peripheral circuit in the vicinity (upper layer) or the area of the main word line address decoder and driver MWDEC / DRV (upper layer)
It becomes possible to install in.

Further, a fuse (link for rescue) FUS
2 and FUS3 may be provided on a memory array area close to the programming circuit RPGM. However, fuses (rescue links) FUS2 and FUS3
Is installed on the memory array area, the process of installing the fuses (repair links) FUS2 and FUS3 on the memory array area is required, and a uniform process can be performed over the entire memory array area. Since the memory characteristics may not be uniform and the memory characteristics may be non-uniform, if possible, fuses (rescue links) FUS2 and FU
It is desirable not to place S3 on the memory array area. The fuse (link for rescue) FU
Since S2 and FUS3 are cut off, it is preferable that fuses (rescue links) FUS2 and FUS3 are provided while excluding as much as possible the area (upper layer) of the sense amplifier SA and the write amplifier WR in the peripheral circuit.

In some cases, adjacent signal lines such as complementary bit lines BL51 and BL51 * may be short-circuited as defective memory cells. Therefore, simply switching to a redundant memory cell as it is may cause another memory to fail due to a short-circuit failure. It is not possible to improve the badness of the cell, the increase in power consumption, and the increase in the local temperature. Incidentally, one of the signal lines such as the complementary bit lines BL51 and BL51 * is connected to the switch circuit CSW51, and the other is a load circuit (L
(AOD), at a position near the load circuit or at a position near the load circuit, a mark 61 of a signal line such as a complementary data line connected to a defective memory cell or a memory cell adjacent to the defective memory cell. In the same manner as the fuses FUS2 and FUS3, a short circuit defect can be eliminated by irradiating a picosecond pulse laser beam to directly cut off the load circuit. In this way, it is possible to directly irradiate a picosecond pulsed laser beam to a signal line such as a complementary bit line and cut it,
The defect can be remedied or corrected with the minimum necessary number of bits.

[0052]

According to the present invention, the size of the semiconductor device can be reduced without increasing the proportion of the area where the rescue link for switching the defective memory cell to the redundant memory cell is occupied even if the integration is highly integrated. An effect that can be realized is achieved. Further, according to the present invention, when a short-circuit defect that is a cause of a defective memory cell has occurred, the short-circuit defect is eliminated by directly irradiating a minimum required signal line with a picosecond pulse laser beam. Thus, it is possible to prevent a loss due to a current flow or a local rise in temperature, thereby achieving a reliable bit relief. That is, it is possible to remedy or correct the short-circuit failure with the minimum necessary number of bits.

Further, according to the present invention, even if it is highly integrated, the semiconductor device such as a microcomputer can be miniaturized without increasing the ratio of the area where the programming element for adjusting the electrical characteristics is occupied. It has an effect that can be done. Further, according to the present invention, in the semiconductor memory device, there is an effect that a decoder provided for reducing the number of relief links can be eliminated, an area occupied by a redundant circuit can be reduced, and downsizing can be realized.

Further, according to the present invention, in a hybrid semiconductor device in which a logic and a memory are provided side by side on a substrate, there is an effect that downsizing can be realized by configuring the memory in a plurality of layers. Further, according to the present invention, in a hybrid semiconductor device having a logic and a memory juxtaposed on a substrate, an area in which a programming element for adjusting a logic characteristic and an area in which a rescue link is provided are replaced by a logic and a memory. It is not necessary to dispose outside the active region (the region where the active elements of the logic and the memory are installed). As a result, the electrical characteristics of the logic are optimized, the defective memory cells are relieved, and the size is reduced. It has the effect of being able to.

[Brief description of the drawings]

FIG. 1 is a diagram showing a schematic configuration of a processing apparatus using a picosecond pulse laser beam according to the present invention.

2A is a diagram illustrating an example of a desired rectangular pattern generated in the liquid crystal mask illustrated in FIG. 1 and projected on a semiconductor device, and FIG. 2B is an image captured from the semiconductor device 1; It is a figure showing an example of an optical image.

FIG. 3 is a diagram showing a first embodiment of a repair link provided corresponding to a normal memory cell;

FIG. 4 is a diagram showing a second embodiment of a repair link provided corresponding to a normal memory cell.

FIG. 5 is a diagram showing a third embodiment of a repair link provided corresponding to a normal memory cell;

FIG. 6 is a cross-sectional view showing an embodiment in which a region provided with a rescue link is provided on a region where an active element (active region) made of a memory element is formed in the semiconductor memory device according to the present invention; It is.

FIG. 7 shows an embodiment in which, in a semiconductor memory device according to the present invention in which a memory area and a peripheral circuit area and a common decoder area are formed, an area provided with a rescue link is arranged on the memory area; It is a top view.

FIG. 8 is a diagram showing a circuit configuration in a semiconductor memory device having a rescue link.

FIG. 9 is a diagram showing a circuit configuration in a semiconductor memory device having no rescue link.

FIG. 10 illustrates an embodiment in which wiring such as a rescue link or a data line of a semiconductor device according to the present invention is irradiated with picosecond pulsed laser light to be cut and the like, and then protected by applying a final passivation film. It is sectional drawing which shows a form.

FIG. 11 is a plan view showing an embodiment of a hybrid semiconductor device having both a logic circuit including a microcomputer and a memory circuit according to the present invention.

FIG. 12 is a partial side sectional view of FIG. 11;

FIG. 13 is a diagram showing a schematic circuit in a semiconductor memory device according to the present invention.

FIG. 14 is a plan view of a chip showing one embodiment of a semiconductor memory device according to the present invention.

FIG. 15 is a schematic block diagram focusing on the connection relation of the circuit blocks shown in the chip plan view shown in FIG. 14;

16 is a diagram showing the memory mat shown in FIG. 14 and a detailed circuit in the vicinity of the memory mat.

FIG. 17 is a diagram for explaining an example of a redundant main word line selection system and a redundant sub word line selection system shown in FIG. 16;

18 is a circuit diagram showing a partial example of the redundant program circuit shown in FIG.

FIG. 19 is a diagram illustrating an example of a switching control circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 1a ... Semiconductor memory device, 1b ...
Hybrid semiconductor device, 2: laser light source, 4: liquid crystal mask, 6: projection processing lens, 23: picosecond pulsed laser light, 19: CAD system, 20: tester,
31, 32, 34, 35 ... wiring, 33, 36, 37 ...
Rescue links, 49: areas provided with rescue links, 49a, 49b: areas formed with wiring such as rescue links, 51, 52, 53: active elements, 61: memory area, 62: peripheral circuit area 81, a normal memory cell, 82, a redundant memory cell, 83, a switch circuit,
84 ... rescue link, 85 ... common decoder, 86
... word line, 87 ... common line, 88 ... data line, 8
9: complementary data line (complementary bit line), 101: wiring,
110: substrate, 111: logic circuit, 112:
Wiring layer, 113: programming element, 121: memory circuit, 122, 124: wiring layer, 123: plate member BP: bonding pad, MA1 to MA8: memory array, MAN1 to MAN8: memory array area,
MAR1 to MAR8 ... redundant memory array area, M
C: Memory cell, RMC: Redundant memory cell, MWD
EC / DRV: Main word line address decoder and driver, MWRDRV: Redundant main word line drive circuit, SA: Sense amplifier, FUS: Fuse (rescue link), RPGM: Redundant program circuit, PER
… Peripheral circuit

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Akira Shimase 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Yokohama, Japan Inside the Manufacturing Research Laboratory, Hitachi, Ltd. No. 1 in the Semiconductor Division, Hitachi, Ltd. (72) Inventor Shuji Ikeda 5--20-1, Kamisui Honcho, Kodaira-shi, Tokyo (72) In-house in Semiconductor Division, Hitachi, Ltd. 5-2-1, Honmachi Semiconductor Division, Hitachi, Ltd.

Claims (13)

[Claims] 1. A semiconductor device according to claim 1, wherein a rescue link for switching a defective circuit to a redundant circuit is provided on a region having an active element. 2. In a semiconductor memory device having a redundant memory cell and a memory cell, a repair link for switching a desired bit in a defective memory cell to the redundant memory cell is provided on an active region of a memory including a peripheral circuit. A semiconductor device characterized by the above-mentioned. 3. A semiconductor memory device having a redundant memory cell and a memory cell, wherein a relief link for switching a desired bit in a defective memory cell to the redundant memory cell is provided on a peripheral circuit of the memory. Semiconductor device. 4. A semiconductor memory device having a redundant memory cell and a memory cell, wherein a defective memory cell is separated by directly cutting a signal line of the defective memory cell. 5. A semiconductor memory device having a redundant memory cell and a memory cell, wherein a signal line of a defective memory cell is directly cut and a protective film is coated thereon. 6. A memory and a logic are juxtaposed on a substrate, and a link for memory rescue is provided on an active area of the memory.
A hybrid semiconductor device, wherein a programming element for adjusting a logic characteristic is provided on an active region of the logic. 7. A hybrid semiconductor device, wherein a logic and a memory are arranged side by side on a substrate, and the memory is constituted by a plurality of layers. 8. A semiconductor device, wherein a rescue link for switching a defective circuit to a redundant circuit is provided on a region having an active element, and 1 ns is provided for the desired rescue link.
A method for manufacturing a semiconductor device, wherein a defective circuit is switched to a redundant circuit by performing processing by aligning and irradiating a laser beam having the following pulse width. 9. In a semiconductor memory device having a redundant memory cell and a memory cell, a rescue link for switching a desired bit in a defective memory cell to the redundant memory cell is provided on an active region of a memory including a peripheral circuit. A semiconductor device for switching a desired bit in a defective memory cell to a redundant memory cell by performing processing by aligning and irradiating a laser beam having a pulse width of 1 ns or less on the desired rescue link. Manufacturing method. 10. In a semiconductor memory device having a redundant memory cell and a memory cell, a relief link for switching a desired bit in a defective memory cell to a redundant memory cell is provided on a peripheral circuit of the memory. A method of manufacturing a semiconductor device, characterized in that a laser beam having a pulse width of 1 ns or less is aligned and radiated to a rescue link to perform processing, thereby switching a desired bit in a defective memory cell to a redundant memory cell. 11. A semiconductor memory device having a redundant memory cell and a memory cell, wherein a defective memory cell is directly irradiated with a laser beam having a pulse width of 1 ns or less by aligning and irradiating the signal line to cut the defective memory cell. A method for manufacturing a semiconductor device, comprising separating cells. 12. In a semiconductor memory device having a redundant memory cell and a memory cell, a defective memory cell is irradiated with a laser beam having a pulse width of 1 ns or less directly to a signal line of the defective memory cell, and cut by irradiating the signal line. A method for manufacturing a semiconductor device, comprising separating a cell and covering the cell with a protective film. 13. In a semiconductor device, a programming element for adjusting electric characteristics is provided on an active area of a circuit, and a desired programming element is irradiated with a laser beam having a pulse width of 1 ns or less in a matched manner. A method for manufacturing a semiconductor device, comprising: adjusting characteristic characteristics.