JPH10340837A - Forming method of mask pattern data and manufacture of solid state element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To exclude misdetection of a mark pattern position or the like, by arranging a mask pattern such that a stuck film pattern is formed in a region containing a mark pattern formed on a substrate. SOLUTION: A silicon nitride film pattern 17 is formed as a polish stopper film in a substrate surface flattening process using a CMP(chemical mechanical polishing) method. The substrate surface is flattened by polishing a silicon oxide film 14. The polishing speed of the silicon nitride film pattern 17 and a silicon nitride film 11 is slower about three times than that of the silicon oxide film 14. A mask pattern 16 which is used for forming the silicon nitride film pattern 17, an etching stopper film, may be corrected such that both the pattern edge do not approach. For example, the mask pattern for working a polish stopper film is corrected such that the whole mark pattern is covered and the pattern edge is not arranged in the vicinity of edge of the mark pattern. The vicinity of edge is a region containing a detection region at the time of mark pattern detection.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mask pattern data creating method and a mask for use in manufacturing various solid-state devices such as semiconductor devices, superconductor devices, magnetic devices, optical integrated circuit devices, and the like. .

[0002]

2. Description of the Related Art Heretofore, a reduction projection exposure method, which is one of optical lithography methods, has been mainly used for forming an extremely fine pattern in a solid-state device such as a large-scale semiconductor integrated circuit. In this method, a mask pattern formed on a mask or a reticle (hereinafter, collectively referred to as a mask) is reduced and transferred onto a substrate using an imaging optical system.

In order to manufacture a solid-state device such as a semiconductor, it is necessary to form a plurality of patterns with high accuracy. When the mask pattern is positioned with respect to the pattern on the substrate and the pattern is superimposed and transferred, the position of the mark pattern formed on the substrate is detected, and the mask pattern transfer position is determined based on the detection result and the pattern is superposed and transferred. As a method of detecting a mark pattern position, a method of detecting a pattern formed on a substrate using detection light such as a laser beam and detecting a mark pattern edge position from an obtained detection signal, a two-dimensional detection of a mark pattern There is a method of comparing an image with a reference pattern position of a detection system.

[0004]

SUMMARY OF THE INVENTION Chemical mechanical polishing technology (CMP
A technique is used in which the substrate surface is flattened by polishing the substrate surface using the above-described technique. Here, there is a possibility that a pattern or a pattern edge that causes a mark pattern detection position error may be formed near the mark pattern depending on a processing process or a base pattern shape. For this reason, erroneous detection of the mark pattern position or the like occurs, and as a result, there is a problem that the overlay accuracy is deteriorated.

[0005]

SUMMARY OF THE INVENTION The above-mentioned problem is related to mask pattern data which is positioned with respect to a pattern formed on a substrate and is superimposed and transferred. The mask pattern data is laminated on the substrate using a chemical mechanical polishing method. The mask pattern data of the resist pattern transfer mask used when processing the adhered film having a lower polishing rate than the polished film, which is applied on the polished film as a polishing stopper film when polishing the polished film. The problem is solved by a method of creating mask pattern data, which is used for positioning and arranges mask patterns so that a deposition film pattern is formed in a region including a mark pattern formed on a substrate.

[0006] Alternatively, the above problem is mask pattern data which is positioned and transferred with respect to a pattern formed on the substrate, and the film to be polished laminated on the substrate by using a chemical mechanical polishing method. In the method of creating mask pattern data of a register pattern transfer mask used when processing an adhered film having a lower polishing rate than the film to be polished, which is applied on the film to be polished as a polishing stopper film when polishing, This problem can be solved by a method of creating mask pattern data, which is used when arranging mask patterns so that a deposition film pattern is not formed in a region including a mark pattern formed on a substrate.

Further, the above problem is related to mask pattern data which is positioned and transferred with respect to a pattern formed on a substrate, and a film to be polished laminated on the substrate by using a chemical mechanical polishing method. In the method of creating mask pattern data of a resist pattern transfer mask used when processing an adhered film having a lower polishing rate than the film to be polished, which is adhered on the film to be polished as a polishing stopper film during polishing. The problem is solved by a method of creating mask pattern data in which the mask pattern is arranged so that the pattern edge position of the deposition pattern is located outside a detection area for detecting a mark pattern formed on the substrate.

Further, the above problem is caused by an exposure mask manufactured using the mask pattern data created by the mask pattern data creation method, and a pattern formation method of transferring a mask pattern onto a substrate using the mask. Further, the problem is solved by a solid-state element manufactured by using the pattern forming method.

Further, the above problem is caused by a step of laminating a film to be polished on a substrate by using a chemical mechanical polishing method, and polishing a film to be polished more than a film to be polished used as a polishing stopper film when polishing the film to be polished. A step of laminating a deposition film having a low speed on the film to be polished, which is used when performing overlay exposure by positioning with respect to a pattern formed on the substrate,
Processing the deposition film so that a deposition film pattern composed of the deposition film is formed on a region including a mark pattern formed on a substrate; polishing the polishing target film; A method for manufacturing a solid-state device comprising a step of removing a film, a step of further laminating a film to be polished on a substrate by using a chemical mechanical polishing method, a polishing stopper film when polishing the film to be polished A step of laminating a film to be polished having a lower polishing rate than the film to be polished on the film to be polished, forming the film on the substrate, which is used when positioning and patterning the pattern formed on the substrate and performing overlapping exposure Processing the deposited film so that the deposited film pattern made of the deposited film is not formed on the region including the marked pattern, polishing the film to be polished, and removing the deposited film. Solid consisting of In the method for manufacturing a solid-state element, further, in the method for manufacturing a solid-state element, a pattern edge position of the deposition film pattern is disposed outside a detection area when detecting a mark pattern formed on the substrate. Further, in the method for manufacturing a solid-state device, the problem is solved by a method for manufacturing a solid-state device in which a pattern formed on the substrate is an element separation pattern.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention has a minimum design dimension of 250 nm.
The manufacturing process of the large-scale semiconductor integrated circuit device will be described in detail using examples.

In this embodiment, the numerical aperture (NA) of the projection optical system is 0.6 for transferring a circuit pattern using the minimum design size.
A KrF reduction projection exposure apparatus having a reduction ratio of 5: 1 was used.

An example of the configuration of an exposure apparatus for exposing a mask pattern on a substrate will be described with reference to FIG. The light emitted from the light source 31 includes a fly-eye lens 32, an illumination aperture 30,
The mask 36 is illuminated via the condenser lenses 33 and 35 and the mirror 34. Among the exposure optical conditions, coherency was adjusted by changing the size of the opening of the illumination system aperture 30. Further, in the modified illumination exposure method for improving the resolution characteristics by optimizing the shape of the illumination light source, the shape and size of the opening of the aperture 30 are changed under predetermined conditions.

A pellicle 37 is provided on the mask 36 to prevent pattern transfer failure due to foreign matter adhesion. The mask pattern drawn on the mask 36 is projected via a projection lens 38 onto a wafer 39 as a sample substrate. The mask 36 is placed on a mask stage 48 controlled by a mask position control means 47, and the center of the mask 36 and the optical axis of the projection lens 38 are accurately aligned.

The wafer 9 is vacuum-adsorbed on a sample stage 40. The sample stage 40 is mounted on a Z stage 41 movable in the optical axis direction of the projection lens 38, that is, in the Z direction.
Further, it is mounted on an XY stage 42. The Z stage 41 and the XY stage 42 are driven by the respective driving units 13 and 14 according to a control command from the main control system 49, and can be moved to a desired exposure position. The position is accurately monitored by the laser length measuring device 45 as the position of the mirror 46 fixed to the Z stage 41.
In addition, the surface position of the wafer 39 is measured by a focus position detecting means included in a normal exposure apparatus. Z according to the measurement result
By driving the stage 41, the surface of the wafer 39 can always be made to coincide with the image plane of the projection lens.

An alignment optical system 55 provided adjacent to the projection lens 38 is used for detecting a mark pattern position on the substrate when a mask pattern is superimposed on a pattern on the substrate and exposed. The method of performing the overlay exposure using the alignment optical system 55 different from the projection lens 38 for transferring the mask pattern in this way is called an off-axis alignment method. On the other hand, a method of detecting and aligning a mark pattern on a substrate through a projection lens system is called a TTL alignment method.

FIG. 1 is a schematic cross-sectional view for explaining a manufacturing process of the semiconductor integrated circuit device manufactured in this embodiment. A silicon oxide film 11 and a silicon nitride film 12 were sequentially stacked on a P-type silicon substrate 10, and an element isolation pattern was transferred thereon to form a resist pattern 13 (a, b). The silicon nitride film 12 and the silicon oxide film 11 were etched using the resist pattern 13 as a mask, and the silicon substrate 10 was further etched to a depth of 300 nm (c). After removing the resist pattern 13 and the silicon nitride film 12 (d), C
The silicon oxide film 14 was laminated so as to fill the etched portion of the silicon substrate by using the VD method (e). next,
The silicon nitride film 15 was laminated again (f), and the silicon nitride film 15 was etched using the resist pattern 16 (g) as a mask to form a silicon nitride film pattern 17 (h). The silicon nitride film pattern 17 is provided as a polishing stopper film in a subsequent substrate surface flattening step using a CMP (chemical mechanical polishing) method.

Next, the silicon oxide film 14 was polished under predetermined conditions using a CMP apparatus to perform a step of planarizing the substrate surface (i). At this time, the polishing rate of the silicon nitride film pattern 17 and the silicon nitride film 11 was about three times slower than that of the silicon oxide film 14. After polishing the silicon oxide film,
After the MP process, a cleaning process is performed.
Then, the silicon nitride film pattern 17 was removed (j).

Here, the mask pattern used for transferring the resist pattern 16 for forming the silicon nitride film pattern 17 is based on the mask pattern used for transferring the resist pattern 13 for element isolation pattern processing. Created.
For example, a case will be described in which the element isolation pattern is transferred using a negative resist by a normal transmission mask and an annular illumination method which is one of the modified illumination exposure methods.

Similarly, when a negative resist is used for polishing stopper film processing, a mask pattern for polishing stopper film processing can be formed from a mask pattern for element isolation pattern processing. When the same type (negative or positive) resist material is used for the transfer of the element separation pattern and the polishing stopper film processing pattern, the mask pattern for the element separation pattern transfer is processed by black and white reversal (negative / positive reversal). be able to.

FIG. 2 shows a prior art. A semiconductor integrated circuit device in which a mask pattern for processing a polishing stopper film prepared by inverting a mask pattern for transferring an element separation pattern into a black-and-white image is used. FIG. 4 is a schematic cross-sectional view illustrating a manufacturing process. After laminating the silicon nitride film 15 as a polishing stopper film by a predetermined process, a register pattern 16 for processing the polishing stopper film is formed (FIG. 2A). The silicon nitride film is processed using the register pattern 16 as a mask (FIG. 2B), and after flattening the substrate surface using a CMP method (FIG. 2C), the silicon nitride film 15 is removed (FIG. d)).

When the mask pattern for the mark stopper is simply inverted between black and white when creating the mask pattern for processing the polishing stopper film, the register pattern for processing the polishing stopper film and the element isolation pattern formed on the substrate are overlapped. When an alignment error occurs as shown in FIG.
As shown in (1), the cross-sectional shape of the mark pattern after polishing becomes asymmetric.

FIG. 4A is a diagram schematically showing an enlarged mark pattern portion. As shown in this figure, the pattern edge of the polishing stopper film is shifted and transferred near the edge position of the mark pattern formed at the time of the element isolation pattern processing.

For this reason, erroneous detection or error may occur when detecting the mark pattern position.

When the silicon oxide film at the mark pattern portion is polished, the sectional shape of the silicon oxide film at the pattern edge portion is changed or smoothed, and the mark pattern may not be detected. In FIG. 4A, the mark pattern is arranged between AB. When both pattern edges are close to each other, a mark pattern detection signal obtained by irradiating the detection light between A and B is, for example, as shown in FIG.
The result is as shown in FIG. When the detection signal is the detection light level I
When the mark pattern edge position is obtained based on the position crossing th, the mark pattern edge position on the left side is C, which is the middle point of ab, and the right side, is the middle point position D of cd. In this example, the position D is different from the pattern edge position Q of the mark pattern formed at the time of the element isolation pattern processing.

In order to prevent this, the mask pattern used to form the silicon nitride film pattern serving as the etching stopper film may be corrected so that both pattern edges do not come close to each other. For example, a mask pattern for polishing stopper film processing is corrected so as to cover the entire mark pattern and not to dispose a pattern edge near the edge of the mark pattern. Here, the vicinity of the edge is an area including a detection area when the mark pattern is detected. Further, it is preferable that the mark pattern is sufficiently distant from the mark pattern edge position to prevent erroneous detection of the mark pattern position due to a local change in the film thickness of the laminated film or the resist film to be laminated in the subsequent steps. Since the cross section of the element at this time is as schematically shown in FIG. 4B, the detection signal between A 'and B' is as shown in FIG. 5B. The mark pattern edge positions obtained from this detection signal are C 'and D', which are the midpoint positions of a'-b 'and c'-d', respectively, and both coincide with the mark pattern edge positions P and Q.

The polishing stopper film pattern may not be formed on the mark pattern. In this case, the cross section of the substrate is schematically shown in FIG.
As in the case shown in (b), the mark pattern position can be accurately detected.

FIG. 6 is a diagram showing a pattern arrangement. A polishing stopper film pattern 62 is formed on a mark pattern 61 formed on the substrate. Areas used for detecting the mark pattern position are indicated by 60-1 and 60-2. Conventionally, the edge position of the polishing stopper film pattern is arranged near the mark pattern edge position as shown in FIG. 6A or FIG. 6B, so that the erroneous detection of the mark pattern position as described above is performed. May occur. On the other hand, FIG.
By arranging the polishing stopper film pattern so as to cover the entire mark pattern as shown in (1), erroneous detection of the mark pattern position can be prevented. Alternatively, as shown in FIG. 6D, it is sufficient that the polishing stopper film pattern 62 is an area including the areas 60-1 and 60-2 used for detecting the mark pattern.

In a normal solid-state device manufacturing process, when a mask pattern is superimposed and transferred on a pattern on a substrate, it is checked whether or not the superposition error between the two is within a standard determined in the process. Inspection patterns used in the inspection at this time may have the same problem as the mark pattern described above. Therefore, for example, as shown in FIG. 10A, if the pattern 65 for polishing stopper film processing is arranged so as to sufficiently cover the pattern 66 for overlay error measurement so that no measurement error occurs at the time of overlay error measurement. Good. As a result, it is possible to suppress the occurrence of a measurement error as in the detection of the mark pattern.

FIG. 8 is a schematic sectional view showing a part of a semiconductor integrated circuit device manufactured in this embodiment. The figure shows a cross section in the step of laminating the insulating film after the formation of the storage electrode.

A P-type Si semiconductor 101 is used as a substrate. A buried element isolation region 102 is formed on the surface by using a known element isolation technique. Next, for example, a thickness of 150 nm
The word line 105 having a structure in which the polycrystalline silicon and the silicon oxide having a thickness of 200 nm are stacked is formed. Through a normal process, a data line 108 made of polycrystalline silicon, high-melting-point metal silicide, or a stacked film of these is formed.

Further, the storage electrode 1 made of polycrystalline silicon
14 is formed. After that, tantalum pentoxide, silicon nitride, silicon oxide, a ferroelectric, a composite film of these, or the like is deposited, and a capacitor insulating film 115 is formed.
Subsequently, a low-resistance conductor such as polycrystalline silicon, a high-melting-point metal, a high-melting-point metal silicide, or Al or Cu is applied to form a plate electrode 116. Further, a semiconductor integrated circuit device was manufactured through a process of forming and processing an interlayer insulating film, a wiring, a passivation film, and the like through a normal process. Although only typical manufacturing steps have been described here, the normal element manufacturing steps are used for other steps.

Next, a pattern formed in a lithography process for manufacturing the above-described semiconductor integrated circuit device will be described. FIG. 9 shows a pattern arrangement of a memory portion of a typical pattern constituting a manufactured semiconductor integrated circuit device. Patterns of word lines 122, data lines 124, active areas 121, storage electrodes 126, and electrode extraction holes 125 are arranged. In this embodiment, the word line 122 and the data line 1
24, a spatial frequency modulation type (so-called Levenson type) phase shift mask in which phase shifter patterns are arranged every other periodic mask pattern for pattern transfer of the storage electrode 126 is used.

In each lithography process, after transferring the mask pattern onto the resist film on the substrate, the overlay error between the circuit pattern on the substrate and the resist pattern formed by the transfer is measured by an automatic overlay accuracy measuring device and a scanning type. When measured using an electron microscope, the overlay error was less than the desired tolerance ± 70 nm, and the overlay error in the transfer pattern area could be kept within the desired overlay error range.

FIG. 10B shows a pattern used when an overlay error is measured by an automatic overlay accuracy measuring device. The overlay error between the two patterns was measured from the relative displacement between the overlay error measurement pattern 66 formed on the substrate and the pattern 67 that was positioned and transferred to the pattern on the substrate.

By manufacturing a large-scale integrated circuit device as described above, a desired pattern can be transferred with a desired overlay accuracy with high accuracy. As a result, it is possible to suppress a decrease in yield caused by misalignment and an increase in cost due to an increase in required time in the reproduction processing step.

In this embodiment, the manufacturing process of a large-scale semiconductor integrated circuit device has been described by way of example. However, the method described in this embodiment may be applied to the manufacture of various other solid-state devices. Is also possible.

By manufacturing a large-scale integrated circuit device as described above, a desired pattern can be transferred with a desired overlay accuracy with high accuracy. As a result, it is possible to suppress a decrease in yield caused by misalignment and an increase in cost due to an increase in required time in the reproduction processing step.

In this embodiment, the manufacturing process of a large-scale semiconductor integrated circuit device has been described as an example. However, the method described in this embodiment may be applied to the manufacture of various other solid-state devices. Is also possible.

[0039]

As described above, according to the present invention, it is possible to suppress the deterioration of the overlay accuracy and to manufacture the solid-state device with a high yield.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view showing a manufacturing process of a solid-state device according to the present invention.

FIG. 2 is a schematic cross-sectional view showing a conventional solid-state element manufacturing process.

FIG. 3 is a cross-sectional view of a solid-state element in a manufacturing process of the solid-state element using the present invention.

FIG. 4 is a schematic diagram illustrating a cross-section of a solid-state element in a manufacturing process of the solid-state element using the present invention in comparison with a conventional one.

FIG. 5 is an explanatory diagram illustrating the operation of the present invention in comparison with a conventional method.

FIG. 6 is a plan view showing a pattern arrangement for explaining an embodiment of the present invention in comparison with a conventional method.

FIG. 7 is a schematic diagram illustrating a configuration example of an exposure apparatus.

FIG. 8 is a schematic view showing a part of a cross section of a semiconductor device manufactured by using the present invention.

FIG. 9 is a schematic view showing an example of a mask pattern of a mask used in manufacturing a semiconductor device.

FIG. 10 is a schematic view showing an example of a mask pattern of a mask used in manufacturing a semiconductor device.

[Explanation of symbols]

11 mask substrate, 12 light shielding film, 13 phase shifter film, 14 light shielding film, 15 light shielding film, 16 etching stopper film, 30 illumination system diaphragm, 31 light source, 32 fly-eye lens, 33 Condenser lens, 34 mirror, 35 condenser lens, 36 mask, 37 pellicle, 38 projection lens, 39 wafer, 40, 40
-1, 40-2: sample stage, 41: Z stage, 42: X
Y stage, 43 ... driving means, 44 ... driving means, 45 ...
Laser length measuring device, 46 mirror, 47 mask position control means, 48 mask stage, 49 main control system, 50 storage device, 51 laser length measuring device, 52 mirror, 53 sample holder changing device, 55: network device, 56: substrate cassette table, 57-1, 57-2: substrate transport system, 60-
1, 60-2: detection area, 61: mark pattern, 62,
63, 64: polishing stopper film pattern, 65: pattern for polishing stopper film processing, 66: pattern for overlay error measurement, 101: Si semiconductor substrate, 102: element isolation region, 105: word line, 108: data line 114, storage electrode, 115, capacitor insulating film, 116, plate electrode, 121, element isolation pattern, 122, word line pattern, 123, contact pattern, 124, data line pattern, 125, electrode extraction hole pattern, 126, Storage electrode pattern.

Claims (11)

[Claims] The present invention relates to mask pattern data which is positioned and transferred with respect to a pattern formed on a substrate, and is used when polishing a film to be polished laminated on the substrate using a chemical mechanical polishing method. In the method of creating mask pattern data of a resist pattern transfer mask used when processing an adherend film having a lower polishing rate than the polished film, which is adhered on the polished film as a polishing stopper film, A method of generating mask pattern data, comprising: arranging a mask pattern so that a deposition film pattern is formed in a region including a mark pattern formed on a substrate. 2. A mask pattern data which is positioned and superimposed and transferred with respect to a pattern formed on a substrate, and is used when polishing a film to be polished laminated on a substrate by using a chemical mechanical polishing method. In the method of creating mask pattern data of a resist pattern transfer mask used when processing an adherend film having a lower polishing rate than the polished film, which is adhered on the polished film as a polishing stopper film, A method of generating mask pattern data, comprising: arranging a mask pattern so that a deposition film pattern is not formed in a region including a mark pattern formed on a substrate. 3. The mask pattern data creating method according to claim 1, wherein the pattern edge position of the deposition film pattern is located outside a detection area for detecting a mark pattern formed on the substrate. A mask pattern data creating method, wherein the mask pattern is arranged so as to be performed. 4. The method for creating mask pattern data according to claim 1, wherein the pattern formed on the substrate is an element isolation pattern. Method. 5. An exposure mask manufactured by using the mask pattern data created by the method for creating mask pattern data according to claim 4. 6. A pattern forming method, wherein a mask pattern is transferred onto a substrate using the mask according to claim 5. 7. A solid state device manufactured by using the pattern forming method according to claim 6. 8. A step of laminating a film to be polished on a substrate by using a chemical mechanical polishing method, wherein a polishing rate is lower than a film to be polished used as a polishing stopper film when polishing the film to be polished. A step of laminating a film to be deposited on the film to be polished, and positioning the pattern with respect to a pattern formed on the substrate and performing overlay exposure on an area including a mark pattern formed on the substrate. Processing the deposited film so that a deposited film pattern composed of a deposited film is formed;
A method of manufacturing a solid-state device, comprising a step of polishing the film to be polished and a step of removing the film to be deposited. 9. A step of laminating a film to be polished on a substrate using a chemical mechanical polishing method, wherein the polishing rate is lower than a film to be polished used as a polishing stopper film when polishing the film to be polished. A step of laminating a film to be deposited on the film to be polished, and positioning the pattern with respect to a pattern formed on the substrate and performing overlay exposure on an area including a mark pattern formed on the substrate. A step of processing the deposited film so that a deposited film pattern composed of a deposited film is not formed, a step of polishing the film to be polished, and a step of removing the deposited film, Production method. 10. A method for manufacturing a solid-state device according to claim 8, wherein a pattern edge position of said deposition film pattern is arranged outside a detection area for detecting a mark pattern formed on said substrate. A method for manufacturing a solid-state device. 11. The method for manufacturing a solid state device according to claim 8, wherein the pattern formed on said substrate is an element separation pattern.
A method for manufacturing a solid state device.