JPH10340584A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To expand the data holding part of a memory cell without damaging the stability and also to make the sense unnecessary in a semiconductor memory device. SOLUTION: A memory cell is provided with one digit line DR for read operation. In the initial stage of the read operation, one shot pulse is added to a MOS transistor M11 so as to be in an on-state for a short time by a pulse generating circuit PG and as the result, the digit line DR is picked up to a power source potential Vcc. The pulling down of the digit line DR to the grounding potential is performed by MOS transistors M5, M6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to an SRAM constituted by CMOS and BiCMOS.

[0002]

2. Description of the Related Art As shown in FIG. 10, a conventional semiconductor memory device has a data storage portion composed of MOS transistors M1, M2, M3 and M4, and MOS transistors M7 and M9 for controlling data input / output. A word line WL for controlling ON / OFF of the MOS transistors M7 and M9;
Digit lines D and DB for transmitting data, and MOS transistors M15 and M16 serving as loads when reading data
And a sense amplifier SA for amplifying the potential difference between the digit lines D and DB at the time of reading, and a write circuit WC for driving the digit lines D and DB at the time of writing.

Next, the operation of the conventional example will be described.
In the read state, the word line WL becomes high potential,
The S transistors M7 and M9 are turned on. The read current I ₁ (when the MOS transistor M2 is on) or I ₂ (when the MOS transistor M4 is on) flows through one of the digit lines D and DB according to the information of the memory cell, and the load MOS transistors M14 and M15 By
The digit line where the current is flowing is set at 0.
The other digit line through which no current flows at a potential lower by about 1 V has the same potential as Vcc, and the potential difference is amplified by the sense amplifier SA.

In a write operation, when the word line WL is at a high potential, digit lines D and DB are written by a write circuit WC.
Is set to the ground potential and the other to Vcc, and data is written to the memory cell through the MOS transistors M7 and M9.

[0005]

The above-described conventional semiconductor memory device has the following problems.

The first problem is that in the read operation,
DC current is consumed by the memory cell and the sense amplifier. The reason is that in the read operation, the MOS transistor M3 holding data in the memory cell,
This is because a current flows through M4 and the potential difference between digit lines D and DB is small, so that a sense amplifier for potential amplification is required.

The second problem is that since a current flows through the MOS transistors M3 and M4 which hold data in the memory cells, a very large read current cannot be obtained, and the digit lines D and DB are not connected. In order to increase the response speed, the impedance of the MOS transistors M14 and M15 is reduced, so that the potential difference between the digit lines D and DB is only 0.1 V. The reason is that if an excessively large current flows through the data holding portion in the memory cell, the current causes a potential change in the data holding portion,
This is because the stability of data retention is reduced.

An object of the present invention is to realize an increase in read current without deteriorating the stability of data retention in a memory cell, to increase the amplitude of a digit line potential at the time of read, and to provide a circuit configuration that does not require a sense amplifier. Another object of the present invention is to provide a semiconductor memory device.

[0009]

According to the present invention, there is provided a semiconductor memory device comprising: one read digit line; a MOS transistor for raising the digit line to a power supply potential; and a memory cell without deteriorating data stability. It has a MOS transistor that pulls down the digit line to the ground potential.

Since the gate of the MOS transistor for passing the read current of the memory cell is connected to the MOS transistor of the data holding portion, the read current does not flow to the holding portion. Therefore, the read current can be increased without considering the stability of the memory cell. Since a large current can flow through the read operation digit line, the read operation digit line can be pulled down in a short time. However, since the memory cell itself does not have the function of raising the digit line for read operation, raising the digit line for read operation must be performed by the MO for controlling the digit line.
This is performed by an S transistor.

As a result, the load MOS transistor for improving the response speed of the digit line as in the conventional example is not required, and the DC current flowing through the memory cell during the read operation can be reduced. Also, the DC consumed by the sense amplifier
The current is also reduced.

According to an embodiment of the present invention, the digit line has one digit line for a read operation and two digit lines for a write operation. A current path through which a read current can flow through the digit line for use.

According to an embodiment of the present invention, the word line comprises:
It has two systems for read operation and write operation, and one of the two digit lines for write operation is shared with the digit line for read operation.

According to an embodiment of the present invention, the word line comprises:
There are two systems for read operation and write operation, and the digit line has one for read operation and one for write operation.

According to the embodiment of the present invention, the digit line for the write operation is shared with the digit line for the read operation.

[0016]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram of a semiconductor memory device according to a first embodiment of the present invention. MOS transistors M1 to M
4 forms a latch circuit for holding data. MO
The S transistors M5 and M6 serve to pass a read current in a read operation. MOS transistors M7-
M10 is the MOS transistor M1 in the write operation.
The inversion operation of the latch circuit formed by .about.M4 is performed. WL
Is a word line for controlling on / off of the MOS transistors M5, M7, M9, DR is a digit line for read operation, and DW and DWB are digit lines for write operation. MOS transistor M11 serves to pull up digit line DR at the beginning of the read operation. MO
The S transistor M11 is driven by a circuit PG that generates a one-shot pulse based on a clock signal. In the data output section, MOS transistors M12, M1
3 latches when the digit line DR is at a high potential to prevent the digit line DR from floating. Y
Is a digit line selection signal, which stops the operation of the MOS transistor M11 when it is not selected and, at the same time, serves to fix the digit line DR to a low potential by the MOS transistor M14.

As a modification of the second embodiment of the present invention, as shown in FIG. 2, the data inverting circuit of the memory cell may be configured as M7 and M9. in this case,
MOS constituting a memory cell as compared with the embodiment of FIG.
Although the number of transistors can be reduced, a current flows through the data holding unit, so that a design that pays attention to stability is required.

Next, the operation of this embodiment will be described with reference to FIGS.
This will be described in detail with reference to FIG.

First, it is assumed that the word line WL and the selection signal Y become high potential, and the memory cell and the digit line DR are in the selected state. Next, at the beginning of the read operation, the short-time MOS transistor M
A one-shot pulse is applied so that 11 is turned on, and digit line DR is pulled up to power supply potential Vcc. Thereafter, when the data of the memory cell stores the state where the read current becomes 0 (the MOS transistor M6 is turned off), the potential of the digit line DR is maintained at a high potential as shown by a solid line in FIG. Become. At this time DOB,
Since YB is at a low potential, the MOS transistor M
12 and 13 are turned on, and the digit line DR is kept at a high potential. Conversely, when the data in the memory cell stores a state in which a read current flows (the MOS transistor M6 is on), the potential of the digit line DR changes from a high potential to a low potential as shown by a dotted line in FIG. To be reduced to At this time, until the data output DOB is inverted from the low potential to the high potential, the MOS transistors M12, M13
Is turned on, it acts to pull up digit line DR. However, MOS transistors M12, M
If the element size of the element 13 is reduced, the reduction by the memory cell is not hindered.

Next, the write operation will be described. The write operation is the same as the conventional example. When the word line WL is at a high potential and the memory cell is in a selected state, the digit line DW is at a high potential,
When the digit line DWB is at a low potential, the MOS transistors M9 and M10 are turned on in the embodiment of FIG.
The potential of B is lowered. In the embodiment of FIG. 2, since DWB is at a low potential, the node QB is pulled down through the ON-state MOS transistor M9. Digit line DW is low potential,
When the digit line DWB is at a high potential, the MOS transistors M7 and M8 are turned on in the embodiment of FIG. 1 to lower the potential of the digit line Q. In the embodiment of FIG. 2, since the digit line DW has a low potential, the node Q is pulled down through the ON-state MOS transistor M7.

[0022]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 4 is an example corresponding to the embodiment of FIG. The numerical values added to the MOS transistors M1 to M14 represent the channel width in μm. Each of the transistors M1 to M14 has a channel length of 0.5 μm. Since the write operation is not different from the conventional one, the explanation will be focused on the read operation. A feature of the present invention is that the channel width of the data read transistors M5 and M6 is four times as large as that of the MOS transistor M4 in the data storage portion. In the conventional circuit, the channel width of the read transistor needs to be reduced to 1/3 to 1/4 of the transistor in the data storage portion due to the problem of the stability of data retention. In the present embodiment, when the transistor size of the data storage portion is the same, a current approximately one order of magnitude larger than that of the related art can flow.

Next, the operation of the embodiment of the present invention will be described in detail with reference to FIG.

In the example of FIG. 4, the read current is 1 mA.
Let it flow. When the capacitance of the digit line DR for the read operation is 0.5 pF, the potential decreasing speed is dV / dt = I / C = 1 mA / 0.5 pF = 2 V / nS. Assuming that the power supply potential is 3 V, Vcc / 2
The time t for falling is t = (Vcc / 2) / (dV / dt) = 0.75 nS.

[0026]

FIG. 6 is a diagram showing a second embodiment of the present invention. In this embodiment, the read operation control transistor M5 is independently controlled by the read operation word line WLR, and the write operation control transistors M7 and M9 are independently controlled by the write operation word line WLW. This embodiment can be applied to a two-port SRAM.

FIG. 7 shows a second embodiment in which one of two write operation digit lines is shared with a read operation digit line. In this embodiment, only one of the read operation word line WLR and the write operation word line WLW is operated at a high potential. When word line WLR is at a high potential, digit line D operates as a digit line for read operation, and when word line WLW is at a high potential, digit lines D and DWB operate as digit lines for write operation.

FIG. 8 shows an embodiment comprising one digit line for read operation and one digit line for write operation.
The word lines are a WLR for read operation and a WL for write operation.
W. This embodiment can be applied to a two-port SRAM.

FIG. 9 shows an embodiment in which the digit line for read operation and the digit line for write operation are shared in the embodiment of FIG. In the present embodiment, the read operation word line W
Only one of the LR and the write operation word line WLW is operated at a high potential.

[0030]

As described above, the present invention has the following effects. (1) The read current can be increased without deteriorating the stability of the data holding unit of the memory cell. The reason is that the read current does not flow into the data holding unit, so that the read current can be increased without causing a potential change in the data holding unit. (2) The potential of the read operation digit line can be reduced from the power supply potential to the ground potential, and a sense amplifier becomes unnecessary. The reason is that since the read current of the memory cell is large, the digit line potential can be reduced in a short time.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a modification of the first embodiment.

FIG. 3 is an operation waveform diagram of the first embodiment.

FIG. 4 is a circuit diagram of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 5 is an operation waveform diagram of the first embodiment.

FIG. 6 is a circuit diagram of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 7 is a circuit diagram of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 8 is a circuit diagram of a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 9 is a circuit diagram of a semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 10 is a circuit diagram of a conventional example of a semiconductor memory device.

[Explanation of symbols]

M1～M14 MOS transistor WL, WLR, WLW word line D, DB, DR, DW, DWB digit line Y digit line selection signals I, I _1, I ₂ read current Q, nodes QB data holding unit DOB data output RP digit Line pulling p-type MOS transistor drive signal WC write circuit PG pulse generation circuit SA sense amplifier

Claims (5)

[Claims] 1. A semiconductor memory device having a memory cell array composed of a matrix of a plurality of word lines and digit lines and a MOS transistor controlling the digit lines, wherein the memory cell has one digit line for a read operation. A semiconductor memory device, wherein the operation of raising the digit line is performed by applying a one-shot pulse to the MOS transistor at the beginning of a read operation, and the operation of lowering the digit line is performed by the memory cell. . 2. The digit line has one for a read operation and two for a write operation. A read current is supplied to the read operation digit line without causing a current to flow into the data holding unit in the memory cell. 2. A current path through which current can flow.
13. The semiconductor memory device according to claim 1. 3. The word line has two systems for read operation and write operation, and one of the two digit lines for write operation is shared with the digit line for read operation. Semiconductor storage device. 4. The semiconductor memory device according to claim 2, wherein the word line has two systems for a read operation and a write operation, and the digit line has one for a read operation and one for a write operation. 5. The semiconductor memory device according to claim 4, wherein the digit line for write operation is shared with the digit line for read operation.